JPH044595B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a data fast-forwarding method used in an automatic musical instrument performance device such as an automatic piano performance device. An automatic piano performance device is provided with a key driving solenoid and a pedal driving pedal solenoid corresponding to each key and each pedal of the piano, and these solenoids are stored on a cassette tape or floppy disk, etc. The piano is automatically operated based on the performance data provided, and performs automatic piano performance. By the way, in this automatic piano performance device,
If you want to fast-forward data, in an automatic performance device that uses a cassette tape system, you simply need to fast-forward the tape by rotating a mechanism such as a motor at high speed, but in an automatic performance device that uses a storage device such as a floppy disk, Although it is possible to send data on a floppy disk at an extremely fast speed depending on the rotational speed of the disk, the speed is so fast that there is no real sense of how many songs it is. However, when fast-forwarding an automatic performance device, it is desirable that data be sent at approximately the same speed as fast-forwarding a tape; in other words, an appropriate amount of data is sent depending on how long the operator holds down the fast-forward switch. It is necessary. In addition, during fast forwarding, the solenoids that drive each key and each pedal of the piano are driven at a faster speed than during normal performance, so no noise is generated, and the solenoid is not overloaded due to driving at such a fast speed. It is also important to prevent the solenoid from deteriorating and burning out. Therefore, the present invention provides a data fast-forwarding method that can send data stored in a storage means such as a floppy disk at a speed corresponding to the time data of the stored data. At the time when a change in the performance state of the piano is detected, time data obtained by measuring the elapsed time from the previous time when a change in the performance state was detected based on the first clock pulse and performance state data corresponding to the performance state after the change are recorded in the order of progression of the music. When the performance data is reproduced, time measurement based on the first clock pulse is started each time the time data is read out from the storage means in the order in which it is stored, and each time the time data matches the read time data, the time measurement is started. In an automatic piano performance method in which performance state data corresponding to time data is read and supplied to an operator drive unit of the piano to automatically perform the piano, when a fast forward command is received during the reproduction of the performance data, the first clock pulse is applied. is switched to a second clock pulse with a shorter cycle to start time measurement, and each time the measured value matches the time data read from the storage section, the next stored time is read out without reading out the performance state data. It is characterized by reading only data. An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the structure of an automatic piano performance device to which the method according to the present invention is applied. First, an outline of this automatic piano performance device will be explained. First, each key of the keyboard 1 is provided with two key switches and solenoids 2, 2, . . . for driving the keys. In this case, the two key switches provided for each key operate at different timings in response to key operations (details will be described later), and the key drive solenoids 2
is adapted to drive the key when its plunger protrudes from the solenoid 2. Further, a damper pedal, a sostenuto pedal, etc. (together referred to as a pedal device 3) provided on the piano are each provided with a pedal switch and a solenoid 2 for driving the pedal. Key press/release is detected based on the output of each key switch, and key operation speed, that is, key press strength is determined based on the operation interval of the two key switches provided on one key. Furthermore, depression/release of each pedal is detected based on the output of the pedal switch. and,
Performance data is created based on these detection results and written on the disk of the floppy disk device 4. When reproducing the performance data (when performing automatic piano performance), the performance data recorded on the floppy disk device 4 is sequentially read out, subjected to predetermined data conversion, and then supplied to the solenoid drive circuit 5. As a result, the solenoids 2 provided on each key and each pedal are driven based on the performance data, and automatic performance of the piano is performed. The above-mentioned automatic piano performance device will be described in detail below. In FIG. 1, a key switch group 6 is a block showing a set of key switches provided for each key of the keyboard 1. Here, an example of the configuration of two key switches provided corresponding to one key is shown in the second example.
This will be explained with reference to the figures. In this figure, the number 6
a is a key, and below the front end of this key 6a are a first key switch _K1 and a second key switch _K2.
are provided for each. In this case, the first key switch _K1 and the second key switch _K2 each have their tip portions bent upward into a substantially inverted J-shape so that the keys 6a
Movable contacts SK ₁ , which constitute the pressed parts A and B,
SK ₃ and fixed contacts SK ₂ and SK ₄ that are close to the lower surface of the movable contacts SK ₁ and SK ₃ , and the pressed part of the movable contact SK ₁ of the first key switch K ₁ is the second
It is set higher than the pressed portion (b) of the movable contact _SK3 of the key switch _K2 and is close to the lower surface of the key 6a. Therefore, when the operation part of the key 6a is pressed down, the pressed part A first elastically deforms downward and comes into contact with the fixed contact _SK2 , turning the first key switch _K1 on, and then the pressed part B turns on. By elastically deforming downward, the second key switch _K2 is turned on. The pedal switch group 7 is made up of pedal switches provided for each pedal of the pedal device 3, and the output of each pedal switch is supplied to a pedal switch interface 8. The key information generating circuit 9 detects the on/off state of each key switch K ₁ , K ₂ by scanning each key switch K ₁ , K ₂ of the key switch group 6, and according to this detection result, the key code KC ( This circuit outputs key information consisting of keystroke strength data SD (8 bits), keystroke confirmation code KD (1 bit). That is, this key information generation circuit 9 has three shift registers 9a (16 stages, 7 stages) driven by a clock pulse _φ0 .
bit), 9b (16 stages, 8 bits), 9c (16
1 bit). When any key (hereinafter referred to as key A) is pressed anew, the first key switch of key A is pressed.
When _K1 is turned on, the key code KC of key A is transferred to the empty stage of shift register 9a (currently
This empty stage is assumed to be the 10th stage), and the time from the time when the first key switch _K1 of key A is turned on until the second key switch _K2 is turned on, and this Shift register 9 uses the measurement result as keystroke strength data SD
Then, when the second key switch _K2 of key A is turned on, the keystroke confirmation code KD (“1” signal) is written to the shift register 9.
Write to the 10th stage of c. Further, when key A is released, the data at the 10th stage of each shift register 9a to 9c is erased (set to "0") at the time when the first key switch _K1 is turned off. Here, as is clear from the fact that each of the shift registers 9a to 9c described above has a 16 stage configuration, this key information generation circuit 9 allocates key information of a maximum of 16 keys to each stage of the shift registers 9a to 9c. be able to. The key information assigned to each stage of the shift registers 9a to 9c is output to the FI _- FO memory 10 in a time-division manner in accordance with the clock pulse φ ₀ described above. The central processing unit (hereinafter referred to as CPU) 11 is
It controls each part of the apparatus based on a program, and is connected to each part of the apparatus via a bus line 12. ROM (read only memory) 13 is CPU 11
This is a memory that stores programs used in RAM (Random Access Memory)
14 is a region 14a to 14d as shown in FIG.
16K words of memory with 14
Each of a to 14d has a storage capacity of 4K words.
The areas 14a to 14c are used as a buffer memory when writing data to or reading data from the disk of the floppy disk device 4, and the area 14d is used as a working area. The _FI -FO memory 10 is a 16.times.16 bit first-in-first-out memory whose writing/reading is controlled by a memory controller 16. That is, when a write command is supplied from the CPU 11 to the memory controller 16,
The memory controller 16 puts the _FI -FO memory 10 into a writing state. As a result, all data in the shift registers 9a to 9c of the key information generating circuit 9 are transferred to the FI _- FO memory ₁₀ based on the clock pulse φ0.
written to. Furthermore, when a read command is supplied from the CPU 11 to the memory controller 16,
The memory controller 16 puts the _FI -FO memory 10 in a read state. As a result, all data in the FI _- FO memory 10 is transferred to the RAM 14 via the CPU 11.
new data area NDE (third
(Figure). In addition, this F _I -FO memory 1
The reason why 0 is inserted is that the CPU 11 and the key information generation circuit 9 are driven by different (non-synchronized) clock pulses. The pedal switch interface 8 is a circuit that detects the on/off state of each pedal switch in the pedal switch group 7 and outputs pedal data PD corresponding to the detected on/off state. The control signal generation circuit 18 receives a 2MHz clock pulse _φ1 supplied from the basic clock generation circuit 19.
Counting is performed based on the repetition data BD supplied from the CPU 11, and the resulting clock pulse φ ₂ is output to the CPU 11 via the pass line 12. The period of this clock pulse _φ2 is normally 4 msec, but may be 3.5 msec or 3 msec depending on the case.
It is changed to msec, or 200μsec, etc. The operation unit 20 includes switches such as a start switch, a stop switch, a write designation switch for designating writing to the disk of the floppy disk device 4, a read designation switch for designating reading from the disk, and a fast forward switch. The output of each switch is coded,
It is output to the bus line 12. The solenoid drive circuit 5 connects the CPU 11 to the bus line 12 and the output interface 2.
Solenoid drive data supplied via 1
Based on SKD, the period is constant and the same data
A solenoid drive signal having a pulse width corresponding to SKD is created, and this solenoid drive signal is sent via amplifiers 22, 22... to solenoids 2, 2... corresponding to the key code KC or pedal data PD supplied from the CPU 11. supply Next, the operation of the automatic piano performance device configured as described above will be explained. [1] When recording data related to a performer's performance on the disk of the floppy disk device 4. In this case, the player turns on the disk write designation switch provided on the operating section 20, presses the start switch, and thereafter performs normal piano performance using the keyboard 1 and pedal device 3. When start is pressed by the performer,
First, the CPU 11 outputs repetition data BD specifying a 4 msec period to the control signal generation circuit 18. As a result, a clock pulse φ ₂ having a period of 4 msec is thereafter outputted from the control signal generation circuit 18 and supplied to the CPU 11 . The CPU 11 performs the following processes every time the clock pulse φ ₂ is supplied. First, a write command is output to the memory controller 16 to transfer all data in the shift registers 9a to 9c of the key information generation circuit 9 to the F _I -FO memory 10. Next, the data is written in the new data area NDE (FIG. 3) set in the area 14d of the data RAM 14 transferred to the _FI -FO memory 10. Next, pedal switch interface 8
Pedal data PD output from
Write in new data area NDE of RAM14. Next, the data in the timer area TE set in the area 14d of the RAM 14 is set to “1”.
Add. The meaning of this will be explained later. Next, the new data area of RAM14
Data in NDE and area 14d of RAM14
Old data area set in
By comparing the data in ODE,
Changes in the pressed state of the keyboard 1 and the operating state of the pedal device 3 (hereinafter, these changes are referred to as events) are detected. The old data area ODE stores the contents of the shift registers 9a to 9c and the pedal data PD when the clock pulse _φ2 was output last time (4 msec ago). If no event is detected in the above process, the contents of the new data area NDE of RAM14 are transferred to the old data area.
Move to ODE and complete the series of processing. From then on,
The CPU 11 waits for the next clock pulse _φ2 to occur. If an event is detected in the above process, a data group shown in Figure 4 (hereinafter referred to as event frame EF) is created and
14 area 14a. Note that the event frame EF will be described in detail later. Next, if an event is detected, clear the timer area TE. Next, the contents of the new data area NDE are transferred to the old data area ODE, and the series of operations ends. Thereafter, the CPU 11 waits for the next clock pulse _φ2 to occur. The above is the process that the CPU 11 performs every time the clock pulse _φ2 occurs. Here, the data in the timer area TE and the event frame EF described above will be explained. First, as is clear from the process described above, the data in the timer area TE is cleared every time an event occurs, and as is clear from the process described above, the data in the timer area TE is cleared to " ₁ " every time a clock pulse is added. That is,
The data in the timer area TE when an event occurs is from the time when the previous event occurred.
Time until the current event occurs (time with the basic unit of clock pulse φ ₂ period of 4 msec)
It shows. Next, the event frame EF includes the first word count data WD1 and the tie data as shown in Figure 4.
It consists of four data: TD (time data), event data ED (musical sound data), and second word count data WD2. Below, these data will be explained in order. () First word count data WD1 This data indicates the total number of words of the timer data TD and the event data ED. () Timer data TD RAM1 at the time of performing the above processing
This data is stored in the timer area TE of No. 4, and is data indicating the time from the time when the previous event occurred to the time when the current event occurred. Note that this timer data TD is 2
It is a word structure. () Event data ED This data is related to the key or pedal where the event occurred. That is, when a new key is pressed and the second key switch _K2 is turned on, the key code KC (7 bits) of the pressed key, the key-on code (“1”), and 2 consisting of keystroke strength data SD (8 bits) for the same key
The word data becomes event data ED.
Note that the key code KC and keystroke strength data SD are stored in the new data area NDE. Further, when the key is released, as shown in FIG. 5B, one word of data consisting of the key code KC of the released key and the key-off code ("0") becomes event data ED. Further, when any pedal of the pedal device 3 is turned on, one word of data consisting of the pedal data PD and the pedal on code (“1”) becomes the event data ED, as shown in FIG. When the pedal in the on state is turned off, one word of data consisting of the pedal data PD and the pedal off code ("0") becomes the event data ED, as shown in FIG. 5D. Also,
For example, if two keys are turned on at the same time, the two sets of data shown in Figure 5 A become event data ED. For example, if a key and a pedal are turned on at the same time, Figure 5 A and C become the event data ED. The data shown becomes event data ED.
Note that the above-mentioned timer data TD and event data ED are collectively referred to as performance data. () Second word count data WD2 This data is exactly the same as the first word count data WD1. That is, in this embodiment, the same number of words data is added to the beginning and end of the event frame EF. Next, a process in which the above-mentioned event frame EF is written into the area 14a will be specifically explained using an example. Now, for example, at time t ₀ shown in FIG. 6, the start switch is turned on, at time t ₄ the key switch K ₂ of key F ₃ (third octave/F note key) is turned on, and at time t ₈ the key
Key switch K ₂ of G ₃ (third octave/G note) is turned on, and at time t ₁₁ key switch K ₃ is turned on.
Assume that the key switch _K1 of the key F3 is turned off, and the key switch _K1 of the key _F3 is turned off at time _t14 . When the start switch is turned on at time t ₀ , thereafter, the start switch is turned on at time t ₁ , t ₂ , t ₃ every 4 msec.
Although the clock pulse φ ₂ is generated at the time t ₁ to _{t 3} , there is no change in the key depression state and no event is detected. Then, time t ₅
When an event check is performed at
An event is detected because the pressed state of key F ₃ has changed compared to the state of t ₃ , and as a result,
Event frame EF-1 shown in Figure 7 is RAM
14 areas 14a. in this case,
Timer data TD-1 becomes "4" (this data indicates time T ₁ in FIG. 6),
Event data ED-1 is the key code of key F ₃
KC, key-on code "1" and keystroke strength data SD, and first and second word count data WD1-1 and WD2-1 both become "4". Next, an event check is performed at times t ₆ and t ₇ , but no event is detected at these times t ₆ and t ₇ , and therefore no event frame EF is created. Next, the time
When an event check is performed at _t9 , an event is detected because the pressed state of key _G3 has changed, and as a result, the event frame EF-2 shown in FIG.
During this period, the above-mentioned event frame EF-1 is continuously written. Similarly, at time _t12 , an event is detected because the pressed state of key _G3 changes, and as a result, RAM1
The event frame EF-3 shown in FIG. 7 is created in the area 14a of No. 4, and since the pressed state of the key _F3 changes at time _t15 , an event is detected, and this result , an event frame EF-4 shown in FIG. 7 is created. In this manner, in this embodiment, each time an event is detected, performance data (timer data TD and event data ED) is recorded in the area 14a of the RAM 14 in the form of an event frame EF. Then, the area 14a is full
(full), the event frame EF is written into the area 14b of the RAM 14, and the CPU 11 sequentially transfers the data in the area 14a to the floppy disk device 4 via the disk controller 24. The data is supplied to the disk device 4 and written to the disk disk in the disk device 4. Next, when area 14b becomes Full, area 1
An event frame EF is created in area 4c, and data in area 14b is written to the disk. Thus, regions 14a-14c are used for cycling. The above is the process of recording the performance data related to the piano player's performance on the disk in the floppy disk device 4. [2] When performing automatic performance. Next, the operation of the apparatus shown in FIG. 1 when performance data written on the disk of the floppy disk device 4 is read out and automatic piano performance is performed based on the read performance data will be described. In this case, the operator first turns on the disk read designation switch on the operation unit 20, and then presses the start switch. When the start switch is pressed, CPU11
First, download 12K words of data recorded on the disk of floppy disk device 4.
The data is sequentially transferred to areas 14a to 14c of the RAM 14. Next, the CPU 11 outputs the repetition data BD specifying 4 msec to the control signal generation circuit as in the case of data recording described above. As a result, the control signal generation circuit 18 outputs a clock pulse φ ₂ with a period of 4 msec, and the CPU 11
supplied to Thereafter, the CPU 11 processes the data in the areas 14a to 14c based on the clock pulse _φ2 . This processing process will be described below, but for convenience of explanation, the event frames shown in FIG.
Assume that EF-1, EF-2, ... are written. Now, after outputting the repetition data BD specifying a 4 msec period to the control signal generation circuit 18, the CPU 11 outputs the first word count data shown in FIG.
WD1-1 (“4”) and timing data
TD-1 ("4") is read from area 14a of RAM 14 and written to temporary storage area SPE and timer area TE in area 14d, respectively. Thereafter, each time the clock pulse _φ2 is output, "1" is subtracted from the contents of the timer area TE, and the result of this subtraction is written into the timer area TE again. Then, when the content of the timer area TE becomes "0", that is, when the time _T1 shown in FIG. 6 has elapsed, the next process is performed. (a) First word count data WD1-1 stored in temporary storage area SPE of RAM14
The number of words in the timer data TD "2" is subtracted from ("4"). (b) This subtraction result, i.e., event data
Area 1 based on the word count “2” of ED-1
Event data ED-1 from 4a (Figure 7)
and the read event data ED-1
Event data area EDE of area 14d
write to. (c) Read the first word count data WD1-2 ("4") and timer data TD-2 ("3") shown in FIG.
Write each to. When event data ED-1 is written to the event data area EDE in area 14d (the above
(b)), this event data ED-1 (key
Solenoid drive data SKD is created based on the key code KC of key F ₃ , key press strength data SD, and key on code “1”), and the key code of key F _{3 is}
Output Interface 21 with KC
supplied to The output interface 21 receives the supplied solenoid drive data SKD.
and temporarily memorize the key code KC of key F ₃ ,
Also, the memorized data SKD and key code
KC is supplied to the solenoid drive circuit 5. Solenoid drive circuit 5 contains solenoid drive data
Create a solenoid drive signal based on SKD,
It is supplied via an amplifier 22 to a solenoid 2 provided at key F ₃ . As a result, the key _F3 is driven with a strength corresponding to the keystroke strength data SD. From then on, every time the clock pulse _φ2 is output, the timer area TE is
"1" is subtracted from the content (in this case, "3"). And the content of timer area TE is "0"
At the point in time (the point in time when time _T2 shown in FIG. 6 has elapsed), the same process as in the case described above is performed again. That is, (a) the word number "2" of the timer data TD is subtracted from the first word number data WD1-2 ("4"). (b) Area 14 based on this subtraction result (“2”)
Event data ED-2 is read from a,
Written to event data area EDE. (c) First word count data WD1 from area 14a
-3 (“3”) and timer data TD-3
(“2”) is read and written to the temporary storage area SPE and timer area TE, respectively. Then, event data ED-2 (key code KC of key G ₃ ,
When the keystroke strength data SD and key-on code "1") are written, the solenoid 2 provided on the key _G3 is driven based on this event data ED-2. Next, when time T ₃ (Figure 6) corresponding to timer data TD-3 ("2") has elapsed, the same processing as in (a) to (c) above is performed again, and as a result, the timer area Timer data TD-4 to TE
("2") is in the event data area EDE, and event data ED-3 is in the event data area.
First word number data WD1-4 are respectively written to EDE. And the event data area
When event data ED-3 (key code KC of key G ₃ and key off code “0”) is written to EDE, solenoid 2 provided in key G ₃
is turned off. The same process is repeated thereafter, and the piano is automatically played. In the above example, only the driving of the keys on the keyboard 1 has been described, but the driving of the pedals of the pedal device 3 is performed in the same manner. [3] When performing fast forward When the operator presses the fast forward switch provided on the operation unit 20, the CPU 11 first outputs repetition data BD specifying a 200 μsec cycle to the control signal generation circuit 18. As a result, a clock pulse φ ₂ having a period of 200 μsec is outputted from the control signal generation circuit 18 and supplied to the CPU 11 . From then on,
The CPU 11 subtracts "1" from the data in the timer area TE every time the clock pulse φ ₂ is supplied, and returns the subtraction result to the timer area TE.
write to. Then, when the content of timer area TE becomes "0", the next event frame
Read the EF timer data TD and the first word count data WD1 from the area 14a of the RAM 14,
Write to timer area TE and temporary storage area SPE respectively. Thereafter, the above-described operation is repeated every time the clock pulse _φ2 is output. When the timer data TD and first word count data WD1 in area 14a are all processed, timer data TD and first word count data WD1 in areas 14b and 14c are subsequently processed in the same manner. In addition, areas 14a, 1
When data processing in areas 14b and 14c is completed, new data is read from the disk of the floppy disk device 4, and
4c. Then, when the operator presses the stop switch, the above operation is stopped and fast forwarding is completed. Note that in the above operation, the first word count data WD1 is the next timer data.
Used to calculate TD address. In this way, in the case of fast forwarding, areas 14a to 14
The timer data TD and the first word count data WD1 stored in c are read out sequentially in the performance order, and the time indicated by the read timer data TD is
It is measured based on a clock pulse φ ₂ with a period of 200 μsec. As a result, it becomes possible to send the data on the disk of the floppy disk device 4 at substantially the same speed as the fast forwarding of a cassette tape. In this case, the event data ED is from area 14a to
14c and, of course, the piano does not play automatically, so there is no discomfort. As described in detail above, when a fast forward command is received during playback of performance data, the present invention switches the first clock pulse to a second clock pulse with a shorter cycle to start time measurement, and the time value is stored. Each time the time data read from the playback matches the time data read out, only the next stored time data is read out without reading out the performance status data. Data can be sent at approximately the same speed as fast-forwarding data stored on tape. In addition, since the piano does not play automatically during fast-forwarding, the solenoids that drive each key and pedal of the piano are not driven at a faster speed than during normal playback, so automatic fast-forwarding does not generate musical sounds that are unpleasant to the listener. Noise generation from solenoid etc. due to fast forward drive can be prevented. Furthermore, since deterioration and burnout of the solenoid caused by overload driving of the solenoid due to high-speed driving as described above is avoided, the reliability and durability of the solenoid are dramatically improved, which is an extremely excellent effect.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a side sectional view showing the configuration of key switches K ₁ and K ₂ provided on each key of a piano, and FIG.
The figure shows the internal structure of the RAM 14 in Fig. 1, Fig. 4 shows the structure of the event frame EF, Fig. 5 A to D show the format of the event data ED, and Fig. 6 shows the key FIG. 7 is a timing diagram showing an example of an operation, and is a diagram showing data written to the RAM 14 shown in FIG. 1 in response to the key operations shown in FIG. 6. 4... Storage means (floppy disk device),
11...Central processing unit (CPU), 14...Random access memory (RAM), 18...Control signal generation circuit.

Claims (1)

[Claims] 1. When recording performance data, at the time when a change in the performance state of the piano is detected, time data obtained by measuring the elapsed time from the time when a change in the previous performance state was detected based on the first clock pulse and the performance after the change. Performance state data corresponding to the state is stored in the storage unit in the order of progression of the music, and when the performance data is reproduced, time measurement based on the first clock pulse is started each time time data is read out from the storage unit in the storage order, and the time measurement value is In an automatic piano performance method, in which the performance state data corresponding to the time data is read out every time the time data matches the time data read out, and the data is supplied to an operator drive unit of the piano to automatically play the piano, during the playback of the performance data. When a fast forward command is received, the first clock pulse is switched to a second clock pulse with a shorter cycle to start time measurement, and each time the time value matches the time data read from the storage section, the performance state is changed. An automatic piano performance method characterized by reading out only the next stored time data without reading out the data.