JPH0125992Y2 - - Google Patents

Description

[Detailed description of the invention] This invention relates to an automatic musical instrument performance device that automatically plays a musical instrument, such as an automatic piano performance device, for example.
The purpose of this is to record and play back performance data based on externally supplied clock pulses and operation signals. To provide an automatic musical instrument performance device capable of synchronously recording data and synchronously reproducing data.

This invention has a control section, an operation section, and a pulse generation circuit, and the control section is based on a first operation signal output from the operation section and a first clock pulse output from the pulse generation circuit. In an automatic musical instrument performance device that records and plays back performance data, the clock input terminal receives a second clock pulse supplied from the outside, the operation signal input terminal receives a second operation signal supplied from the outside, and the means for selectively supplying one of the first and second clock pulses to the control section; and means for selectively supplying either the first and second operation signals to the control section. It is something that has been established.

An embodiment of this invention will be described below with reference to the drawings. FIG. 1 is a block diagram showing the configuration of an automatic piano performance device according to this invention. It also has a playback function (a function to automatically play the piano). Also,
This automatic piano performance device can not only be used alone, but also be connected to other automatic piano performance devices to record/record performance data based on the clock pulses and operation signals of the other automatic piano performance devices.
It is now possible to play. In the following explanation, when two automatic piano performance devices are connected, the automatic piano performance device that outputs clock pulses and operation signals is the master device, and the automatic piano performance device that receives clock pulses and operation signals is the slave device. It is called a machine.

Below, the main components will be explained first. In FIG. 1, reference numeral 1 denotes a piano keyboard, and each key of this keyboard 1 is provided with a first key switch, a second key switch, and solenoids 2, 2, . . . for driving the keys. In this case, the first and second key switches are turned on at different timings when the keys are operated. That is, when a key is operated, first the first key switch is turned on, and then the second key switch is turned on. The key switch group 3 is a block indicating a set of key switches provided for each key. The key information generating circuit 4 constantly detects the on/off state of each key by constantly scanning the output of each key switch of the key switch group 3. If a new key is pressed, the key code for the same key is
The KC and keystroke strength data SD are written into an internal register, and when the key is released, the keycode KC and keystroke strength data SD written in the same register are erased. The contents of the register are output to the bus line 5. In addition, keystroke strength data
The SD is determined by measuring the time from when the first key switch of each key is turned on until the second key switch is turned on. Further, a plurality of the registers are provided in consideration of the case where a plurality of keys are pressed at the same time.

A CPU (central processing unit) 6 controls each part of the apparatus based on a program stored in a ROM (read only memory) 7, and is connected to each part of the apparatus via a bus line 5. The pulse generation circuit 8 is configured with a counter that counts the basic clock pulse φ ₁ supplied from the basic clock generation circuit 9, and counts the basic clock pulse φ ₂ having a period corresponding to the period data BD supplied from the CPU 6. is generated and output to terminal a of the switching means 10. The switching means 10 is controlled by the output of a master/slave switching switch (hereinafter abbreviated as M/S switching switch) 11.
When the output of the M/S changeover switch 11 is a "1" signal, the common terminal c and terminal a are connected,
In the case of a "0" signal, common terminal c and terminal b are connected. Further, a clock pulse obtained at a clock input terminal 12 is supplied to a terminal a of this switching means 10, and a signal obtained at a common terminal c is outputted to a bus line 5. Note that as this switching means 10, a gate circuit is normally used. The M/S changeover switch 11 uses this automatic performance device as a master device. The M/S switch 11 is switched depending on whether it is used as a slave device, and when the M/S switch 11 is turned on to the master side, a “1” signal is output to the bus line 5, and when it is turned on to the slave side, it is outputted to “0”. A signal is output to bus line 5.

The operation section 13 includes a start switch that is pressed when recording or playing performance data starts, a stop switch that is pressed when recording or playing performance data ends, a recording/playback switch that switches between recording and playing performance data, a fast forward switch, and a fast rewind switch. It is composed of switches and the like, and the output of each switch is encoded and output to the bus line 5 as an operation signal TS. Clock input terminal 1
2 and the operation signal input terminal 14 are terminals used when this automatic performance apparatus is used as a sleep machine.The clock input terminal 12 is supplied with clock pulses from the master machine, and the operation signal input terminal 14 is supplied with clock pulses from the master machine. Operation signals are supplied from the machine. The operation signal supplied to the operation signal input terminal 14 is output to the bus line 5 via the interface circuit 15.

The solenoid drive circuit 16 connects the CPU 6 to the bus line 5 and the output interface 1.
Solenoid drive data supplied via 7
Based on SKD, the period is constant and the same data
Create a solenoid drive signal with a pulse width corresponding to SKD, and use this solenoid drive signal CPU
Output to solenoid 2 corresponding to key address KA supplied from 6.

Next, the operation of the apparatus shown in FIG. 1 will be explained.

[1] Operation when used alone In this case, the operator (or performer)
Turn the changeover switch 11 to the master side. As a result, a "1" signal is output from the M/S changeover switch 11, and is supplied to the CPU 6 via the bus line 5.
are connected. From M/S switch 11
When a "1" signal is supplied to the CPU 6, the CPU 6 receives this "1" signal and enables the operating section 13 and disables the interface circuit 15.

Next, operations for recording performance data and operations for reproducing performance data will be sequentially explained.

[1-1] Operation when recording performance data In this case, the performer turns the recording/playback switch on the operation section 13 to the recording side, presses the start switch, and then uses keyboard 1 to perform normal recording. Play the piano.

When the start switch is pressed, the CPU 6
First, cycle data BD corresponding to a 4 msec cycle is output to the pulse generation circuit 8. As a result, a clock pulse φ ₂ having a period of 4 msec is output from the pulse generating circuit 8 and is supplied to the CPU 6. Thereafter, the CPU 6 performs the following processing every time the clock pulse _φ2 is supplied.

First, the data stored in the register in the key information generation circuit 4 is written into the area 19a (see FIG. 2) of the RAM (random access memory) 19.
Next, the written data and the previous time (4 msec ago)
By comparing the data written in the area 19a, a change in the key depression state of the keyboard 1 (hereinafter, this change is referred to as an event) is detected. for example
When the CPU 6 performs event detection at times t ₁ to _{t 6} every 4 msec as shown in Fig. 3, the key F ₃ (key for the third octave F sound) is turned on at time ta, and the key F ₃ is turned off at time tb. Assuming that, an event is detected at times _t2 and _t5 , and no event is detected at times _t1 , _t3 , _t4 , and _t6 .

If no event is detected, no processing is performed, but if an event is detected, CPU 6
does the following: That is, when a key-on is detected, as shown in FIG. 4A, the key code KC of the pressed key, the key-on code (“1”),
A data block DB consisting of keystroke strength data SD for the same key and time data TD indicating the time from the time when the previous event was detected to the time when the current event is detected is written in the area 19b of the RAM 19. In addition, when a key-off is detected, as shown in Figure 4B, the key code KC of the released key, the key-off code (“0”), and the time from the time when the previous event was detected to the time when the current event is detected. Data block DB consisting of time data TD until RAM1
9 is written in area 19b. In this case, for example, the third
The time data TD at the time of event detection at time _t5 shown in the figure corresponds to time _T1 shown in the figure.

In this way, the CPU 6 performs an event check every 4 msec, and each time an event is detected, the data block DB containing the key code KC whose state has changed, time data, etc. is stored in the area 19b of the RAM 19.
I will write it in. Then, when the area 19b becomes full, the data in the area 19b is sequentially transferred to the floppy disk device 22 via the disk controller 21.
write to the disc. Furthermore, data related to events that occur during this writing are sequentially written into the area 19c of the RAM 19. When the area 19c becomes Full, the data in the area 19c is written on the disk, and new data is written in the area 19b.

[1-2] Operation during playback of performance data In this case, the operator turns the recording/playback switch to the playback side and then presses the start switch.

When the start switch is pressed, the CPU 6
First, data on the disk of the floppy disk device 22 is transferred to areas 19b and 19c of the RAM 19. Next, data block DB-1 at the starting address of area 19b is read and written to area 19a. Here, data block DB-1 is assumed to be the data block DB at key-on shown in FIG. 4A. Thereafter, the CPU 6 measures the time corresponding to the time data TD of the data block DB-1 written in the area 19a. And time data TD
When the time corresponding to
Write in a. Here, data block DB-2 is the data block DB at key-off shown in Fig. 4 (b).
Suppose that After that, CPU6 becomes a data block.
The time corresponding to the time data TD of DB-2 is measured, and the data block DB in area 19a is
-1 key code KC and keystroke strength data SD are processed. In other words, data block DB-1
The keystroke strength data SD is converted according to the characteristics of the solenoid 2, and the resulting solenoid drive data SKD is outputted from the output interface 17 together with the key address KA corresponding to the key. The output interface 17 stores the supplied solenoid drive data SKD and key address KA, and also outputs the stored data SKD and key address KA to the solenoid drive circuit 16.
Output to. This allows the data block DB-
The plunger of solenoid 2 corresponding to the key code KC of 1 is driven at a speed corresponding to the keystroke strength data SD, and the plunger of solenoid 2 drives the key corresponding to the above key code KC, generating the musical tone of the same key. do. Note that the above-described conversion from the keystroke strength data SD to the solenoid drive data SKD is performed based on a conversion table stored in the ROM 7 in advance.

Next, data block DB-2 in area 19a
When the time corresponding to the time data TD elapses,
CPU6 writes the next data block DB from area 19b.
-3 is read and written to area 19a. From then on,
CPU6 is the time data of data block DB-3
Measure the time corresponding to TD. Further, the CPU 6 clears the solenoid drive data SKD stored in the output interface 17 based on the key-off code ("0") and key code KC of the data block DB-2 in the area 19a. As a result, the solenoid drive signal applied to the solenoid 2 corresponding to the key code KC of the data block DB-2 is turned off, and the musical tone of the key stops. Thereafter, the above-described operations are repeated, and automatic piano performance is performed.

[2] Operation when two automatic piano performance devices are connected and used.

The case where these two automatic piano performance devices are operated in conjunction is mainly when playing in ensemble with the two pianos. In other words, when recording performance data for an ensemble of two pianos, if each is recorded by a separate automatic performance device, the clock pulse φ ₂
Due to the slight difference in the period of the , and the slight difference in the point at which the start switch is pressed, it is impossible to record data at a perfect period. Also, during playback, it is almost impossible to press the start switches of two automatic performance devices in perfect agreement.
Therefore, when recording and reproducing performance data related to an ensemble performance of two pianos, it is necessary to use the same operation signal TS and clock pulse _φ2 .

FIG. 5 shows the connection of two automatic piano performance devices in this case, in which the clock pulse φ ₂ output from the pulse generation circuit 8 of the master device M is supplied to the clock input terminal 12 of the scraper S, Further, the operation signal TS output from the operation unit 13 of the master machine M is transmitted to the operation signal input terminal 14 of the scrap machine S.
supplied to Then, the M/S changeover switch 11 of the master machine M is turned on to the master side, and the M/S changeover switch 11 of the slave machine S is turned on to the slave side. M/S changeover switch 11 of the scraper S
is input to the slave side, the "c" signal is output from the M/S changeover switch 11, and as a result, the common terminal c and terminal b of the changeover means 10 of the slave machine S are
are connected. Further, when the "0" signal output from the M/S changeover switch 11 of the slave machine S is supplied to the CPU 6 via the bus line 5, the CPU
6 enables the interface circuit 15 and disables the operating section 13.

From now on, the slave machine S receives the clock pulse _φ2 output from the master machine M and the operation signal TS.
As a result, data recording and data reproduction can be performed in complete synchronization with the master device M.

In this case, the data recording/reproduction operations in the master machine M and the slave machine S are exactly the same as in the case of the single machine described above.

In this case, when the fast-forward switch, fast-reverse switch, etc. provided on the operation unit 13 of the master machine M are operated, fast-forward, fast-reverse, etc. of data on the disk disks of the master machine M and the slave machine S are instructed. be done.

In the above embodiment, the case where two automatic performance devices are connected is described, but three or four automatic performance devices are connected.
Of course, it is also possible to connect automatic performance devices such as the following, and operate each automatic performance device in synchronization.

As explained above, the automatic performance device according to this invention can operate based on clock pulses and operation signals supplied from the outside. As a result, when recording/reproducing performance data relating to an ensemble performance of a plurality of musical instruments, it becomes possible to record and reproduce the performance data of each musical instrument synchronously.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing the configuration of an embodiment of the present invention, FIG. 2 is a diagram showing the storage area of the RAM 19 in FIG. 1, FIG. 3 is a timing chart for explaining event detection, and FIG. 4 is a diagram showing the storage area of the RAM 19 in FIG. A and B are respectively floppy disk devices 22 in FIG.
FIG. 5 is a diagram showing the format of data written on the disk of the present invention, and FIG. 5 is a diagram showing a case where two automatic piano performance devices are connected. 6...Central processing unit (CPU), 8...Pulse generation circuit, 11...M/S changeover switch, 12...
Clock input terminal, 13...operation unit, 14...operation signal input terminal, 15...interface circuit.

Claims (1)

[Scope of utility model registration request] It has a control section, an operation section, and a pulse generation circuit,
In the automatic musical instrument performance device, the control unit records and reproduces performance data based on a first operation signal output from the operation unit and a first clock pulse output from the pulse generation circuit, wherein a clock input terminal for receiving a second clock pulse supplied from the outside; an operation signal input terminal for receiving a second operation signal supplied from the outside; and means for selectively supplying one of the first and second operation signals to the control section.