JPH0460338B2 - - Google Patents
Info
- Publication number
- JPH0460338B2 JPH0460338B2 JP55040885A JP4088580A JPH0460338B2 JP H0460338 B2 JPH0460338 B2 JP H0460338B2 JP 55040885 A JP55040885 A JP 55040885A JP 4088580 A JP4088580 A JP 4088580A JP H0460338 B2 JPH0460338 B2 JP H0460338B2
- Authority
- JP
- Japan
- Prior art keywords
- base
- emitter
- layer
- window
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 21
- 229920005591 polysilicon Polymers 0.000 claims description 21
- 239000012535 impurity Substances 0.000 claims description 17
- 238000004519 manufacturing process Methods 0.000 claims description 11
- 239000000758 substrate Substances 0.000 claims description 9
- 239000004065 semiconductor Substances 0.000 claims description 8
- 238000010438 heat treatment Methods 0.000 claims description 6
- 238000009792 diffusion process Methods 0.000 description 16
- 238000000034 method Methods 0.000 description 13
- 229910004298 SiO 2 Inorganic materials 0.000 description 9
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 description 6
- 230000015572 biosynthetic process Effects 0.000 description 6
- 229910052796 boron Inorganic materials 0.000 description 6
- 238000005530 etching Methods 0.000 description 6
- 229910052751 metal Inorganic materials 0.000 description 6
- 239000002184 metal Substances 0.000 description 6
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 description 5
- 229910052785 arsenic Inorganic materials 0.000 description 5
- RQNWIZPPADIBDY-UHFFFAOYSA-N arsenic atom Chemical compound [As] RQNWIZPPADIBDY-UHFFFAOYSA-N 0.000 description 5
- 230000008569 process Effects 0.000 description 5
- 229910052710 silicon Inorganic materials 0.000 description 5
- 239000010703 silicon Substances 0.000 description 5
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 description 4
- 229910052814 silicon oxide Inorganic materials 0.000 description 4
- 238000000992 sputter etching Methods 0.000 description 4
- 238000007796 conventional method Methods 0.000 description 3
- 238000000206 photolithography Methods 0.000 description 3
- 238000001947 vapour-phase growth Methods 0.000 description 3
- 238000009826 distribution Methods 0.000 description 2
- 238000000605 extraction Methods 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 125000004435 hydrogen atom Chemical class [H]* 0.000 description 2
- 229920002120 photoresistant polymer Polymers 0.000 description 2
- 239000007790 solid phase Substances 0.000 description 2
- OAICVXFJPJFONN-UHFFFAOYSA-N Phosphorus Chemical compound [P] OAICVXFJPJFONN-UHFFFAOYSA-N 0.000 description 1
- 230000002159 abnormal effect Effects 0.000 description 1
- 229910052787 antimony Inorganic materials 0.000 description 1
- WATWJIUSRGPENY-UHFFFAOYSA-N antimony atom Chemical compound [Sb] WATWJIUSRGPENY-UHFFFAOYSA-N 0.000 description 1
- 239000010953 base metal Substances 0.000 description 1
- 239000000969 carrier Substances 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 239000011248 coating agent Substances 0.000 description 1
- 238000000576 coating method Methods 0.000 description 1
- 230000006866 deterioration Effects 0.000 description 1
- 230000002542 deteriorative effect Effects 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 238000001465 metallisation Methods 0.000 description 1
- 238000002156 mixing Methods 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 230000003647 oxidation Effects 0.000 description 1
- 238000007254 oxidation reaction Methods 0.000 description 1
- 229910052698 phosphorus Inorganic materials 0.000 description 1
- 239000011574 phosphorus Substances 0.000 description 1
- 238000001259 photo etching Methods 0.000 description 1
- 230000009467 reduction Effects 0.000 description 1
- 230000007480 spreading Effects 0.000 description 1
- 238000003892 spreading Methods 0.000 description 1
- 239000012808 vapor phase Substances 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/283—Deposition of conductive or insulating materials for electrodes conducting electric current
- H01L21/285—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation
- H01L21/28506—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers
- H01L21/28512—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table
- H01L21/28525—Deposition of conductive or insulating materials for electrodes conducting electric current from a gas or vapour, e.g. condensation of conductive layers on semiconductor bodies comprising elements of Group IV of the Periodic Table the conductive layers comprising semiconducting material
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Bipolar Transistors (AREA)
Description
【発明の詳細な説明】
本発明は半導体装置の製造方法に関し、特に高
周波用バイポーラトランジスタ又は該トランジス
タ素子を含む集積回路装置の製造方法に関するも
のである。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a method of manufacturing a semiconductor device, and more particularly to a method of manufacturing a high frequency bipolar transistor or an integrated circuit device including the transistor element.
高周波特性の良好なバイポーラトランジスタ素
子を実現するためには、微細寸法のパターンを形
成すると共に浅い接合を形成してベース幅を薄く
し、かつベース抵抗及びコレクターベース間容量
を減じる事が重要である。従つて、素子パターン
構造が微細化され拡散窓をそのままオーミツクコ
ンタクト用の窓として用いるいわゆるウオツシユ
ドエミツタ構造等が採られた。しかしながら、か
かる構造ではエミツタ領域が極めて浅く、このた
め電極形成のための金属を被覆するとその金属が
エミツタ・ベース間接合を貫通してしまうことが
生じ易く、このため電極金属膜着と拡散層の間に
ポリシリコン層を介在させる等の改善が施される
様になつてきた。 In order to realize bipolar transistor elements with good high-frequency characteristics, it is important to form microscopic patterns and shallow junctions to thin the base width and reduce base resistance and collector-base capacitance. . Therefore, the element pattern structure has been miniaturized, and a so-called washed emitter structure has been adopted in which the diffusion window is used as an ohmic contact window. However, in such a structure, the emitter region is extremely shallow, and therefore, when the metal for forming the electrode is coated, the metal tends to penetrate the emitter-base junction. Improvements such as interposing a polysilicon layer in between have been made.
第１図は最近のこの種のトランジスタ素子の断
面を概念的に説明するもので、金属電極を施す前
の工程での状態を示す断面図である。例えば、Ｎ
導電型を呈するシリコン半導体基板１の主表面に
ボロン（Ｂ）を熱拡散法により選択拡散さしめて
Ｐ導電型を呈するベース層２を形成し、シリコン
酸化膜（SiO2）等の絶縁膜３で基板表面を被覆
し、このSiO2膜等の絶縁膜３の所定部にエミツ
タ窓を開口した後、砒素（As）等を多量に添加
したポリシリコン層を気相成長等によつて形成
し、写真蝕刻技術を用いてエミツタ窓の部分を含
む様にポリシリコン層４を残し、高温熱処理を通
してポリシリコン層４から不純物（As等）をベ
ース層２の中に拡散移入せしめてエミツタ拡散層
５を形成する。しかる後に絶縁膜（SiO2等）３
のベース電極配着部分にベースコンタクト窓をや
はり写真蝕刻技術を用いて開口し、コンタクト抵
抗低減用のP+層６の熱拡散等の方法でベース層
２内に形成する。このとき、前記不純物添加ポリ
シリコン層４の表面は気相成長SiO2膜等でマス
クされている。 FIG. 1 conceptually explains the cross-section of a recent transistor element of this type, and is a cross-sectional view showing the state in a step before applying a metal electrode. For example, N
A base layer 2 having a P conductivity type is formed by selectively diffusing boron (B) on the main surface of a silicon semiconductor substrate 1 having a conductivity type by a thermal diffusion method, and then an insulating film 3 such as a silicon oxide film (SiO 2 ) is formed. After coating the substrate surface and opening an emitter window in a predetermined part of the insulating film 3 such as this SiO 2 film, a polysilicon layer doped with a large amount of arsenic (As) etc. is formed by vapor phase growth or the like. Using photo-etching technology, the polysilicon layer 4 is left so as to include the emitter window portion, and impurities (such as As) are diffused from the polysilicon layer 4 into the base layer 2 through high-temperature heat treatment to form the emitter diffusion layer 5. Form. After that, insulating film (SiO 2 etc.) 3
A base contact window is opened in the base electrode mounting portion using photolithography, and is formed in the base layer 2 by thermal diffusion of the P + layer 6 for reducing contact resistance. At this time, the surface of the impurity-doped polysilicon layer 4 is masked with a vapor-phase grown SiO 2 film or the like.
ここで、要求される高周波特性を実現するため
に、ベース拡散層２に形成された電極金属とのコ
ンタクト抵抗を低減せねばならないが、前記P+
層６の不純物としてはエミツタ不純物のAsより
拡散波数の大きいＢを用い、エミツタ拡散熱処理
より低温で拡散する事によつて既に形成されたエ
ミツタ・ベース接合を大きく変化しない様にする
のが普通である。このとき、P+層６の深さはベ
ース層２とほぼ同程度以下となる。従つて、ベー
スコンタクト部分も極めて浅いものとなり、ベー
ス金属電極形成工程以後での製品信頼度が低くな
る（メタリゼーシヨンの劣化を生じやすい）、さ
らにエミツタ窓とベースコンタクト窓の位置合せ
作業は微細な寸法であるために難しく、製品歩留
を大幅に低下させる。前述のP+層６をエミツタ
拡散層５形成前に深く形成する事もできるが、こ
の場合エミツタ窓とベースコンタクト窓の位置合
せ作業は一層難しいものとなつてしまうし、ベー
スコレクタ容量も増大する事になり優れた高周波
特性を実現できない。 Here, in order to realize the required high frequency characteristics, the contact resistance with the electrode metal formed in the base diffusion layer 2 must be reduced, but the P +
As the impurity for layer 6, it is common to use B, which has a higher diffusion wave number than the emitter impurity As, and to diffuse it at a lower temperature than the emitter diffusion heat treatment so as not to significantly change the emitter-base junction that has already been formed. be. At this time, the depth of the P + layer 6 is approximately equal to or less than the depth of the base layer 2. Therefore, the base contact portion is also extremely shallow, reducing product reliability after the base metal electrode formation process (metallization is likely to deteriorate), and the alignment work of the emitter window and the base contact window requires minute dimensions. This makes it difficult and significantly reduces product yield. It is also possible to form the aforementioned P + layer 6 deeply before forming the emitter diffusion layer 5, but in this case the alignment work of the emitter window and the base contact window becomes even more difficult, and the base collector capacitance also increases. As a result, excellent high frequency characteristics cannot be achieved.
更に、かかるトランジイタ素子形成するために
は、ボロン（Ｂ）のシリコン（Si）中における拡
散係数は砒素（As）のそれより大きいため予め
ベース層２の不純物濃度を低く抑えてベース層に
於けるＢの濃度勾配を小さくし、エミツタ層形成
のための熱処理の際のAsとの相対的な拡散速度
を低くおさえ、所定のベース幅を得る如くせねば
ならない。従つて、いわゆるベース抵抗が大きく
なり必然的に高周波特性に大きい制約を課し、本
来同一微細度でベース抵抗の小さい場合に実現で
きる高周波特性を劣化している事になる。 Furthermore, in order to form such a transistor element, since the diffusion coefficient of boron (B) in silicon (Si) is larger than that of arsenic (As), it is necessary to suppress the impurity concentration of the base layer 2 to a low level in advance. The concentration gradient of B must be made small, the relative diffusion rate with As during the heat treatment for forming the emitter layer must be kept low, and a predetermined base width must be obtained. Therefore, the so-called base resistance becomes large, which inevitably imposes a large restriction on the high frequency characteristics, deteriorating the high frequency characteristics that could originally be achieved with the same fineness and small base resistance.
本発明は上記に鑑みなされたもので、極めて良
好な高周波特性をもち、製品信頼度の高い安価な
細密パターンをもつバイポーラトランジスタ又は
このトランジスタを含む半導体装置の製造方法を
提供する事を目的とするものである。 The present invention has been made in view of the above, and it is an object of the present invention to provide a bipolar transistor having extremely good high-frequency characteristics, high product reliability, and an inexpensive, fine pattern, or a method for manufacturing a semiconductor device including this transistor. It is something.
本発明によれば、半導体基板の一主表面上に一
導電型のベース領域を形成する工程と、ベース領
域内に凹状にくぼんだベースコンタクト窓及びエ
ミツタ窓を形成する工程と、ベースコンタクト窓
上に一導電型不純物添加ポリシリコン層を、エミ
ツタ窓上に逆導電型不純物添加ポリシリコン層を
それぞれ形成する工程と、加熱処理によつて不純
物をベース領域中に拡散させて一導電型のベース
コンタクト領域及び逆導電型のエミツタ領域を形
成する工程とを含む半導体装置の製造方法を得
る。 According to the present invention, a step of forming a base region of one conductivity type on one main surface of a semiconductor substrate, a step of forming a concave base contact window and an emitter window in the base region, and a step of forming a concave base contact window and an emitter window on the base contact window. A process of forming an impurity-doped polysilicon layer of one conductivity type on the emitter window and an impurity-doped polysilicon layer of the opposite conductivity type on the emitter window, and diffusing impurities into the base region by heat treatment to form a base contact of one conductivity type. A method of manufacturing a semiconductor device is obtained, including a step of forming a region and an emitter region of opposite conductivity type.
以下、本発明の実施例について図面を参照しな
がらより詳細に説明する。 Hereinafter, embodiments of the present invention will be described in more detail with reference to the drawings.
第２図ａ乃至ｃは本発明の一実施例を示す半導
体装置の製造方法を製造工程順に示したもので、
各領域の電極を形成する前までの主要工程断面で
ある。まず、第２図ａの示す様に、例えばＮ導電
型を与える不純物（例えば、アンチモンSb、リ
ンＰ、砒素As）をドーピングしたシリコン基板
１１の一主表面内に通常の選択拡散技術を用いて
ボロン（Ｂ）を熱拡散する等によつてＰ導電型の
ベース層１２を形成し、この後、熱酸化や気相成
長法等によつて形成されたシリコン酸化膜
（SiO2）等の絶縁膜１３で基板１１表面を被覆す
る。 FIGS. 2a to 2c show a method for manufacturing a semiconductor device according to an embodiment of the present invention in the order of manufacturing steps.
This is a cross-section of the main steps up to the time before forming electrodes in each region. First, as shown in FIG. 2a, a conventional selective diffusion technique is used to form a silicon substrate 11 doped with an impurity (for example, antimony Sb, phosphorus P, arsenic As) that provides N conductivity type. A P conductivity type base layer 12 is formed by thermally diffusing boron (B), and then an insulating film such as a silicon oxide film (SiO 2 ) formed by thermal oxidation or vapor phase growth is formed. The surface of the substrate 11 is coated with a film 13.
次いで、該絶縁膜１３上に通常の方法によつて
ベースコンタクト窓（ベース電極取り出し部）２
０及びエミツタ窓（エミツタ電極取り出し部）２
１の部位を除いてフオトレジスト膜（図示せず）
を形成し、その後、これをマスクにして例えばフ
レオン（CF4）及び水素（H2）の混合雰囲気を用
い減圧状態下でプラズマスパツタエツチングして
絶縁膜１３及び基板ベース層１２の表面から所望
の深さまで穿孔する。この際、ベースコンタクト
窓２０及びエミツタ窓２１は同時に開孔するが、
プラズマスパツタエツチング法を用いる事によつ
て極めて微細寸法のパターンについて再現性よく
横方向に拡りのない異方性エツチングができる。
さらに、フレオン及び水素等の混合比（ガス組成
比）を変化する事によつて酸化膜及びシリコンの
エツチング速度比を制御でき、エツチング処理時
間を適当に設定すればベース層１２内への削り込
みは容易に制御できる。この後、エツチングスク
として使用したフオトレジスト膜を通常の方法で
除去すれば第２図ａの状態が得られる。 Next, a base contact window (base electrode extraction part) 2 is formed on the insulating film 13 by a normal method.
0 and emitter window (emitter electrode extraction part) 2
Photoresist film (not shown) except for part 1
Thereafter, using this as a mask, plasma sputter etching is performed under reduced pressure using a mixed atmosphere of Freon (CF 4 ) and hydrogen (H 2 ), for example, to form desired areas from the surfaces of the insulating film 13 and the substrate base layer 12. Drill to a depth of . At this time, the base contact window 20 and the emitter window 21 are opened at the same time,
By using the plasma sputter etching method, it is possible to perform anisotropic etching of extremely fine patterns with good reproducibility without spreading in the lateral direction.
Furthermore, by changing the mixing ratio (gas composition ratio) of freon, hydrogen, etc., the etching rate ratio of the oxide film and silicon can be controlled, and by setting the etching treatment time appropriately, etching into the base layer 12 is possible. can be easily controlled. Thereafter, the photoresist film used as an etching mask is removed by a conventional method to obtain the state shown in FIG. 2a.
次に、第２図ｂの如くエミツタ窓２１及びベー
スコンタクト窓２０を含んで夫々、例えば砒素
（As）を高濃度（例えば1020〜1021／cm3程度）に
添加したポリシリコン層１４及び例えばボロン
（Ｂ）を高濃度（例えば1019〜1020／cm3程度）に
添加したポリシリコン層１６を形成する。具体的
には、700〜800℃にて気相成長法によつてまず
As添加ポリシリコン層１４を基板表面上に形成
し、更にポリシリコン層上にSiO2膜１４′を形成
した後、通常の写真蝕刻技術を用いてSiO2膜１
４′にパターン形成し、これをマスクにAs添加ポ
リシリコン層１４のパターン形成する。次いで他
方の不純物を添加したポリシリコン層１６につい
てこれを繰り返せばよい。無論この逆の場合でも
よい。 Next, as shown in FIG. 2b, a polysilicon layer 14 doped with arsenic (As) at a high concentration (for example, about 10 20 to 10 21 /cm 3 ) including the emitter window 21 and the base contact window 20, respectively. For example, a polysilicon layer 16 doped with boron (B) at a high concentration (for example, about 10 19 to 10 20 /cm 3 ) is formed. Specifically, it is first grown by vapor phase growth at 700 to 800℃.
After forming the As-doped polysilicon layer 14 on the substrate surface and further forming the SiO 2 film 14' on the polysilicon layer, the SiO 2 film 1 is formed using ordinary photolithography.
4' is patterned, and using this as a mask, the As-doped polysilicon layer 14 is patterned. Next, this process may be repeated for the other impurity-doped polysilicon layer 16. Of course, the opposite case may be used.
しかる後、同図ｃのように例えば1000℃程度の
高温熱処理をする事によつてAs及びＢの不純物
を高濃度に添加されたポリシリコン層１４及び１
６から夫々As及びＢが固相拡散によつてベース
層１２中に移入し夫々エミツタN+層１５及びベ
ースコンタクト低減用P+層１７が形成できる。
そして、通常の方法でポリシリコン１４，１６上
のSiO2膜１４′及び１６′を除去する。 Thereafter, as shown in FIG.
As and B from 6 are introduced into the base layer 12 by solid phase diffusion to form an emitter N + layer 15 and a base contact reduction P + layer 17, respectively.
Then, the SiO 2 films 14' and 16' on the polysilicon 14 and 16 are removed using a conventional method.
以降、通常の金属電極形成工程を行なわしめれ
ば、本発明によるバイポーラトランジスタ素子が
形成される。 Thereafter, a normal metal electrode forming process is performed to form a bipolar transistor element according to the present invention.
かかるトランジスタは、ベース層１２の深さを
従来の方法により深くしてもエミツタ形成部のベ
ース層１２が予め薄くなつているので、所定のベ
ース幅を実現するためのエミツタ層１５は浅くて
すむ。エミツタ用不純物の拡散時間は短時間とな
りエミツタ用不純物の濃度分布は急峻なものとな
る。これはエミツターベース接合に於いてベース
不純物との濃度比が大きくなりキヤリアのいわゆ
る注入効率を高くすべく作用する。 In such a transistor, even if the depth of the base layer 12 is increased by the conventional method, the base layer 12 in the emitter formation portion is already thin, so the emitter layer 15 only needs to be shallow to realize a predetermined base width. . The diffusion time of the emitter impurity becomes short and the concentration distribution of the emitter impurity becomes steep. This increases the concentration ratio with the base impurity in the emitter-base junction and acts to increase the so-called injection efficiency of carriers.
一方、トランジスタ素子の性能はベース抵抗に
よつて大きく支配されるが、前述の如く本実施例
のトランジスタではプラズマスパツタエツチング
法を用いており、これによつて極めて微細寸法が
可能となり、エミツタパターンの寸法を極めて細
かく（エミツタ窓寸法て0.8〜1μ程度）容易に再
現性よくできる。このため、エミツタ１５直下の
ベース層抵抗はベース不純物濃度が適当に小さく
抵抗率がやや大きくても、小さな値となる。更に
エミツタ層１５の外側（いわゆる外部ベースと称
されるエミツタ直下を除くベース層の部分）の抵
抗値は、ベース層１２の深さが従来より深くでき
るので非常に小さくなる。特に、ベース層１２を
通常の不純物熱拡散技術によつて形成する場合に
は表面部分に濃度の高い、即ち抵抗率の低い不純
物分布となるのでこの効果は顕著となる。加え
て、ベースコンタクト抵抗低減用のP+層１７は、
やはり予めベース層１２が凹状に削穴されている
ため深い部分から高濃度とする事ができ、同時に
ボロンを高濃度に添加したポリシリコン層１６が
存在するため極めて良好な低抵抗の非整流性接続
を与える様に作用する。さらに、P+層１７の形
成は、本実施例の製造方法ではエミツタ層１５の
形成と同時になされるので、予め各ポリシリコン
層１４及び１６中の添加不純物濃度を適当に、即
ちベース層１２中への不純物固相拡散移入のため
の熱処理時の実現時拡散係数が同程度となる様に
設定しておけば、P+層がコレクタ内に拡大して
ベース−コレクタ間容量を増加することはない。 On the other hand, the performance of a transistor element is largely controlled by the base resistance, but as mentioned above, the transistor of this embodiment uses the plasma sputter etching method, which allows extremely fine dimensions and emitter resistance. Pattern dimensions can be made extremely fine (emitter window dimensions of about 0.8 to 1μ) easily and with good reproducibility. Therefore, the base layer resistance directly under the emitter 15 has a small value even if the base impurity concentration is appropriately small and the resistivity is somewhat high. Furthermore, the resistance value outside the emitter layer 15 (the so-called external base, a portion of the base layer excluding the area immediately below the emitter) becomes extremely small because the depth of the base layer 12 can be made deeper than before. In particular, when the base layer 12 is formed by a normal impurity thermal diffusion technique, this effect becomes remarkable because the impurity distribution is high in concentration, that is, low in resistivity, in the surface portion. In addition, the P + layer 17 for reducing base contact resistance is
As expected, since the base layer 12 is pre-drilled in a concave shape, it is possible to achieve a high concentration from a deep part, and at the same time, since there is a polysilicon layer 16 doped with boron at a high concentration, it has an extremely good non-rectifying property with low resistance. It acts to provide a connection. Furthermore, since the formation of the P + layer 17 is performed at the same time as the formation of the emitter layer 15 in the manufacturing method of this embodiment, the concentration of added impurities in each polysilicon layer 14 and 16 is adjusted in advance, that is, in the base layer 12. If the actual diffusion coefficients during heat treatment for solid phase diffusion of impurities are set to be about the same, the P + layer will not expand into the collector and increase the base-collector capacitance. do not have.
以上の事は全てバイポーラトランジスタ素子の
高周波特性を夫々改善する様に作用することにな
り、本発明によれば著しく良好な高周波特性をも
つたトランジスタ素子又はこの素子を含む集積回
路装置を実現することができる。 All of the above acts to improve the high frequency characteristics of the bipolar transistor element, and according to the present invention, it is possible to realize a transistor element with extremely good high frequency characteristics or an integrated circuit device including this element. Can be done.
さらに、第２図ｃの様に、エミツタ窓２１及び
ベース−コンタクト窓２０には夫々の不純物を高
濃度に含んだポリシリコン層が存在するため、後
続の金属電極形成による接合劣化はなく製品の信
頼度は非常に浅い接合を作るにもかかわらず極め
て安全なものとなる。更に、前述の様に、細密パ
ターンを再現性よく異方性エツチングのプラズマ
スパツタエツチング法によつてエミツタ窓２１及
びベースコンタクト窓２０を同時に開孔した後、
エミツタ層１５及びベースコンタクト抵抗低減用
P+層１７を形成するため、フオトリングラフイ
プロセスに於ける相対的位置合せの問題は著しく
緩和され、P+層１７及びエミツタ層１５の異常
近接による接合不全も全くなくなる。従つて細密
寸度パターンをもつ高周波トランジスタ素子等の
製造歩留を大幅に改善できる。 Furthermore, as shown in FIG. 2c, since the emitter window 21 and the base-contact window 20 each have a polysilicon layer containing a high concentration of impurities, there is no bonding deterioration due to the subsequent formation of metal electrodes, and the product is stable. Reliability is extremely safe despite creating very shallow joints. Further, as described above, after the emitter window 21 and the base contact window 20 are simultaneously opened by the plasma sputter etching method, which is anisotropic etching of a fine pattern with good reproducibility,
For reducing emitter layer 15 and base contact resistance
Since the P + layer 17 is formed, relative alignment problems in the photolithography process are significantly alleviated, and bond failures due to abnormal proximity of the P + layer 17 and the emitter layer 15 are completely eliminated. Therefore, the manufacturing yield of high-frequency transistor elements and the like having fine-grained patterns can be greatly improved.
このように、本発明によれば高周波性能を大幅
に改善すると同時に安価な製造信頼度の高い高周
波バイポーラトランジスタ素子又は該素子を含む
集積回路装置を実現できる。 As described above, according to the present invention, it is possible to realize a high-frequency bipolar transistor element or an integrated circuit device including the element, which greatly improves high-frequency performance, and at the same time is inexpensive and has high manufacturing reliability.
尚、上記実施例でPNP型も同じように適応で
きることは無論である。 It goes without saying that the above embodiments can also be applied to the PNP type.
第１図は改良された従来の高周波用バイポーラ
トランジスタ素子の電極形成前の断面図、第２図
ａ乃至ｃは本発明の一実施例を示す高周波用バイ
ポーラトランジスタを製造工程順に示した断面図
である。
１，１１……Ｎ型シリコン基板、２，１２……
Ｐ型ベース層、３，１３……シリコン酸化膜
（SiO2）、４，１４……砒素（As）高添加ポリシ
リコン層、５，１５……エミツタ領域、６，１７
……電極接触抵抗低減用領域、１６……ボロン
（Ｂ）高添加ポリシリコン層、１４′，１６′……
シリコン酸化膜、２０……ベースコンタクト窓、
２１……エミツタコンタクト窓。
FIG. 1 is a sectional view of an improved conventional high frequency bipolar transistor element before electrode formation, and FIGS. 2 a to 2 c are cross sectional views showing a high frequency bipolar transistor according to an embodiment of the present invention in the order of manufacturing steps. be. 1, 11... N-type silicon substrate, 2, 12...
P-type base layer, 3, 13... Silicon oxide film (SiO 2 ), 4, 14... Arsenic (As) highly doped polysilicon layer, 5, 15... Emitter region, 6, 17
...Region for reducing electrode contact resistance, 16...Polysilicon layer with high boron (B) addition, 14', 16'...
Silicon oxide film, 20...Base contact window,
21...Emitsuta contact window.
Claims (1)
領域を形成する工程と、前記ベース領域内に凹状
にくぼんだベースコンタクト窓及びエミツタ窓を
形成する工程と、前記ベースコンタクト窓上に一
導電型不純物添加ポリシリコン層を、前記エミツ
タ窓上に逆導電型不純物添加ポリシリコン層をそ
れぞれ形成する工程と、加熱処理によつて前記不
純物を前記ベース領域中に拡散させて一導電型の
ベースコンタクト領域及び逆導電型のエミツタ領
域を形成する工程とを含むことを特徴とする半導
体装置の製造方法。1. A step of forming a base region of one conductivity type on one main surface of a semiconductor substrate, a step of forming a concave base contact window and an emitter window in the base region, and a step of forming a base region of one conductivity type on the base contact window. forming a polysilicon layer doped with a type impurity and a polysilicon layer doped with an opposite conductivity type on the emitter window, and diffusing the impurity into the base region by heat treatment to form a base contact of one conductivity type. 1. A method of manufacturing a semiconductor device, comprising: forming a region and an emitter region of opposite conductivity type.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4088580A JPS56135964A (en) | 1980-03-28 | 1980-03-28 | Semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4088580A JPS56135964A (en) | 1980-03-28 | 1980-03-28 | Semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS56135964A JPS56135964A (en) | 1981-10-23 |
| JPH0460338B2 true JPH0460338B2 (en) | 1992-09-25 |
Family
ID=12592958
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4088580A Granted JPS56135964A (en) | 1980-03-28 | 1980-03-28 | Semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS56135964A (en) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5077227A (en) * | 1986-06-03 | 1991-12-31 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method for fabricating the same |
Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227355A (en) * | 1975-08-27 | 1977-03-01 | Hitachi Ltd | Diffusion layer formation method |
| JPS5285481A (en) * | 1976-01-06 | 1977-07-15 | Westinghouse Electric Corp | Transistor |
| JPS5353255A (en) * | 1976-10-26 | 1978-05-15 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5377472A (en) * | 1976-12-21 | 1978-07-08 | Sony Corp | Production of semiconductor device |
| JPS53132275A (en) * | 1977-04-25 | 1978-11-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its production |
-
1980
- 1980-03-28 JP JP4088580A patent/JPS56135964A/en active Granted
Patent Citations (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5227355A (en) * | 1975-08-27 | 1977-03-01 | Hitachi Ltd | Diffusion layer formation method |
| JPS5285481A (en) * | 1976-01-06 | 1977-07-15 | Westinghouse Electric Corp | Transistor |
| JPS5353255A (en) * | 1976-10-26 | 1978-05-15 | Toshiba Corp | Manufacture of semiconductor device |
| JPS5377472A (en) * | 1976-12-21 | 1978-07-08 | Sony Corp | Production of semiconductor device |
| JPS53132275A (en) * | 1977-04-25 | 1978-11-17 | Nippon Telegr & Teleph Corp <Ntt> | Semiconductor device and its production |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS56135964A (en) | 1981-10-23 |
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