JPH0460226B2 - - Google Patents
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- Publication number
- JPH0460226B2 JPH0460226B2 JP59040160A JP4016084A JPH0460226B2 JP H0460226 B2 JPH0460226 B2 JP H0460226B2 JP 59040160 A JP59040160 A JP 59040160A JP 4016084 A JP4016084 A JP 4016084A JP H0460226 B2 JPH0460226 B2 JP H0460226B2
- Authority
- JP
- Japan
- Prior art keywords
- frequency
- frequency conversion
- conversion circuit
- stage
- mixer
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000006243 chemical reaction Methods 0.000 claims description 51
- 239000013078 crystal Substances 0.000 claims description 8
- 229920000729 poly(L-lysine) polymer Polymers 0.000 description 9
- 230000003595 spectral effect Effects 0.000 description 7
- 238000005259 measurement Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 2
- 239000000284 extract Substances 0.000 description 2
- 229910052792 caesium Inorganic materials 0.000 description 1
- TVFDJXOCXUVLDH-UHFFFAOYSA-N caesium atom Chemical compound [Cs] TVFDJXOCXUVLDH-UHFFFAOYSA-N 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 229910052701 rubidium Inorganic materials 0.000 description 1
- IGLNJRXAVVLDKE-UHFFFAOYSA-N rubidium atom Chemical compound [Rb] IGLNJRXAVVLDKE-UHFFFAOYSA-N 0.000 description 1
Description
【発明の詳細な説明】
(A) 発明の技術分野
本発明は、周波数比較器、特に位相ロツクド・
ループ回路を用いた周波数変換回路とミキサとを
有する差周波数拡大器が複数段カスケードに接続
されて構成される周波数比較器において、初段の
周波数変換回路内で用いる電圧制御水晶発振器を
高安定かつ低雑音のものとし、例えば10-9ないし
10-12程度の周波数確度を有する周波数標準器の
特性チエツクに用いるようにした周波数比較器に
関するものである。DETAILED DESCRIPTION OF THE INVENTION (A) Technical Field of the Invention The present invention relates to a frequency comparator, particularly a phase-locked frequency comparator.
In a frequency comparator configured by cascading multiple stages of difference frequency expanders having a frequency conversion circuit using a loop circuit and a mixer, the voltage controlled crystal oscillator used in the first stage frequency conversion circuit is highly stable and low. For example, 10 -9 or
This invention relates to a frequency comparator used to check the characteristics of a frequency standard having a frequency accuracy of about 10 -12 .
(B) 技術の背景と問題点
例えば、高安定水晶発振器やルビジウム原子発
振器やセシウム原子発振器などの超超高安定周波
数標準器においては、10-9ないし10-12程度の周
波数確度を保証することが必要である。このため
にそのような極めて微小な周波数偏差を短時間に
かつ正確に測定することが必要となる。(B) Technical background and problems For example, in ultra-highly stable frequency standards such as highly stable crystal oscillators, rubidium atomic oscillators, and cesium atomic oscillators, frequency accuracy of about 10 -9 to 10 -12 must be guaranteed. is necessary. For this reason, it is necessary to accurately measure such extremely small frequency deviations in a short time.
このような周波数偏差を測定するに当つては、
２つの周波数の差周波数を取出して測定すること
となるが、僅かな周波数の差を拡大した形で検出
する手段として第１図に示す如き構成をもつ差周
波数拡大器が知られている。 When measuring such frequency deviation,
The difference frequency between two frequencies is extracted and measured, and a difference frequency expander having a configuration as shown in FIG. 1 is known as a means for detecting a slight difference in frequency in an enlarged form.
第１図において、１は周波数変換回路であつて
位相ロツクド・ループ回路（以下PLLと略す）
を有するもの、２はミキサ、f0＋△ｆは測定対象
周波数、f0は基準周波数、fx1は変換後周波数、
fb1はミキサ後周波数を表わしている。 In Figure 1, 1 is a frequency conversion circuit, which is a phase-locked loop circuit (hereinafter abbreviated as PLL).
2 is the mixer, f 0 +△f is the frequency to be measured, f 0 is the reference frequency, f x1 is the frequency after conversion,
f b1 represents the frequency after mixer.
図において、周波数変換回路１の変換率を
N1／N2とすると、ミキサ後周波数fb1は
fb1＝f0／N2〔（N2−N1）＋N1（△ｆ／f0）〕
で表わされる。今例えば
f0＝５〔ＭHz〕
△ｆ＝10-3〔Hz〕
N1／N2＝249／250
とすると、ミキサ後周波数fb1は
fb1＝５×106／250〔（250−249）−249（10-3／５×
106）〕
＝５／250×106〔１−249（10-3／５×106）〕
となつて、測定対象周波数f0＋△ｆにおける周波
数偏差△ｆ／f0が251倍に拡大されて検出可能と
なる。即ち２×10-10の偏差が略５×10-8の偏差
として検出可能となる。 In the figure, the conversion rate of frequency conversion circuit 1 is
Assuming that N 1 /N 2 , the post-mixer frequency f b1 is expressed as f b1 =f 0 /N 2 [(N 2 −N 1 )+N 1 (△f/f 0 )]. For example, if f 0 = 5 [MHz] △f = 10 -3 [Hz] N 1 /N 2 = 249/250, the frequency after mixer f b1 is f b1 = 5 × 10 6 /250 [(250-249 )−249(10 -3 /5×
10 6 )] = 5/250×10 6 [1-249 (10 -3 /5×10 6 )] Therefore, the frequency deviation △f/f 0 at the measurement target frequency f 0 +△f is increased by 251 times. It is magnified and becomes detectable. That is, a deviation of 2×10 −10 can be detected as a deviation of approximately 5×10 −8 .
しかし、第１図図示の如き単一の差周波数拡大
器のみでは十分な拡大率を得られないことから、
一般には第２図図示の如く２段接続した構成が用
いられる。 However, since a sufficient magnification cannot be obtained with only a single difference frequency magnifier as shown in FIG.
Generally, a two-stage connected configuration as shown in FIG. 2 is used.
第２図において、符号１，２，f0，f0＋△ｆ，
fx1，fb1は第１図に対応し、３は周波数変換回路
（変換率N3）であつてPLLをもつもの、４はミキ
サ、fx2は変換後周波数、fb2はミキサ後周波数を
表わしている。この場合におけるミキサ後周波数
fb2は
fb2＝f0／N2〔N3（N2−N1）−N2＋N1N3（△ｆ／f0）
〕
で表わされる。そして例えば
f0＝５〔ＭHz〕
△ｆ＝10-3〔Hz〕
N1／N2＝249／250
N3＝251
とすると、ミキサ後周波数fb2は
fb2＝５×106／250〔251（250−249）−250
＋249×251（10-3／５×106）〕
＝５×106／250〔１＋249×251（10-3／５×10
6）〕
となつて、略6.25×104倍に拡大されて検出可能
となる。換言すると、２×10-10の偏差が1.2×
10-5の偏差に拡大して検出可能となる。 In Fig. 2, the symbols 1, 2, f 0 , f 0 +△f,
f x1 and f b1 correspond to Fig. 1, 3 is a frequency conversion circuit (conversion rate N 3 ) with PLL, 4 is a mixer, f x2 is the frequency after conversion, and f b2 is the frequency after mixer. It represents. Frequency after mixer in this case
f b2 is f b2 = f 0 / N 2 [N 3 (N 2 - N 1 ) - N 2 + N 1 N 3 (△f/f 0 )
] It is expressed as . For example, if f 0 = 5 [MHz] △f = 10 -3 [ Hz] N 1 /N 2 = 249/250 N 3 = 251, the frequency after mixer f b2 is f b2 = 5 × 10 6 /250 [ 251(250−249)−250 +249×251( 10-3 / 5 ×106)] =5× 106 /250[1+249×251( 10-3 /5×10
6 )] and becomes detectable after being magnified approximately 6.25×10 4 times. In other words, the deviation of 2×10 -10 is 1.2×
It becomes detectable when the deviation is expanded to 10 -5 .
上述の如き構成によつて周波数偏差を拡大して
検出することが可能となるが、実際には上述の周
波数変換回路１や３においてPLLを用いており、
測定精度は、PLLの同期性やPLL内雑音などの
影響を受け易い。即ち、上述の構成の場合には、
入力の周波数の差分について拡大されるが、周波
数のランダムな「ゆらぎ」も拡大されるために、
PLL内雑音による周波数ゆらぎを防止すること
が望まれる。 Although the configuration described above makes it possible to magnify and detect frequency deviations, in reality, PLLs are used in the frequency conversion circuits 1 and 3 described above.
Measurement accuracy is easily affected by PLL synchronization, noise within the PLL, etc. That is, in the case of the above configuration,
The input frequency difference is magnified, but the random "fluctuations" of the frequency are also magnified, so
It is desirable to prevent frequency fluctuations due to noise within the PLL.
(C) 発明の目的と構成
本発明は上記の点を解決することを目的として
おり、本発明の周波数比較器は、位相ロツクド・
ループ回路を用いた周波数変換回路と当該周波数
変換回路の後段にもうけられるミキサとを有する
差周波数拡大器をそなえ、当該差周波数拡大器を
複数段カスケードに接続して構成した周波数比較
器において、
初段の周波数変換回路が、当該周波数変換回路
中の位相ロツクド・ループ回路に対して、基準周
波数f0に対して偏差した周波数（f0＋△ｆ）（但
し△ｆは正または負の値をもつもの）が供給され
ると共に、当該初段の周波数変換回路の周波数変
換率を（Ｎ−１）／Ｎ（但しＮは正の整数）で与
えるよう構成され、
かつ上記初段の周波数変換回路の後段にもうけ
られる第１のミキサに対して上記基準周波数f0が
供給されるよう構成されてなり、
互に、当該第１のミキサからの出力がフイルタ
を介在せしめて次段の周波数変換回路に供給され
ると共に、位相ロツクド・ループ回路をもつ当該
次段の周波数変換回路の周波数変換率を（Ｎ＋
１）（但しＮは正の整数）で与えられるよう構成
され、
かつ上記次段の周波数変換回路の後段にもうけ
られる第２のミキサに対して上記基準周波数f0が
供給されるよう構成されてなり、
上記初段の周波数変換回路中の上記位相ロツク
ド・ループ回路に存在する電圧制御水晶発振器が
第２段以降の周波数変換回路における電圧制御水
晶発振器にくらべて高安定でつ低雑音の発振器を
用いられていることを特徴としている。以下図面
を参照しつつ説明する。(C) Object and Structure of the Invention The present invention aims to solve the above points, and the frequency comparator of the present invention is a phase-locked frequency comparator.
In a frequency comparator comprising a difference frequency expander having a frequency conversion circuit using a loop circuit and a mixer provided at a subsequent stage of the frequency conversion circuit, the frequency comparator is configured by connecting the difference frequency expanders in multiple stages in cascade. The frequency conversion circuit in the frequency conversion circuit has a frequency (f 0 +△f) that deviates from the reference frequency f 0 (however, △f has a positive or negative value) with respect to the phase-locked loop circuit in the frequency conversion circuit. is supplied, and is configured to give the frequency conversion rate of the first-stage frequency conversion circuit as (N-1)/N (where N is a positive integer), and The reference frequency f 0 is supplied to the first mixer to be produced, and the output from the first mixer is supplied to the next stage frequency conversion circuit through a filter. At the same time, the frequency conversion rate of the next stage frequency conversion circuit having a phase-locked loop circuit is (N+
1) (where N is a positive integer), and is configured so that the reference frequency f 0 is supplied to a second mixer provided at a stage subsequent to the frequency conversion circuit at the next stage. The voltage-controlled crystal oscillator present in the phase-locked loop circuit in the first-stage frequency conversion circuit uses an oscillator with higher stability and lower noise than the voltage-controlled crystal oscillator in the second-stage and subsequent frequency conversion circuits. It is characterized by being This will be explained below with reference to the drawings.
(D) 発明の実施例
第３図は本発明の一実施例構成を示す。図中の
符号１，２，３，４，f0，f0＋△ｆ，fx1，fb1，
fx2，fb2は第２図に対応している。また、６，７
は夫々フイルタを表わしている。(D) Embodiment of the invention FIG. 3 shows the configuration of an embodiment of the invention. Symbols 1, 2, 3, 4, f 0 , f 0 +△f, f x1 , f b1 ,
f x2 and f b2 correspond to FIG. 2. Also, 6,7
each represents a filter.
なお図において周波数変換回路１は恒温槽付電
圧制御水晶発振器を含んでおり、当該変換回路１
内のPLLは、恒温槽を全く使用しない周波数変
換回路３内のPLLにくらべて、本発明にいう高
安定かつ低雑音のものとなつている。またフイル
ム６は周波数｜（fx1−f0）｜成分を抽出し、フイル
ム７周波数｜（fx2−f0）｜成分を抽出するものであ
る。 In the figure, the frequency conversion circuit 1 includes a voltage-controlled crystal oscillator with a constant temperature oven.
The PLL inside is highly stable and has low noise according to the present invention, compared to the PLL inside the frequency conversion circuit 3 which does not use a constant temperature bath at all. Further, the film 6 extracts the frequency |(f x1 −f 0 )| component, and the film 7 extracts the frequency |(f x2 − f 0 )| component.
第３図図示の周波数変換回路１の変換率を
N1／N2＝Ｎ−１／Ｎ
とし、周波数変換回路３の変換率を
N3＝Ｎ＋１
とすると、第２図に関連して述べた如く、ミキサ
後周波数fb2は
fb2＝f0／Ｎ〔１＋（Ｎ−１）（Ｎ＋１）（△ｆ／f0
）〕
となり、周波数偏差は（Ｎ−１）（Ｎ＋１）倍に
拡大された形で検出可能となる。 Assuming that the conversion rate of the frequency conversion circuit 1 shown in FIG. 3 is N 1 /N 2 =N-1/N, and the conversion rate of the frequency conversion circuit 3 is N 3 =N+1, the following equations as described in connection with FIG. As shown, the frequency f b2 after mixer is f b2 = f 0 /N [1+(N-1)(N+1)(△f/f 0
)], and the frequency deviation can be detected in a form expanded by (N-1) (N+1) times.
そして、このように構成した周波数比較器にお
ける測定精度は、ミキサ後周波数fb2の周波数パ
ワースペクトル密度Syb2(f)あるいは短期安定度σy
（τ）（Allan分散の平方根）にもとづいて評価可
能である。第３図図示の場合において、
H1（ω），H2（ω）：周波数変換回路１，３の伝
達関数
F1（ω），F2（ω）：フイルタ６，７の伝達関数
Syi(f)：入力の周波数パワー・スペクトラム密
度
Syb2(f)：出力の周波数パワー・スペクトラム密
度
Syx1(f)：周波数fx1の周波数パワー・スペクトラ
ム密度
S〓a1(f)，S〓a2(f)：周波数変換回路１，３の付加
位相雑音
とするとき、ミキサ後周波数fb2のパワー・スペ
クトル密度Syb2(f)は
Syb2(f)N2（Ｎ＋１）2｛１＋（Ｎ−１／Ｎ）2｜H1
（ω）｜2｝｜F1（ω）｜2Syi(f)＋N2（Ｎ−１）2（Ｎ
＋１）2
（ｆ／f02｜H1（ω）｜2｜F1（ω）｜2S〓a1(f)＋N2（
Ｎ＋１）2（ｆ／f0）2｜H2（ω）｜2｜S〓a2(f)
＋（Ｎ−１）2（Ｎ＋１）2｜１−H1（ω）｜2｜F1（ω
）｜2Syx1(f)＋N2Syi(f)−(A)
で表わされ、また短期安定度σy（τ）は
σ2y（τ）＝2∫∞ 0Syb2(f)sin4（πfτ）／（πfτ
）2df−(B)
で与えられる。上記(A)式において、第２項は周波
数変換回路１によつて付加される雑音であり、第
３項は周波数変換回路３によつて付加される雑音
であつて、
（第２項）（Ｎ−１）2（第３項）
の如き関連がある。また周波数変換回路１の伝達
関数H1（ω）のカツトオフ周波数fc1として
ｆ＞fc1のときには
（第４項）N2（第５項）
の如き関連がある。 The measurement accuracy of the frequency comparator configured in this way is determined by the frequency power spectral density S yb2 (f) of the post-mixer frequency f b2 or the short-term stability σ y
It can be evaluated based on (τ) (square root of Allan variance). In the case shown in Figure 3, H 1 (ω), H 2 (ω): Transfer functions of frequency conversion circuits 1 and 3 F 1 (ω), F 2 (ω): Transfer functions of filters 6 and 7 S yi (f): Frequency power spectral density of input S yb2 (f): Frequency power spectral density of output S yx1 (f): Frequency power spectral density of frequency f x1 S〓 a1 (f), S〓 a2 ( f): Added phase noise of frequency conversion circuits 1 and 3, the power spectral density S yb2 (f) of the frequency f b2 after mixer is S yb2 (f)N 2 (N+1) 2 {1+(N-1 /N) 2 ｜H 1
(ω)｜ 2 ｝｜F 1 (ω)｜ 2 S yi (f)＋N 2 (N-1) 2 (N
+1) 2 (f/f 02 ｜H 1 (ω)｜ 2 ｜F 1 (ω)｜ 2 S〓 a1 (f)＋N 2 (
N+1) 2 (f/f 0 ) 2 | H 2 (ω) | 2 | S〓 a2 (f) + (N-1) 2 (N+1) 2 | 1-H 1 (ω) | 2 | F 1 ( ω
)｜ 2 S yx1 (f)＋N 2 S yi (f)−(A), and the short-term stability σ y (τ) is σ 2 y(τ)=2∫ ∞ 0 S yb2 (f) sin 4 (πfτ)/(πfτ
) 2 df−(B). In the above equation (A), the second term is the noise added by the frequency conversion circuit 1, and the third term is the noise added by the frequency conversion circuit 3, (second term) ( N-1) 2 (paragraph 3). Further, when f>f c1 as the cut-off frequency f c1 of the transfer function H 1 (ω) of the frequency conversion circuit 1, there is a relationship such as (4th term) N 2 (5th term).
第３図図示実施例構成の場合には、周波数変換
回路１が恒温槽付高安定水晶発振器を使用してお
り、このために周波数変換回路３にくらべて高安
定でかつ低雑音のものとなる。したがつて、上記
(A)式で与えられるミキサ後周波数fb2のパワー・
スペクトル密度Syb2(f)からも明らかな如く、当該
パワー・スペクトル密度に大きい影響を与える周
波数変換回路１内のPLLによる付加雑音が低減
され、周波数比較器自体の測定精度を向上させる
ことが可能となつている。発明者の実験によれ
ば、第３図図示のＮとして値「250」程度を選ぶ
ことによつて、100秒間の測定で(E) １×10-13程
度の周波数比較精度を得ることが可能となつた。 In the case of the configuration of the embodiment shown in FIG. 3, the frequency conversion circuit 1 uses a highly stable crystal oscillator with a thermostatic oven, and therefore has higher stability and lower noise than the frequency conversion circuit 3. . Therefore, the above
The power of the mixer frequency f b2 given by equation (A) is
As is clear from the spectral density S yb2 (f), the additional noise caused by the PLL in the frequency conversion circuit 1, which has a large effect on the power spectral density, is reduced, making it possible to improve the measurement accuracy of the frequency comparator itself. It is becoming. According to the inventor's experiments, by choosing a value of about 250 for N as shown in Figure 3, it is possible to obtain a frequency comparison accuracy of about (E) 1 × 10 -13 in 100 seconds of measurement. It became.
発明の効果
以上説明した如く、本発明によれば、100秒間
の測定で１×10-13程度の周波数比較精度を得る
ことが可能となつた。Effects of the Invention As explained above, according to the present invention, it has become possible to obtain a frequency comparison accuracy of about 1×10 −13 in 100 seconds of measurement.
第１図および第２図は夫々本発明の前提とされ
た差周波数拡大器の原理図を示す。第３図は本発
明の周波数比較器の一実施例を示す。
図中、１，３は夫々周波数変換回路、２，４は
夫々ミキサ、６，７は夫々フイルタを表わす。
FIGS. 1 and 2 each show a diagram of the principle of a difference frequency expander, which is the premise of the present invention. FIG. 3 shows an embodiment of the frequency comparator of the present invention. In the figure, 1 and 3 represent frequency conversion circuits, 2 and 4 represent mixers, and 6 and 7 represent filters.
Claims (1)
換回路と当該周波数変換回路の後段にもうけられ
るミキサとを有する差周波数拡大器をそなえ、当
該差周波数拡大器を複数段カスケードに接続して
構成した周波数比較器において、 初段の周波数変換回路が、当該周波数変換回路
中の位相ロツクド・ループ回路に対して、基準周
波数f0に対して偏差した周波数（f0＋△ｆ）（但
し△ｆは正または負の値をもつもの）が供給され
ると共に、当該初段の周波数変換回路の周波数変
換率を（Ｎ−１）／Ｎ（但しＮは正の整数）で与
えるよう構成され、 かつ上記初段の周波数変換回路の後段にもうけ
られる第１のミキサに対して上記基準周波数f0が
供給されるよう構成されてなり、 更に、当該第１のミキサからの出力がフイルタ
を介在せしめて次段の周波数変換回路に供給され
ると共に、位相ロツクド・ループ回路をもつ当該
次段の周波数変換回路の周波数変換率を（Ｎ＋
１）（但しＮは正の整数）で与えられるよう構成
され、 かつ上記次段の周波数変換回路の後段にもうけ
られる第２のミキサに対して上記基準周波数f0が
供給されるよう構成されてなり、 上記初段の周波数変換回路中の上記位相ロツク
ド・ループ回路に存在する電圧制御水晶発振器が
第２段以降の周波数変換回路における電圧制御水
晶発振器にくらべて高安定でかつ低雑音の発振器
を用いられていることを特徴とする周波数比較
器。[Claims] 1. A difference frequency expander including a frequency conversion circuit using a phase-locked loop circuit and a mixer provided at a subsequent stage of the frequency conversion circuit, and the difference frequency expanders are connected in a cascade in multiple stages. In a frequency comparator configured as follows, the first-stage frequency conversion circuit calculates a frequency (f 0 +△f) that deviates from the reference frequency f 0 (with respect to the phase-locked loop circuit in the frequency conversion circuit). Δf has a positive or negative value), and is configured to give the frequency conversion rate of the first stage frequency conversion circuit as (N-1)/N (where N is a positive integer), and is configured such that the reference frequency f 0 is supplied to a first mixer provided after the first stage frequency conversion circuit, and further, the output from the first mixer is provided through a filter. It is supplied to the next-stage frequency conversion circuit, and the frequency conversion rate of the next-stage frequency conversion circuit having a phase-locked loop circuit is set to (N+
1) (where N is a positive integer), and is configured so that the reference frequency f 0 is supplied to a second mixer provided at a stage subsequent to the frequency conversion circuit at the next stage. The voltage-controlled crystal oscillator present in the phase-locked loop circuit in the first-stage frequency conversion circuit uses an oscillator with higher stability and lower noise than the voltage-controlled crystal oscillator in the second-stage and subsequent frequency conversion circuits. A frequency comparator characterized by:
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4016084A JPS60185169A (en) | 1984-03-02 | 1984-03-02 | Frequency comparator |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4016084A JPS60185169A (en) | 1984-03-02 | 1984-03-02 | Frequency comparator |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS60185169A JPS60185169A (en) | 1985-09-20 |
| JPH0460226B2 true JPH0460226B2 (en) | 1992-09-25 |
Family
ID=12573007
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4016084A Granted JPS60185169A (en) | 1984-03-02 | 1984-03-02 | Frequency comparator |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60185169A (en) |
Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5337472A (en) * | 1976-09-18 | 1978-04-06 | Oki Electric Ind Co Ltd | Frequency comparator |
-
1984
- 1984-03-02 JP JP4016084A patent/JPS60185169A/en active Granted
Patent Citations (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5337472A (en) * | 1976-09-18 | 1978-04-06 | Oki Electric Ind Co Ltd | Frequency comparator |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS60185169A (en) | 1985-09-20 |
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