JPH0459783B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a flip-flop using complementary transistors.

FIG. 1 shows a memory cell conventionally used in CMOSRAM. P channel transistor 3,
4, and a flip-flop formed by a loop connection of an inverter consisting of N-channel transistors 5 and 6, data is input/output via N-channel transistors (transfer gates) 1 and 2 whose ON/OFF is controlled by an address line ADR.
BIT, and are connected. When the memory cell is in the read state, the signal is transferred from the flip-flop to the data line, and in the write state, the signal is transferred from the data line to the flip-flop.
Communicate when turned ON. A feature of this CMOS memory cell is that in a stable state, the inverter that makes up the flip-flop requires very little power because it is CMOS, so it requires very little power to retain the data stored in the memory. It consumes less power than N-MOS, and even in the operating state, it consumes less power than N-MOS, and because of its low power operation, it is used in a wide variety of fields.

On the other hand, the disadvantage of this CMOS memory is that its cell size is large, and therefore N-MOS
Compared to RAM, the memory capacity stored on the same chip size is small, making it difficult to increase the capacity. The root cause of this is that, since it is CMOS, space is required to create a P-channel transistor in a plane, and space to create and separate a P ^- well that insulates the N-channel and serves as a substrate.

Conventionally, it has been proposed to reduce the size of the inverter by configuring one of the transistors forming the inverter as a thin film transistor and stacking it on top of the transistor formed on the substrate. Diffusion layers such as the source and drain of the transistor formed in the polycrystalline silicon layer and the source and drain of the transistor formed in the polycrystalline silicon layer were connected using a wiring material such as Al.

When a metal material such as Al is used as the wiring material, the contact hole requires a considerable area, which is not desirable from the viewpoint of high integration.

In order to solve the above problems, the present invention provides the first
In a flip-flop formed on the surface of a substrate and above the substrate, the input and output of two inverters each configured by connecting a conductivity type transistor and a second conductivity type transistor in series between power supplies are cross-connected. The transistor has two first conductivity type impurity-introduced layer regions formed on the surface of the substrate as a source and drain, and the second conductivity type transistor is formed in a polycrystalline silicon layer disposed above the substrate. Two second conductivity type impurity doped regions are used as a source and a drain, and at least one of the inverters is configured to electrically connect one of the first conductivity type impurity doped regions and one of the second conductivity type impurity doped regions. The method is characterized in that a first conductivity type polycrystalline silicon layer is interposed between the two conductivity type connection paths and is connected to partially overlap one of the second conductivity type impurity-introduced regions.

FIG. 2a is a plan view of an embodiment of the flip-flop according to the present invention, and FIG. 2b is a cross-sectional view taken along line AB in FIG. 2a. There are portions that will become source/drain regions within the boundary 18 of the selective oxidation mask. After forming a field film by selective oxidation, growing a gate oxide film, and forming contact holes 10 and 11 for connecting the first layer of polycrystalline silicon to the substrate 30, the first
Layer polycrystalline silicon 19, 20, 21, 27
After depositing (shaded pattern),
Source/drain 3 by implanting P ions into the entire surface
1, 32, 33 are formed. Thereafter, a second field film 36 is deposited, the second field film on the polycrystalline silicon 19, 20 that will become the gate is removed, and the polycrystalline silicon 19, 20 is thermally oxidized to form a gate insulating film of the thin film transistor. Form. After that, contact holes 12, 13, and 14 are opened to connect the first layer and the second layer of polycrystalline silicon, and the second layer of polycrystalline silicon 22, which forms the channel, source, and drain of the thin film transistor, is opened. 23 (pattern of dots) is deposited and selectively P ⁺ diffused. Furthermore, after depositing the third field film 35 and opening the contact holes 15 and 16, the Al-Si layer 24 and
25 and 26 are formed. As a result, N ⁺ diffusion layer 31
In the polycrystalline silicon layer 22, an N-channel transistor has a source connected to the (-) power supply V _SS , a drain 32, and a gate of the polycrystalline silicon 20, and a source 55 connected to the (+) power supply V _DD , and a channel 54. , drain 56, polycrystalline silicon 20
A CMOS flip-flop can be constructed in which a P-channel transistor is formed with the gate as the gate, and each drain is connected via a diode.

FIG. 5 shows a circuit diagram of the cell pattern shown in FIG. 2. N-channel transistors 40 to 43 are formed in bulk silicon single crystal, and P-channel transistors 44 and 45 are formed as polycrystalline thin film transistors. Diodes 46 and 47 are polycrystalline silicon diodes that occur at the connection point between the P channel and N channel transistors, and by interposing an N ⁺ polycrystalline silicon layer that is polymerized with the P ⁺ polycrystalline silicon layer, these diodes can be The diode is formed by partially overlapping polycrystalline silicon layers, and has a large leakage current and a large junction area, so it has low resistance and does not interfere with the operation of flip-flops or silicon memories.

In general, it is known that polycrystalline silicon layers have extremely low mobility and poor transistor characteristics compared to single-crystalline silicon, and in particular have a large OFF leakage current. However, as a result of our efforts to improve this characteristic, the inventors discovered the following. As shown in Figure 3, the deposition temperature of polycrystalline silicon was set to 700℃.
The mobility was improved when the temperature was lower than ℃, and a characteristic close to 10 was obtained especially near 500℃. In addition, improving OFF leakage depends on the manufacturing method of the gate film, which is made by thermally oxidizing polycrystalline silicon, and dry oxidation at high temperature is the best method. Furthermore, even if the deposition temperature of the polycrystalline silicon layer is high, it is possible to improve mobility and OFF leakage by performing laser annealing.

Figure 4 shows the process of depositing polycrystalline silicon at 500°C, then lightly doping P ions into the channel area by ion implantation, and forming a gate oxide film.
Characteristics of transistors of the same size as those used in memory cells formed at 1100°C.
The properties are sufficient for memory applications.

With the above configuration, a metal material such as Al is not used as a wiring material, so a large contact hole is not required, and the size of the semiconductor device can be reduced.

Furthermore, at least one of the inverters is arranged between one of the impurity-doped regions of the first conductivity type and one of the impurity-doped regions of the second conductivity type, between the electrical connection path between the one of the impurity-doped regions of the second conductivity type. A PN junction between the polycrystals is formed by interposing a first conductivity type polycrystalline silicon layer that is partially overlapped and connected. A PN junction between polycrystals is a PN junction formed between single crystal silicon, or
Since the leakage current is larger than that of a PN junction made of polycrystalline silicon and single crystal silicon, it has the effect of reducing voltage drop.Furthermore, since the PN junctions of polycrystalline silicon are formed by polymerization, the junction area is small. This has the effect of reducing voltage drop.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of a CMOSRAM. FIG. 2a is a plan view of an embodiment of the flip-flop according to the present invention, and FIG. 2b is a sectional view. FIG. 3 is a diagram showing the relationship between the mobility of polycrystalline silicon and the deposition temperature, and FIG. 4 is a diagram showing the characteristics of a polycrystalline silicon transistor obtained according to the present invention. Fifth
The figure is a circuit diagram of FIG. 2. 10, 11, 12, 13, 14, 15, 16...
...Contact hole, 19, 20, 21, 27...
...First layer polycrystalline silicon, 22, 23... Second layer polycrystalline silicon, 30... Substrate, 31,
32, 33...source/drain, 54...channel, 55...source, 56...drain.

Claims (1)

[Claims] 1. Inputs and outputs of two inverters each configured by connecting a first conductivity type transistor and a second conductivity type transistor in series between power supplies are cross-connected, and are formed on the surface of a substrate and above the substrate. In the flip-flop, the transistor of the first conductivity type uses two impurity-introduced layer regions of the first conductivity type formed on the surface of the substrate as a source and drain, and the transistor of the second conductivity type is arranged above the substrate. two impurity-introduced regions of the second conductivity type formed in the polycrystalline silicon layer formed in the polycrystalline silicon layer are used as a source and a drain;
Connected between one of the impurity-introduced regions of the conductivity type and one of the impurity-introduction regions of the second conductivity type, partially overlapping with one of the impurity-introduction regions of the second conductivity type. A flip-flop characterized in that a polycrystalline silicon layer of a first conductivity type is interposed.