JPH0459699A - Production of longitudinal semiconductor superlattice - Google Patents

Production of longitudinal semiconductor superlattice

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Publication number
JPH0459699A
JPH0459699A JP17115490A JP17115490A JPH0459699A JP H0459699 A JPH0459699 A JP H0459699A JP 17115490 A JP17115490 A JP 17115490A JP 17115490 A JP17115490 A JP 17115490A JP H0459699 A JPH0459699 A JP H0459699A
Authority
JP
Japan
Prior art keywords
growth
superlattice
gaas
terrace
longitudinal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17115490A
Other languages
Japanese (ja)
Inventor
Yasuto Kawahisa
川久 慶人
Atsushi Kurobe
篤 黒部
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Toshiba Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Toshiba Corp filed Critical Toshiba Corp
Priority to JP17115490A priority Critical patent/JPH0459699A/en
Publication of JPH0459699A publication Critical patent/JPH0459699A/en
Pending legal-status Critical Current

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Abstract

PURPOSE:To reproducibly and uniformly obtain the subject longitudinal semiconductor superlattice by alternately supplying raw material gases respectively containing an element constituting a semiconductor crystal layer to a base plate for growth. CONSTITUTION:A respectively prescribed amount of trimethylgallium and trimethylaluminium are initially alternately supplied onto a GaAs base plate 11 in order and Al and Ga atom planes are grown on a terrace 11a of the base plate crystal surface in the lateral direction to the step. Arsine (AsH3) is then supplied thereto to grow GaAs:15 and AlAs:14. According to the above- mentioned method, AlAs and GaAs are grown in order and a longitudinal superlattice is formed. As a single atom layer growth method where raw materials are alternately supplied is used in the above-mentioned method, deposition of Al on the next terrace can entirely be prevented in growth of GaAs on the remaining terrace part without requirement of accurate control of the growth conditions such as the supply of trimethylgallium, the growth pressure and the growth temperature. An ideal longitudinal superlattice can be formed therefor.

Description

【発明の詳細な説明】 〔発明の目的〕 (産業上の利用分野) 本発明は1次元トランジスタ、あるいは量子井戸細線構
造を有する低発振しきい値レーザに用いられる縦型半導
体超格子の製造方法に関する。
[Detailed Description of the Invention] [Object of the Invention] (Industrial Application Field) The present invention provides a method for manufacturing a vertical semiconductor superlattice used in a one-dimensional transistor or a low oscillation threshold laser having a quantum well thin wire structure. Regarding.

(従来の技術) 従来の超格子(2次元超格子)のもつ成長方向のポテン
シャルV(Z)に加え、面内方向にも人工的なポテンシ
ャルV (x + y )を加えることによって、量子
細線のような構造が形成されれば、従来の超格子では得
られなかった新たな物性や、超高速トランジスタや、超
低しきい値レーザを実現できる可能性が指摘されている
(例えばH,5akaki他、Jpn、 J、 App
l、 Phys、 28 L、31.4 (1989)
)。
(Prior art) In addition to the potential V (Z) in the growth direction of a conventional superlattice (two-dimensional superlattice), by adding an artificial potential V (x + y) in the in-plane direction, quantum wire It has been pointed out that if a structure such as et al., Jpn, J, App
I, Phys, 28 L, 31.4 (1989)
).

成長面内に微細な同期構造を作り込むための最とも有力
な方法は、ミスオリエンテーションのあるオフ基板表面
の周期的な原子ステップ上にGaAsトAQAsを交互
に堆積する方法である(P、M。
The most promising method for creating fine synchronous structures in the growth plane is to deposit GaAs and AQAs alternately on periodic atomic steps on the off-substrate surface with misorientation (P, M .

Petroff他、Appl、 Phys、 Lett
、 45620 (+984))、この方法では、面内
方向の周期Lxは平均テラス長aXcotα (ただし
aは半導体1分子層厚2.83人、αはオフアングル)
で与えられる。最近この方法によって100人オーダの
周期構造を有するプレーナ超格子構造が、MBE (分
子線エピタキシャル法)(J、 M、 Ga1nes他
、J、 Vac、 Sci & Technol、 8
6゜1378 (+988))およびMOCVD (有
機金属気相成長法)(T、 Fukui、 Appl、
 Phys、 Lett 50. 、!124 (19
87))によって作製された。ただし、従来のMBEま
たはMOCVDで縦型超格子を成長させる際は、成長速
度を低くし、かつ超格子を形成する複数の半導体層を交
互に成長した時の成長量を正確に1分子層相当量に制御
する必要がある。。成長量が1分子層相当量よりわずか
にずれても、縦型超格子は大きく傾くことが言われてい
る。例えばiAsとGaAsからなる縦型超格子を例に
とると、第3図に示す様に縦型超格子の傾き角をβとし
、基板の傾き角をθとすると、tanβ=(1−(m 
+ n ))/lan fjが成立する。ここでmとn
は、(AQAs)m(6aAs)nの指数m、nである
。よってm+n=1のとき、すなわち隣のテラスにはみ
出すことなくテラス上全面に正確に1分子層のAQ、A
sとGaAsを成長させた場合はβ=O度となる。しか
し例えばθ=2°てm+n=】、05であるとβ#55
°にもなってしまう。m+n=1.05は5例えばGa
As 1分子が次のテラス上へ堆積した場合に相当する
Petroff et al., Appl, Phys, Lett
, 45620 (+984)), in this method, the period Lx in the in-plane direction is the average terrace length aXcotα (where a is the thickness of one semiconductor molecule layer, 2.83, and α is the off-angle).
is given by Recently, a planar superlattice structure with a periodic structure on the order of 100 nanometers has been produced by this method using MBE (Molecular Beam Epitaxial Method) (J, M, Ga1nes et al., J, Vac, Sci & Technol, 8).
6°1378 (+988)) and MOCVD (Metalorganic Chemical Vapor Phase Deposition) (T, Fukui, Appl.
Phys, Lett 50. ,! 124 (19
87)). However, when growing a vertical superlattice by conventional MBE or MOCVD, the growth rate is lowered and the amount of growth when multiple semiconductor layers forming the superlattice are grown alternately is precisely equivalent to one molecular layer. The amount needs to be controlled. . It is said that even if the growth amount deviates slightly from the amount equivalent to one molecular layer, the vertical superlattice tilts significantly. For example, taking a vertical superlattice made of iAs and GaAs as an example, if the tilt angle of the vertical superlattice is β and the tilt angle of the substrate is θ, then tanβ=(1−(m
+ n ))/lan fj holds true. Here m and n
are the exponents m and n of (AQAs)m(6aAs)n. Therefore, when m+n=1, that is, exactly one molecular layer of AQ, A is spread over the entire surface of the terrace without overflowing to the adjacent terrace.
When s and GaAs are grown, β=0 degrees. However, for example, if θ=2° and m+n= ], 05, then β#55
It also becomes °. m+n=1.05 is 5, for example Ga
This corresponds to the case where one As molecule is deposited onto the next terrace.

従来のMBEあるいはMOCVDにより縦型超格子の構
造を制御するためには、成長時間および原料供給量を精
度良く制御する必要がある。しかし、次のテラスへの析
出を抑制しかつテラス全面に異なる半導体層を1分子層
順次成長させるためには、MBEにおいては、ソース充
填されているクヌードセンセルの温度制御が、またMO
CVDにおいては、原料流量制御に難がある。このよう
に、従来の技術では不可能ではないが、再現性良く、縦
型超格子を作製することが難しいという問題があった。
In order to control the structure of a vertical superlattice by conventional MBE or MOCVD, it is necessary to precisely control the growth time and the amount of raw material supplied. However, in MBE, in order to suppress precipitation on the next terrace and to grow different semiconductor layers one molecular layer sequentially over the entire terrace surface, it is necessary to control the temperature of the Knudsen cell filled with the source.
In CVD, there are difficulties in controlling the flow rate of raw materials. As described above, although it is not impossible using conventional techniques, there is a problem in that it is difficult to produce a vertical superlattice with good reproducibility.

(発明が解決しようとする課題) 上記従来のMBE法およびMOCVD法を用いて縦型超
格子を形成するためには、原料の供給量を高精度に制御
しなければならず、再現性良く、しかも、例えば2イン
チウェハ全面に均一に縦型超格子を成長させることが困
難であるという問題があった。
(Problems to be Solved by the Invention) In order to form a vertical superlattice using the above-mentioned conventional MBE method and MOCVD method, the amount of raw material supplied must be controlled with high precision, and the Moreover, there is a problem in that it is difficult to uniformly grow a vertical superlattice over the entire surface of a 2-inch wafer, for example.

この発明は上記従来の成長法の問題点に鑑みて改良され
た縦型超格子の作成方法を提供することを目的とするも
のである。
It is an object of the present invention to provide an improved method for creating a vertical superlattice in view of the problems of the conventional growth methods described above.

〔発明の構成〕[Structure of the invention]

(課題を解決するための手段) 本発明に係る縦型半導体超格子の製造方法は、成長容器
内に結晶の指数面が(100)、(I ]、 I )、
または(110)等から所定の方位に傾いた基板を配置
し、その結晶面上に二種類以上の半導体結晶層を順次単
分子層成長させて縦型半導体超格子を形成するに際し、
単導体結晶層の構成元素を含む原料カスを交互に成長容
器に導入し前記基板の結晶面上に単原子層成長法により
半導体超格子を形成することを特徴とする。
(Means for Solving the Problems) A method for manufacturing a vertical semiconductor superlattice according to the present invention is such that the index plane of the crystal is (100), (I ], I ),
Or, when a vertical semiconductor superlattice is formed by arranging a substrate tilted in a predetermined direction from (110), etc., and growing two or more types of semiconductor crystal layers in monolayer sequentially on the crystal plane,
The method is characterized in that raw material scraps containing constituent elements of a single conductor crystal layer are alternately introduced into a growth container to form a semiconductor superlattice on the crystal plane of the substrate by a single atomic layer growth method.

(作 用) 本発明によれば、原料ガスを交互に被成長基板上に供給
することにより、この被成長基板上に再現性良く、しか
も均一に縦型半導体超格子を作製することができる。
(Function) According to the present invention, by alternately supplying raw material gas onto the growth substrate, a vertical semiconductor superlattice can be uniformly produced on the growth substrate with good reproducibility.

本発明の作用につきGaAs/AQAsの縦型超格子を
例に第1図を参照して説明する。
The operation of the present invention will be explained using a GaAs/AQAs vertical superlattice as an example with reference to FIG.

まず、GaAs (100) 2°off基板(off
方向(110))11上に一定量のトリメチルガリウム
(TMG)とトリメチルアルミニウム(TMA)を順次
交互に供給し、基板結晶表面のテラス部上11a上にス
テップより横方向にAQおよびGa原子面を成長させる
(第1図(a))。
First, a GaAs (100) 2°off substrate (off
A certain amount of trimethyl gallium (TMG) and trimethyl aluminum (TMA) are sequentially and alternately supplied in the direction (110)) 11, and AQ and Ga atomic planes are formed laterally from a step on the terrace portion 11a of the substrate crystal surface. grow (Fig. 1(a)).

次に、アルシン(ASHJ)を供給し、GaAs15お
よびAQAs14を成長させる(第1図(b))。部上
の如くして順次^ρAsとGaAsを成長させ、第1図
(b)に示す様な縦型超格子を作成させる。原料を交互
に供給する単原子層成長法(Atomj、c Laye
r Epitaxy) %用いるため、例えば第1図(
b)に示すようにGaAsを残りのテラス部に成長させ
る際、TMGの供給量、成長圧力、成長温度等の成長条
件を正確に制御しなくても、次のテラス上へのAQの堆
積は全く生ぜず、第1図(b)に示す様に理想化された
縦型超格子を作成することが可能となる。この様に、従
来の成長法では作成することが困難であった理想的な縦
型超格子を作成することが可能となる。
Next, arsine (ASHJ) is supplied to grow GaAs15 and AQAs14 (FIG. 1(b)). By growing ρAs and GaAs sequentially as described above, a vertical superlattice as shown in FIG. 1(b) is created. Monoatomic layer growth method (Atomj, c Laye) in which raw materials are alternately supplied
r Epitaxy) %, for example, in Figure 1 (
As shown in b), when growing GaAs on the remaining terraces, AQ can be deposited on the next terrace without accurately controlling the growth conditions such as TMG supply amount, growth pressure, and growth temperature. This makes it possible to create an idealized vertical superlattice as shown in FIG. 1(b). In this way, it is possible to create an ideal vertical superlattice, which has been difficult to create using conventional growth methods.

(実施例) 以下この発明の一実施例として、傾斜基板上へのGaA
s/AQAs縦型超格子の作製について第1図および第
2図を参照して説明する。基板にはGaAs(100)
2°オフ基板11を用いた。オフの方向は((111)
である。GaK料にはトリメチルガリウム(TMG)を
、AQ原料にはトリメチルアルミニウム(TMA)を、
As原料にはアルシン(AsH,)を用いた。成長容器
]02に基板11をサセプタ103上に載置して内装し
、加熱コイル105によって高周波加熱を施し、表面の
熱処理ならびにバッファ層のGaAsを成長温度650
℃で成長させた後、成長温度を500°Cに設定し、ガ
ス導入口104より水素をキャリアカスとしてTMAを
1.2μmol導入する。その後H2置換を行なった後
、ガス導入口104よりTMGを0.3μmolμm型
る。次にH2置換を行なった後、カス導入口104より
AsH,をH2をキャリアガスとして150μmol導
入する、その後H2置換を行う。この成長プロセスを1
サイクルとし、1800サイクルの成長を行なった。1
サイクルとはすなわち、丁NA導入/H2置換/ TM
G導入/H2置換/AsH3導入/H2置換、六つのカ
ス導入プロセスに相当している。なお、成長圧力は3 
Torrに設定した。なお、成長容器102内は、ガス
排出口106から排気を施し上記設定条件とした。
(Example) As an example of the present invention, GaA on an inclined substrate will be described below.
The fabrication of the s/AQAs vertical superlattice will be explained with reference to FIGS. 1 and 2. The substrate is GaAs (100)
A 2°-off substrate 11 was used. The off direction is ((111)
It is. Trimethylgallium (TMG) is used as the GaK material, trimethylaluminum (TMA) is used as the AQ material,
Arsine (AsH, ) was used as the As raw material. Growth container] 02 is equipped with a substrate 11 placed on a susceptor 103, and high-frequency heating is performed by a heating coil 105 to heat treat the surface and grow GaAs in the buffer layer at a growth temperature of 650.
After growth at .degree. C., the growth temperature is set at 500.degree. C., and 1.2 .mu.mol of TMA is introduced from the gas inlet 104 using hydrogen as a carrier gas. Thereafter, after performing H2 substitution, 0.3 μmol μm of TMG is introduced from the gas inlet 104. Next, after performing H2 replacement, 150 μmol of AsH is introduced from the waste inlet 104 using H2 as a carrier gas, and then H2 replacement is performed. This growth process 1
Growth was performed for 1800 cycles. 1
The cycle is: NA introduction/H2 substitution/TM
This corresponds to six waste introduction processes: G introduction/H2 substitution/AsH3 introduction/H2 substitution. In addition, the growth pressure is 3
It was set to Torr. The inside of the growth container 102 was evacuated from the gas exhaust port 106 to meet the above set conditions.

この様にして成長した薄膜結晶の膜厚は約5100人で
あり、1サイクル当りの成長膜厚は1分子層に相当して
いた。またX線回折から得られる超格子の回折角より、
超格子周期が原子ステップの間隔に一致していた。さら
にTEM[lからも傾斜のない理想化された縦型超格子
が作成されていることが確認された。なお本実施例にお
いては、GaAs0.5分子、−4QAs0.5分子層
の縦型超格子の作成例を示したか、例えば導入するTM
Aの供給量を変化させることにより、GaAs m分子
層、AQAs n分子層(m+n=1)の縦型超格子を
作成することかできる。また本実施例では1分子層を形
成する間に2種の半導体層を交互に成長させたが、単原
子層成長法により3種類以上の半導体を順次成長させ、
3種類以上の半導体から成る縦型超格子を形成すること
も可能である。
The thickness of the thin film crystal grown in this manner was about 5100, and the film thickness grown per cycle was equivalent to one molecular layer. Also, from the diffraction angle of the superlattice obtained from X-ray diffraction,
The superlattice period matched the atomic step spacing. Furthermore, it was confirmed from TEM [l] that an idealized vertical superlattice with no tilt was created. In this example, an example of creating a vertical superlattice of 0.5 molecules of GaAs and 0.5 molecules of -4QAs is shown.
By changing the amount of A supplied, a vertical superlattice of m molecular layers of GaAs and n molecular layers of AQAs (m+n=1) can be created. Furthermore, in this example, two types of semiconductor layers were grown alternately while forming one molecular layer, but three or more types of semiconductors were grown sequentially by a monoatomic layer growth method.
It is also possible to form a vertical superlattice consisting of three or more types of semiconductors.

〔発明の効果〕〔Effect of the invention〕

本発明に係る縦型半導体超格子の作製方法は、結晶の指
数面が(1,00)、(111)または(] 10)等
から所定の方位に傾いた基板結晶表面上に2種類以上の
半導体結晶層を順次単分子層成長させ、雄型半導体超格
子を作成する際、前記半導体層の構成元素を含む原料ガ
スを交互に被成長基板上に供給することにより、この基
板上に再現性良く、均一に縦型半導体超格子を製造する
ことができる顕著な効果がある。
In the method for manufacturing a vertical semiconductor superlattice according to the present invention, two or more kinds of crystals are formed on a substrate crystal surface whose index plane of the crystal is tilted in a predetermined direction from (1,00), (111), or (]10), etc. When a male semiconductor superlattice is created by sequentially growing monomolecular layers of semiconductor crystal layers, a source gas containing the constituent elements of the semiconductor layer is alternately supplied onto the substrate to be grown. There is a remarkable effect that a vertical semiconductor superlattice can be manufactured in a good and uniform manner.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図(a)、(b)はいずれも本発明の詳細な説明す
るための図、第2図は本発明の一実施例に用いられる気
相成長装置の要部を示す図、第3図は、縦型超格子の傾
き角βの説明するための図である。 11・GaAs基板、lla・・・基板のテラス、12
−GaAs、13−AQAso (b) 代理人 弁理士 大 胡 典 夫 74 : AQAS 15:GaAs 第  1  図
1(a) and 1(b) are diagrams for explaining the present invention in detail, FIG. 2 is a diagram showing essential parts of a vapor phase growth apparatus used in one embodiment of the present invention, The figure is a diagram for explaining the tilt angle β of a vertical superlattice. 11.GaAs substrate, lla...Trace of substrate, 12
-GaAs, 13-AQAso (b) Agent Patent Attorney Norio Ogo 74: AQAS 15:GaAs Fig. 1

Claims (1)

【特許請求の範囲】[Claims] 成長容器内に結晶の指数面が(100)、(111)、
または(110)から所定の方位に傾いた基板を配置し
、その結晶面上に二種類以上の半導体結晶層を順次単分
子層成長させて縦型半導体超格子を形成するに際し、半
導体結晶層の構成元素を含む原料ガスを交互に成長容器
に導入し前記基板の結晶面上に単原子層成長法により半
導体超格子を形成することを特徴とする縦型半導体超格
子の製造方法。
The index planes of the crystal are (100), (111),
Alternatively, when a vertical semiconductor superlattice is formed by arranging a substrate tilted in a predetermined direction from (110) and growing two or more types of semiconductor crystal layers in monolayer sequentially on the crystal plane, 1. A method for producing a vertical semiconductor superlattice, characterized by forming a semiconductor superlattice on the crystal plane of the substrate by a monoatomic layer growth method by alternately introducing raw material gases containing constituent elements into a growth container.
JP17115490A 1990-06-28 1990-06-28 Production of longitudinal semiconductor superlattice Pending JPH0459699A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17115490A JPH0459699A (en) 1990-06-28 1990-06-28 Production of longitudinal semiconductor superlattice

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP17115490A JPH0459699A (en) 1990-06-28 1990-06-28 Production of longitudinal semiconductor superlattice

Publications (1)

Publication Number Publication Date
JPH0459699A true JPH0459699A (en) 1992-02-26

Family

ID=15917993

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17115490A Pending JPH0459699A (en) 1990-06-28 1990-06-28 Production of longitudinal semiconductor superlattice

Country Status (1)

Country Link
JP (1) JPH0459699A (en)

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