JPH0458532A - Manufacture 0f semiconductor device - Google Patents

Manufacture 0f semiconductor device

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Publication number
JPH0458532A
JPH0458532A JP17057590A JP17057590A JPH0458532A JP H0458532 A JPH0458532 A JP H0458532A JP 17057590 A JP17057590 A JP 17057590A JP 17057590 A JP17057590 A JP 17057590A JP H0458532 A JPH0458532 A JP H0458532A
Authority
JP
Japan
Prior art keywords
film
sin
sio
substrate
sio2
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP17057590A
Other languages
Japanese (ja)
Inventor
Hirotoshi Kawahira
川平 博敏
Masahiro Horio
正弘 堀尾
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sharp Corp
Original Assignee
Sharp Corp
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Filing date
Publication date
Application filed by Sharp Corp filed Critical Sharp Corp
Priority to JP17057590A priority Critical patent/JPH0458532A/en
Publication of JPH0458532A publication Critical patent/JPH0458532A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To restrain the dug amount of an Si substrate and to relax a stress acting on an SiN film and a LOCOS film when the LOCOS film is formed by a method wherein an SiO2 film and the SiN film are formed on the Si substrate, a dry etching operation is executed and, after that, a wet etching operation is executed. CONSTITUTION:An SiO2 film 2 and an SiN film 3 are formed on an Si substrate 1; and after that, a pattern 5 is formed by an exposure operation and a developing operation. At this time, the SiO2 film 2 and the SiN film 3 are dry-etched continuously at the pattern 5; and an SiO2 film 2a only in a proper film thickness is left. In addition, the SiO2 film 2a is wet-etched; and an undercut part 14 is produced under a pattern 13 of the SiN film 3. An SiN film 6 and an SiO2 film 7 are developed; and a sidewall 7a is formed by an etching-back process. An impurity layer 8 is formed; the SiO2 films 7a, 4 are removed; and a LOCOS oxide part 19 is formed by executing a LOCOS oxidation operation. In addition, the SiO2 film on the surface and the whole SiN films 3, 6 are removed; and a LOCOS film 9 is formed.

Description

【発明の詳細な説明】 (イ)産業上の利用分野 本発明は、半導体装置の製造方法に関し、更に詳しくは
半導体製造工程における素子分離工程の微細化を可能に
するfこめの手法に関するものである。
DETAILED DESCRIPTION OF THE INVENTION (a) Industrial Application Field The present invention relates to a method for manufacturing a semiconductor device, and more specifically to a method for making it possible to miniaturize the element isolation process in the semiconductor manufacturing process. be.

(ロ)従来の技術 LSIの素子分離工程においては従来はLOCO8法二
局所酸化法]て形成する。これは活性領域にSiN膜を
被着し、それ以外の部分にイオン注入等を経て1μm前
後の膜厚が得られる様に酸化を行うと、SiNか被着し
ていない部分てフィールド酸化膜(〜1μm)か成形さ
れる。
(b) Conventional technology In the element isolation process of LSI, conventionally, the LSI is formed using the LOCO8 method and two local oxidation method. This is done by depositing a SiN film on the active region and oxidizing the other parts through ion implantation to obtain a film thickness of around 1 μm. ~1 μm).

すなわち、第4図は、通常のLOCO9法に関しての工
程フローを示す。
That is, FIG. 4 shows a process flow regarding the normal LOCO9 method.

第4図(a)に示すように、例えばP型S】基板4Iに
下敷のS + 02膜42を形成後S 13N +膜4
3を堆積する。次にフォトレノストでパターン44を形
成後B(ボロン)45をイオン注入する[第4図(b)
参照]。その後残存しrこ5isN4膜43およびS1
0.膜42をもとに酸化工程を行い、フィールドSiO
2膜46を形成するE第4図(c)参、照コ 。
As shown in FIG. 4(a), for example, after forming an underlying S + 02 film 42 on a P-type S] substrate 4I, an S 13N + film 4 is formed.
Deposit 3. Next, after forming a pattern 44 with photorenost, B (boron) 45 is ion-implanted [Fig. 4(b)]
reference]. After that, the remaining 5 is N4 film 43 and S1
0. An oxidation process is performed based on the film 42 to form a field SiO
4(c) to form two films 46.

この様に活性領域S間の分離を厚い酸化膜で分離する方
法においては、フィールド酸化膜形成時にSiN膜43
の端部に5iOzが侵入し、いわゆるバーズビーク47
ができて[第5図(a)参照コ、チャンネル幅か実効的
に減少する。第5図(b)に下敷SiO2膜厚によるバ
ーズビーク長Qの変化を示す。第5図(b)から、バー
ズビーク長が片側で06〜1.0μmになるにめマスク
サイズからのノットは12〜20μmに至ることがわか
る。
In this method of separating the active regions S using a thick oxide film, the SiN film 43 is formed during the formation of the field oxide film.
5iOz invades the edge of the so-called bird's beak 47
As a result, the channel width is effectively reduced (see FIG. 5(a)). FIG. 5(b) shows the change in bird's beak length Q depending on the thickness of the underlying SiO2 film. From FIG. 5(b), it can be seen that when the bird's beak length becomes 06 to 1.0 μm on one side, the knot from the mask size reaches 12 to 20 μm.

このにめS I N @の端をフィールド部の内側まで
伸ばしてバーズビーク長を短くするオフセットロコス法
(O5ELO法)か提案されている。
To this end, an offset LOCOS method (O5ELO method) has been proposed in which the end of S I N @ is extended to the inside of the field part to shorten the bird's beak length.

すなわち、第3図(a)に示すように、Si基板31上
に、下敷きのSin、膜32、SiN膜33、酸化膜(
HTO膜)34を堆積する。次に、レジストマスクを用
いてパターン35を形成する[第3図(b)参照コ。さ
らに、SiN膜36、HTo膜(酸化膜)37をデポジ
ットする[第3図(c)参照コ。続いて、ドライエツチ
ャーによりエッチバックし、窓35aをあけるとともに
、窓部35aにイオン注入を行う7第3図(d)参照コ
。この際、例えば、1B°を注入する。モして、不純物
層38を形成「第3図(e)参照コした後、ウェットエ
ツチングにより、酸化膜34.37を除去し7第3図(
f)参照2、第3図(g)に示すように、Lacos酸
化(1050℃)を行う。LOGOS膜39を形成後、
SiN膜33,36および5loz膜32を除去するL
第3図(h)参照]。
That is, as shown in FIG. 3(a), an underlying Si film 32, a SiN film 33, and an oxide film (
A HTO film) 34 is deposited. Next, a pattern 35 is formed using a resist mask (see FIG. 3(b)). Furthermore, a SiN film 36 and an HTo film (oxide film) 37 are deposited [see FIG. 3(c)]. Next, etching is performed using a dry etcher to open the window 35a, and ions are implanted into the window 35a (see FIG. 3(d)). At this time, for example, 1B° is injected. After forming the impurity layer 38 (see FIG. 3(e)), the oxide films 34 and 37 are removed by wet etching (see FIG. 3(e)).
f) Perform Lacos oxidation (1050°C) as shown in Reference 2 and Figure 3 (g). After forming the LOGOS film 39,
L to remove SiN films 33, 36 and 5LOZ film 32
See Figure 3(h)].

本方法ではマスクからのノットか抑えられるため微細化
において有利であるか反面次の様を問題点かある。
Although this method is advantageous in miniaturization because knots from the mask can be suppressed, it does have the following problems.

(ハ)発明か解決しようとする課題 】1局所酸化時のバーズビーク長を抑えるためにSiN
膜のオフセット幅を長くする必要かある。
(c) Invention or problem to be solved] 1. SiN to suppress the bird's beak length during local oxidation
Is it necessary to increase the offset width of the membrane?

このfこめに、下敷の5jOz膜とSiN膜を厚膜化す
る必要がありエツチング時に下地のSi○、のバラツキ
やエツチング均一性のバラツキにより下地のSiが掘れ
すぎて溝となって後の工程での不良につながる。
At this point, it is necessary to thicken the underlying 5JOz film and SiN film, and due to variations in the underlying Si○ and variations in etching uniformity during etching, the underlying Si is dug too much and becomes grooves, which can be removed in subsequent steps. This may lead to defects in the product.

2、またこの様な膜厚下で5iOz(局所酸化)を成長
させた場合に強いストレス(応力)を受け、フィールド
酸化部にダメージの発生する可能性がある。
2. Furthermore, when 5iOz (local oxidation) is grown under such a film thickness, strong stress may be applied, which may cause damage to the field oxidation portion.

すなわち、具体的に、第2図(a)に示す様に、Si基
板31上に堆積された、5102膜32/S iN膜3
3 / S i O2膜34が所定のレジストパターン
をマスクにエツチングされる際に、膜厚バラツキ、エツ
チングバラツキにより、Siか掘れすぎる箇所31aか
生じる。この掘れすぎる箇所31aを有するSi基板3
1上に、酸化膜37の堆積C第2図(b);、エッチバ
ック工程E第2図(c):、・を行い、第2図(d)に
示すように、酸化を経fニウェハ−40は、第2図(e
)に示すように、ストレスダメージ、Siの溝の発生す
る可能性がある。
Specifically, as shown in FIG. 2(a), the 5102 film 32/SiN film 3 deposited on the Si substrate 31
3/ When the SiO2 film 34 is etched using a predetermined resist pattern as a mask, some portions 31a are created where Si is dug too much due to variations in film thickness and variations in etching. Si substrate 3 having this excessively dug portion 31a
An oxide film 37 is deposited on the wafer (Fig. 2(b)), an etch-back process (Fig. 2(c)) is performed, and the oxide film 37 is oxidized as shown in Fig. 2(d). -40 is shown in Figure 2 (e
), stress damage and Si grooves may occur.

すなわち、ストレスによるダメージ部39a1Siの掘
れすぎによる溝39bが形成されるおそれがあり、後の
工程で、レジスト残り等が発生する。
That is, there is a possibility that a groove 39b is formed due to excessive digging of the damaged portion 39a1Si due to stress, and residual resist etc. will occur in a later process.

本発明はLS If)製造工程時における上記問題点の
解決を図るためのしので、下地S1の掘れ量を低減し、
かつストレスを緩和するのに有効な方法を提供するもの
である。
The present invention aims to solve the above-mentioned problems during the LS If) manufacturing process, by reducing the amount of digging in the base layer S1,
It also provides an effective method for alleviating stress.

(ニ)課題を解決するための手段及び作用この発明は、
S1基板上に、オフセットロコス法を用いて素子分離部
を形成するに際して、(i)Si基板上に、全面に、下
敷の5iOy膜、第1のSiN膜、第1のSiO2膜を
順次積層し、(11)フォトレノストパターンを用いて
素子分離部形成領成上に、上記第1の5i02膜及び第
1のSiN膜を除去し、さらに上記下敷のSiO2膜を
途中まで除去してS1基板上に下敷の5iOyを残存さ
せながら窓を形成し、(iii)続いて、ウェットエツ
チングを用いて残在された下敷のSin、膜を除去して
窓側壁のSiN膜直下における素子分離部形成領域にア
ンダーカット部を形成し、(IV)窓を含むSi基板上
に、全面に、第2のSiN膜、サイドウオール形成用の
第2の5102膜を順次積層した後、エッチバックをお
こなって窓側壁面部にサイドウオールを形成し、(■)
イオン注入をおこなってSi基板上の素子分離部形成領
域に不純物層を形成し、(Vl)サイドウオールおよび
残存する第1のSiOx膜を除去した後、Si基板上に
、全面に、熱酸化をおこなってS iOtのロコス酸化
膜を形成し、続いて表面の5i02膜およびすへてのS
iN膜を除去して素子分離部を形成することを特徴とす
る半導体装置の製造方法である。
(d) Means and operation for solving the problem This invention includes:
When forming an element isolation part on the S1 substrate using the offset locos method, (i) an underlying 5iOy film, a first SiN film, and a first SiO2 film are sequentially laminated on the entire surface of the Si substrate; , (11) Remove the first 5i02 film and the first SiN film on the element isolation formation region using a photorenost pattern, and further remove part of the underlying SiO2 film to form the S1 substrate. A window is formed while leaving the underlying 5iOy on top, and (iii) the remaining underlying Si film is removed by wet etching to form an element isolation region forming area directly under the SiN film on the window side wall. (IV) After sequentially laminating a second SiN film and a second 5102 film for sidewall formation on the entire surface of the Si substrate including the window, etching back was performed to remove the window side. Form a side wall on the wall part, (■)
After performing ion implantation to form an impurity layer in the element isolation region on the Si substrate and removing the (Vl) sidewall and the remaining first SiOx film, thermal oxidation is applied to the entire surface of the Si substrate. A LOCOS oxide film of SiOt is formed, followed by a 5i02 film on the surface and a LOCOS oxide film of SiOt.
This method of manufacturing a semiconductor device is characterized in that an iN film is removed to form an element isolation section.

すなわち、この発明は、下敷のSiO2膜、SiN膜を
形成後フォトレジストパターンを用いてエツチングしf
こ後、少なくとも100A、以上のSiO2膜をエツチ
ングするウェット処理工程を行うことにより、下地S1
の掘fllを抑え、かつロコス酸化膜形成時にSiN及
びロコス酸化膜に作用する応力を緩和できる方法を提供
する事により構成されるものである。
That is, in this invention, after forming the underlying SiO2 film and SiN film, etching is performed using a photoresist pattern.
Thereafter, by performing a wet treatment process to etch the SiO2 film with a thickness of at least 100A, the base layer S1
The present invention is constructed by providing a method capable of suppressing the trench full and alleviating the stress acting on SiN and the LOCOS oxide film during formation of the LOCOS oxide film.

(ホ)実施例 以下図面に示す実施例に基づいてこの発明を詳述する。(e) Examples The present invention will be described in detail below based on embodiments shown in the drawings.

なおこれによってこの発明は限定されるものではない。Note that this invention is not limited by this.

第1図は本発明による素子分離形成工程の一実施例を示
し、几ものである。
FIG. 1 shows one embodiment of the element isolation forming process according to the present invention, and is a thorough example.

まず、第1図(a)に示すように、Si基板1上に下敷
の5iO=膜2、SiN膜3を形成後、フォトレノスト
4を塗布し、所望のパターン5を、マスク4を用いて露
光、現像する二とによって形成する二第1図(b)参照
j0 この際、ドライエツチング装置を用いてパターン5を下
敷のSiO2、SiNとエツチングを続は適当な膜厚だ
け5IO2膜2aを残す。
First, as shown in FIG. 1(a), after forming an underlying 5iO film 2 and a SiN film 3 on a Si substrate 1, a photorenost 4 is applied, and a desired pattern 5 is exposed using a mask 4. At this time, using a dry etching device, the pattern 5 is etched with the underlying SiO2 and SiN, leaving an appropriate thickness of the 5IO2 film 2a.

さらにウェットエツチングを用いて残存のSiO2膜2
aをエツチングするとともに、SiN膜3のノくターン
13の下に100 A種変のアンダーカット部14を生
じさせる[第1図(c)参照]。
Furthermore, the remaining SiO2 film 2 is etched using wet etching.
At the same time, a 100A type undercut portion 14 is formed under the notch 13 of the SiN film 3 [see FIG. 1(c)].

この後、オフセットSiN形成用のSiN膜6を堆積し
、さらにSiO!膜(HTO膜)7を堆積し[第1図(
d)参照]、エッチバック工程によりウェハーを全面エ
ツチングし、サイドウオール7aを作成する[第1図(
e)参照コ。
After that, a SiN film 6 for forming offset SiN is deposited, and then SiO! A film (HTO film) 7 is deposited [Fig.
d)], the entire surface of the wafer is etched by an etch-back process to create a sidewall 7a [see Fig. 1 (
e) Reference.

この際、アンダーカット部14によりSiN膜6と5i
Op膜2間には空隙15か生じる。また、イオン注入の
窓16が形成される。
At this time, the undercut portion 14 allows the SiN film 6 and 5i to
A void 15 is created between the Op films 2. Also, an ion implantation window 16 is formed.

しかる後、窓16に”B ”のイオン45を注入し、不
純物層8を形成し[第1図(f)参照]、5i0z膜7
i、4を除去し[第1図(g)参照コ、1050℃でロ
コス酸化をおこない、5iOyのロコス酸化部19を形
成し「第1図(h)参照〕、次いで表面のSiO2膜お
よびすべてのSiN膜3.6を除去してLOGO5膜9
を形成する7第1図(i)参照2゜ 本方法では、アンダーカプト部を設けた状態でLOGO
S膜を形成するようにしたので、従来のオフセットロコ
ス膜て形成しTニパターンに比へて81の掘れすぎによ
る形状不良かなく、またロコス酸化膜の上下に発生する
応力をオフセットSiN膜で緩和しているため不良なロ
コス酸化膜が得られる。
Thereafter, "B" ions 45 are implanted into the window 16 to form an impurity layer 8 [see FIG. 1(f)], and the 5i0z film 7 is formed.
i, 4 [see Fig. 1(g)], LOCOS oxidation is performed at 1050°C to form 5iOy LOCOS oxidized part 19 [see Fig. 1(h)], and then the SiO2 film on the surface and all LOGO5 film 9 by removing the SiN film 3.6.
7 See Figure 1 (i) 2 In this method, the LOGO is formed with the undercap part provided.
Since the S film is formed, compared to the conventional offset LOCOS film and T double pattern, there is no shape defect due to excessive digging of 81, and the stress generated above and below the LOCOS oxide film can be reduced by using the offset SiN film. Because of the relaxation, a defective LOCOS oxide film is obtained.

(へ)発明の効果 以上のようにこの発明によれば、LSIの素子分離工程
に、いわゆるオフセットロコス法を用いる際に、シリコ
ン基板上にSiO2膜を形成し、次にS i N膜を形
成し、次にSiO2膜を堆積したのちフォトレノストパ
ターンを用いてエツチングした後に、少なくとも100
Å以上のSiO2膜をエツチングするウェット処理工程
を行うことにより、エツチング時のバラツキや堆積膜の
バラツキによるウェハー内の部分的な下地Siの掘れ量
を最小限に抑制でき、プロセス上のマージンを向上する
事か可能である。
(F) Effects of the Invention As described above, according to the present invention, when using the so-called offset LOCOS method in the LSI element isolation process, an SiO2 film is formed on a silicon substrate, and then a SiN film is formed. Then, after depositing a SiO2 film and etching it using a photorenost pattern, a film of at least 100%
By performing a wet processing process to etch the SiO2 film with a thickness of Å or more, it is possible to minimize the amount of partial excavation of the underlying Si in the wafer due to variations in etching and variations in the deposited film, improving process margins. It is possible to do so.

また、ロコス酸化膜形成時に、S iN及びロコス酸化
膜に作用する応力による結晶の欠陥等を緩和でき、結晶
欠陥等によって生じる電気的な不良(リーク他)を防止
できる効果がある。
Further, when forming the LOCOS oxide film, crystal defects caused by stress acting on the SiN and the LOCOS oxide film can be alleviated, and electrical defects (leakage, etc.) caused by crystal defects can be prevented.

【図面の簡単な説明】[Brief explanation of drawings]

第1図はこの発明の一実施例を示すオフセットロコス工
程の製造工程説明図、第2図は従来例のオフセットロコ
ス工程時に発生する不良を説明する1こめの製造工程説
明図、第3図は従来例のオフセットロコス工程の製造工
程説明図、第4図は通常のLOCO3法を説明するため
の製造工程説明図、第5図(a)および(b)はそれぞ
れ第4図の通常のLOGOS工程における欠点を説明す
るための要部構成説明図および下敷Sin、膜厚対バー
ズビーク長特性図である。 4・・・・・第1のSiO2膜、 5 ・・・・第1のパターン(窓)、 6・・・・・第2のSiN膜、 7・・・・・第2のSiC,膜、 7a ・・・サイドウオール、 8・・・・・・不純物拡散層、 9・・・・・LOCO5酸化膜(Sift膜)、13・
・・ 第2のパターン、 14・・・・・アンダーカット部。 l ・・・51基板、 2・・・下敷の5iO=膜、 3・・・第1のSiN膜、 第2図 13図 第4図 第5図 1右5i02!gA7% (nm)
Fig. 1 is an explanatory diagram of the manufacturing process of an offset locos process showing an embodiment of the present invention, Fig. 2 is an explanatory diagram of the first manufacturing process to explain defects that occur during the conventional offset locos process, and Fig. 3 is an explanatory diagram of the manufacturing process of the offset locos process. 4 is an explanatory diagram of the manufacturing process of the conventional offset LOCO process, FIG. 4 is an explanatory diagram of the manufacturing process for explaining the normal LOCO3 method, and FIGS. 5(a) and (b) are the usual LOGOS process of FIG. 4, respectively. FIG. 2 is an explanatory diagram of a main part configuration and a characteristic diagram of underlay Sin and film thickness versus bird's beak length for explaining the drawbacks in FIG. 4...First SiO2 film, 5...First pattern (window), 6...Second SiN film, 7...Second SiC film, 7a... Side wall, 8... Impurity diffusion layer, 9... LOCO5 oxide film (Sift film), 13...
...Second pattern, 14...Undercut part. l...51 substrate, 2...underlying 5iO = film, 3...first SiN film, Figure 2, Figure 13, Figure 4, Figure 5, Figure 1 right 5i02! gA7% (nm)

Claims (1)

【特許請求の範囲】 1、Si基板上に、オフセットロコス法を用いて素子分
離部を形成するに際して、 (i)Si基板上に、全面に、下敷のSiO_2膜、第
1のSiN膜、第1のSiO_2膜を順次積層し、(i
i)フォトレジストパターンを用いて素子分離部形成領
域上に、上記第1のSiO_2膜及び第1のSiN膜を
除去し、さらに上記下敷のSiO_2膜を途中まで除去
してSi基板上に下敷のSiO_2を残存させながら窓
を形成し、 (iii)続いて、ウェットエッチングを用いて残在さ
れた下敷のSiO_2膜を除去して窓側壁のSiN膜直
下における素子分離部形成領域にアンダーカット部を形
成し、 (iv)窓を含むSi基板上に、全面に、第2のSiN
膜、サイドウォール形成用の第2のSiO_2膜を順次
積層した後、エッチバックをおこなって窓側壁面部にサ
イドウォールを形成し、 (v)イオン注入をおこなってSi基板上の素子分離部
形成領域に不純物層を形成し、 (vi)サイドウォールおよび残存する第1のSiO_
2膜を除去した後、Si基板上に、全面に、熱酸化をお
こなってSiO_2のロコス酸化膜を形成し、続いて表
面のSiO_2膜およびすべてのSiN膜を除去して素
子分離部を形成することを特徴とする半導体装置の製造
方法。
[Claims] 1. When forming an element isolation part on a Si substrate using the offset Locos method, (i) the underlying SiO_2 film, the first SiN film, the first SiN film, and the 1 SiO_2 films are sequentially stacked, (i
i) Using a photoresist pattern, remove the first SiO_2 film and first SiN film on the element isolation formation region, and further remove part of the underlying SiO_2 film to form an underlying film on the Si substrate. A window is formed while leaving SiO_2, and (iii) the remaining underlying SiO_2 film is removed by wet etching to form an undercut in the element isolation region forming area directly under the SiN film on the window side wall. (iv) a second SiN layer is formed on the entire surface of the Si substrate including the window;
After sequentially stacking a second SiO_2 film for forming a sidewall and a second SiO_2 film for forming a sidewall, etchback is performed to form a sidewall on the window side wall surface, and (v) ion implantation is performed to form an element isolation region on the Si substrate. (vi) forming an impurity layer on the sidewall and remaining first SiO_
After removing the 2 films, thermal oxidation is performed on the entire surface of the Si substrate to form a LOCOS oxide film of SiO_2, and then the SiO_2 film on the surface and all SiN films are removed to form an element isolation part. A method for manufacturing a semiconductor device, characterized in that:
JP17057590A 1990-06-27 1990-06-27 Manufacture 0f semiconductor device Pending JPH0458532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP17057590A JPH0458532A (en) 1990-06-27 1990-06-27 Manufacture 0f semiconductor device

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Application Number Priority Date Filing Date Title
JP17057590A JPH0458532A (en) 1990-06-27 1990-06-27 Manufacture 0f semiconductor device

Publications (1)

Publication Number Publication Date
JPH0458532A true JPH0458532A (en) 1992-02-25

Family

ID=15907382

Family Applications (1)

Application Number Title Priority Date Filing Date
JP17057590A Pending JPH0458532A (en) 1990-06-27 1990-06-27 Manufacture 0f semiconductor device

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Country Link
JP (1) JPH0458532A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR970053451A (en) * 1995-12-27 1997-07-31 김주용 Device Separation Method of Semiconductor Device
US5714781A (en) * 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove
US5776812A (en) * 1994-03-30 1998-07-07 Nippondenso Co., Ltd. Manufacturing method of semiconductor device
US5780324A (en) * 1994-03-30 1998-07-14 Denso Corporation Method of manufacturing a vertical semiconductor device
US5972778A (en) * 1994-06-24 1999-10-26 Nec Corporation Method of fabricating semiconductor device
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6015737A (en) * 1991-07-26 2000-01-18 Denso Corporation Production method of a vertical type MOSFET
US6603173B1 (en) 1991-07-26 2003-08-05 Denso Corporation Vertical type MOSFET
US5776812A (en) * 1994-03-30 1998-07-07 Nippondenso Co., Ltd. Manufacturing method of semiconductor device
US5780324A (en) * 1994-03-30 1998-07-14 Denso Corporation Method of manufacturing a vertical semiconductor device
US5972778A (en) * 1994-06-24 1999-10-26 Nec Corporation Method of fabricating semiconductor device
US5714781A (en) * 1995-04-27 1998-02-03 Nippondenso Co., Ltd. Semiconductor device having a gate electrode in a grove and a diffused region under the grove
KR970053451A (en) * 1995-12-27 1997-07-31 김주용 Device Separation Method of Semiconductor Device

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