JPH0457912U - - Google Patents

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Publication number
JPH0457912U
JPH0457912U JP10085890U JP10085890U JPH0457912U JP H0457912 U JPH0457912 U JP H0457912U JP 10085890 U JP10085890 U JP 10085890U JP 10085890 U JP10085890 U JP 10085890U JP H0457912 U JPH0457912 U JP H0457912U
Authority
JP
Japan
Prior art keywords
transistor
collector
emitter
current
circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP10085890U
Other languages
English (en)
Other versions
JP2538239Y2 (ja
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP1990100858U priority Critical patent/JP2538239Y2/ja
Publication of JPH0457912U publication Critical patent/JPH0457912U/ja
Priority to US08/531,063 priority patent/US5717684A/en
Application granted granted Critical
Publication of JP2538239Y2 publication Critical patent/JP2538239Y2/ja
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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Description

【図面の簡単な説明】
第１図は、本考案に係る低周波増幅回路の一実
施例を説明する為の回路図、第２図は、従来の低
周波増幅回路の一例を示す回路図である。 １……入力端子、２……出力端子、３，５……
定電流源回路、４，７……電流ミラー回路、６…
…電源電圧端子、Ａ……出力段、Ｂ……バイアス
回路。

Claims (1)

    【実用新案登録請求の範囲】
  1. 第１のトランジスタのコレクタに抵抗が接続さ
    れ、第１のトランジスタのエミツタに第２のトラ
    ンジスタのコレクタが接続され、第２のトランジ
    スタのエミツタが接地され、該第１のトランジス
    タのエミツタと該第２のトランジスタのコレクタ
    から出力を得る出力段と、該出力段の第１と第２
    のトランジスタのベースにバイアス電流に重畳さ
    れた信号電流を供給するバイアス回路と、該第１
    のトランジスタのコレクタと該抵抗との接続点に
    第３のトランジスタのエミツタが接続され、ミラ
    ー電流を供給する第４のトランジスタのコレクタ
    が該第１のトランジスタのベースに接続されてな
    る電流ミラー回路とを含むことを特徴とする低周
    波増幅回路。
JP1990100858U 1990-01-29 1990-09-26 低周波増幅回路 Expired - Lifetime JP2538239Y2 (ja)

Priority Applications (2)

Application Number Priority Date Filing Date Title
JP1990100858U JP2538239Y2 (ja) 1990-09-26 1990-09-26 低周波増幅回路
US08/531,063 US5717684A (en) 1990-01-29 1995-09-20 Disk cartridge having chamfered wall portion

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1990100858U JP2538239Y2 (ja) 1990-09-26 1990-09-26 低周波増幅回路

Publications (2)

Publication Number Publication Date
JPH0457912U true JPH0457912U (ja) 1992-05-19
JP2538239Y2 JP2538239Y2 (ja) 1997-06-11

Family

ID=31843829

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1990100858U Expired - Lifetime JP2538239Y2 (ja) 1990-01-29 1990-09-26 低周波増幅回路

Country Status (1)

Country Link
JP (1) JP2538239Y2 (ja)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559105U (ja) * 1978-06-30 1980-01-21

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS559105U (ja) * 1978-06-30 1980-01-21

Also Published As

Publication number Publication date
JP2538239Y2 (ja) 1997-06-11

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