JPH0457358A - Integrated circuit device with plurality of power supplies - Google Patents

Abstract

PURPOSE:To reduce the consumed power of an integrated circuit by providing the first input-output buffer circuits which is actuated by the first power supply voltage, an internal circuit which is actuated by the second power supply voltage having a voltage value lower than that of the first power supply voltage, and the second input-output buffer circuit which is connected with the internal circuit and actuated by the second power supply voltage. CONSTITUTION:The first input-output buffer circuits 42 and 43 actuated by the first power supply voltage V1, an internal circuit 48 which is connected with the circuits 42 and 43 and actuated by the second power supply voltage V2 having a voltage value lower than that of the first voltage V1, and the second input-output buffer circuit 47 which is connected with the circuit 48 and actuated by the second power supply voltage V2 are provided. Since the circuits 42 and 43 are actuated by the first voltage V1 and the circuits 48 and 47 are actuated by the second voltage V2 which is lower than the first voltage V1 in such way, the connection with peripheral devices can be made easier and the consumed power can be reduced.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to integrated circuit devices that use multiple power supply voltages.

[Prior Art] In order to reduce the power consumption of an integrated circuit device or to facilitate pattern design and layout design of a photomask, the power supply voltage of the internal circuits of an integrated circuit is reduced. Furthermore, in order to facilitate connection with peripheral devices used outside the integrated circuit device, the input/output buffer section 7 is driven at a power supply voltage higher than the power supply voltage inside the integrated circuit device. is being developed.

FIG. 5 is a block diagram of a conventional integrated circuit device of this type.

As shown in the figure, the integrated circuit device 10 includes an internal circuit 11
and level conversion circuits 12 and 13 and input/output buffer circuit 1
4 and 15, pads 16 to 24, etc.

The pad 16 to which the power supply voltage v1 is supplied is connected to the input/output buffer 7 circuits 14 and 15 and the level conversion circuits 12 and 13.
and is connected to. Power supply voltage v lower than power supply voltage v1
The pad 17 to which 2 is supplied is connected to the level conversion circuit 12.
and 13 and the internal circuit 11. Ground potential v3. The pad 21 to which is supplied is connected to each of these circuits 11
~15 are connected.

The input/output buffer 14 operates at a power supply voltage 1 which is the same voltage as the power supply voltage of an external circuit (not shown) connected to the integrated circuit device 10, and the internal circuit 11 operates at a power supply voltage V2, which is lower than the power supply voltage V2. Operate.

The level conversion circuit 12 is supplied with power supply voltages v1 and v2 for interfacing the input/output buffer 14 and the internal circuit 11.

Although the input protection circuit in the input section requires the power supply voltage V1, the input signal itself may be directly input to the internal circuit 11.

FIG. 6 shows a block diagram of another conventional integrated circuit device.

The difference from the integrated circuit device 11 shown in FIG. 5 is that the power supply voltage is a single power supply voltage V. ol, and the power supply voltage ■. D.I.
The pad 31 supplied with
and level conversion circuits 27 and 28. Voltage V dropped by voltage drop circuit 29. D
2 (voltage at point A in the figure) is the level conversion circuit 27
and 28 and the internal circuit 30, respectively.

Therefore, the input/output buffers 25 and 26 are connected to the power supply voltage Vo. 1
The internal circuit 30 operates at a voltage V lowered by the voltage drop circuit 29. It operates at 2.

However, as in the case of Fig. 5, the input protection circuit at the input section has a power supply voltage ■. ol is required, but the input signal itself may be directly input to the internal circuit 30.

[Problems to be Solved by the Invention] As described above, in the conventional integrated circuit device, all input/output buffers are supplied with a power supply voltage higher than the power supply voltage of the internal circuit. However, some of the circuits in the input/output buffer operate even with the low power supply voltage supplied to the internal circuits, and these circuits are also supplied with a high power supply voltage, resulting in high power consumption. Put it away.

SUMMARY OF THE INVENTION Accordingly, an object of the present invention is to provide a multi-power supply integrated circuit device that can reduce power consumption.

[Means for Solving the Problems] According to the present invention, the above object is achieved by a first input/output buffer circuit that operates with a first power supply voltage, and a first input/output buffer circuit that is connected to the first input/output buffer circuit. This is achieved by including an internal circuit that operates at a second power supply voltage lower than the power supply voltage of , and a second input/output buffer 7 circuit that is connected to the internal circuit and operates at the second power supply voltage. .

[Function] The first input/output buffer 7 circuit operates with the first power supply voltage. This makes it easier to connect to external peripheral devices. The internal circuit and the second input/output buffer circuit operate at a second power supply voltage lower than the first power supply voltage. Since the second input/output buffer is not operated at the first power supply voltage but at a second power supply voltage lower than this, power consumption is reduced.

[Example] Hereinafter, the present invention will be explained in detail with reference to the drawings.

FIG. 1 shows a block diagram of a multiple power supply integrated circuit device as an embodiment of the present invention.

As shown in the figure, a pad 4 to which power supply voltage v1 is supplied
1 includes input/output buffers 42 and 43 and a level conversion circuit 4
4 and 45. This power supply voltage v1 corresponds to the first power supply voltage of the present invention, and the input/output buffers 42 and 43 correspond to the first input/output buffer circuit of the present invention.

The pad 46 to which the power supply voltage ■ and the lower power supply voltage V2 are supplied is connected to the input/output buffer 47 and the level conversion circuit 4.
4 and 45 and an internal circuit 48. This power supply voltage ■2 corresponds to the second power supply voltage of the present invention,
The input/output buffer 47 corresponds to the second input/output buffer circuit of the present invention.

The pad 49 to which the ground potential V55 is supplied is connected to input/output buffers 42, 43 and 47 (not shown in FIG. 1 to avoid complexity), level conversion circuits 44 and 45, and internal circuit 4.
8.

Pads 50 and 51.52 for connecting to external circuits
~53 and 54~56 are input/output buffers 47.43
and 42, respectively.

Input/output buffers 42, 43 and 47 provide an interface between external peripheral devices and internal circuitry 48.

The input/output buffers 42 and 43 operate on the power supply voltage V. Note that this power supply voltage (1) is equal to the power supply voltage of a peripheral device (not shown) used externally.

The input/output buffer 47 and the internal circuit 48 operate on the power supply voltage (2).

The level conversion circuits 44 and 45 have power supply voltages ■1 and ■
2 is supplied, and these power supply voltages (1) and (2) are used to perform level conversion between the signal level of the internal circuit 48 and the signal level of the external peripheral device.

FIG. 2 is a circuit diagram showing an example of the input/output buffer 47 shown in FIG. 1.

As shown in the figure, a pad 50 is connected to the gate electrode of a PMO3 (P-channel metal oxide semiconductor) transistor 57 and the gate electrode of an NMOS (N-channel O3) h range metal 58, and is connected to the drain of the PMOS transistor 57. NMOS transistor 58
is connected to the pad 51. PMOS
The source of the transistor 57 is supplied with the power supply voltage v2, and the source of the NMOS transistor 58 is grounded. These PMOS transistors 57 and NMOS
An inverter 59 is formed by the transistor 58.

PMOS transistor 60 and NMOS transistor 6
1 forms another inverter 62, and the output of the inverter 59 is connected to the input of the inverter 62. Both ends of the crystal oscillator 63, both ends of the feedback resistor 64, and pads 50 and 51 are connected to the outside of this integrated circuit device. One ends of the stabilizing capacitors 65 and 66 are connected to the crystal oscillator 63, and the other ends of the stabilizing capacitors 65 and 66 are grounded. These inverter 59, crystal oscillator 63, feedback resistor 64, and stabilizing capacitors 65 and 66 constitute an oscillation circuit.

Each component of this oscillation circuit differs depending on the type of oscillator. The waveform of the oscillation signal from the oscillation circuit is waveform-shaped by an inverter 62 and then supplied to the internal circuit.

FIG. 3 shows the level conversion circuits 44 and 45 shown in FIG.
It is a circuit diagram showing an example.

The level conversion circuit shown in the figure is the same circuit as the embodiment of the logic level conversion circuit described in the specification of the patent application filed on May 31, 1990 by the applicant of the present application.

This logic level conversion circuit is composed of two inverters 67 and 68, a PMOS transistor 69, and a control circuit consisting of an NMO3h transistor 0.

The power supply terminal of the inverter 68 is supplied with a power supply voltage (2), and the power supply terminal of the inverter 67 is supplied with a power supply voltage V2 lower than the power supply voltage V1.

When a signal voltage at the "0" logic level is applied to the input terminal 71 of the inverter 67, the output terminal voltage of the inverter 67 becomes the "1" logic level. When the output terminal voltage of this impeller 67 is applied to the gate electrode of the NMOS transistor 72 of the inverter 68, this NMOS transistor 7
2 becomes conductive, so the output terminal 74 becomes the logic level "0". This "0" logic level voltage is also applied to the gate electrode of the PMO transistor 9 of the control circuit. As a result, the control circuit completely shuts off the PMOS transistor 73 of the inverter 68.

On the contrary, when a signal voltage at the logic level "1" is applied to the inverter 67, the voltage at the output terminal of the inverter 67 becomes the logic level "0". The voltage at this output terminal is N
Since the voltage is applied to the gate electrode of the MOS transistor 72, this NMO3h run system tough 2 is in a cut-off state.

On the other hand, the signal voltage at the "1" logic level is also applied to the control circuit. As a result, the NMOS transistor 7 of the control circuit
0 becomes conductive, and as a result, the PM of the inverter 68
The OS transistor 73 becomes conductive, and the output terminal 74
The terminal voltage of is at the "]-" logic level. Therefore, this level conversion circuit prevents the through current from flowing into the PMOS transistor 73 and the NMOS transistor 2, which is effective in reducing power consumption. Note that the configuration of the level conversion circuit is not limited to this, and other circuit configurations may be used.

FIG. 4 shows a block diagram of another embodiment of the invention.

As shown in the figure, the difference from the embodiment shown in FIG. 1 is that the power supply voltage is a single power supply voltage VDDI, and the pad 75 supplied with the power supply voltage VDDI is
6 and 77, level conversion circuits 78 and 7.], and voltage drop circuit 80.

This power supply voltage■. D corresponds to the first power supply voltage of the present invention, and the input/output buffers 76 and 77 correspond to the first power supply voltage of the present invention.
Compatible with input/output buffer circuits.

Output voltage VDD dropped by this voltage drop circuit 80
2 (the voltage at point B in the figure) is supplied to the internal circuit 81, the input/output buffer 82, and the level conversion circuits 78 and 79. The output voltage VDD2 of the voltage drop circuit 80 corresponds to the second power supply voltage of the present invention, and the input/output buffer 82 corresponds to the second input/output buffer circuit of the present invention.

The voltage drop circuit 80 drops the power supply voltage V o o 1 to a voltage necessary for the internal circuit 81 to operate. For example, a regulator circuit is used as the voltage drop circuit 80, but the present invention is not limited to this, and other circuits may be used or a diffused resistor may be formed on the integrated circuit.

The crowd buffers 76 and 77 have a power supply voltage ■. The input/output buffer 82 and internal circuit 81 operate at the power supply voltage V
, operates at a supply voltage V oo2 lower than 1.

The level conversion circuits 78 and 79 have a power supply voltage of V oo+
and power supply voltage ■. o2 is supplied, and these voltages VDo+ and V. o2 is used to perform level conversion between the signal level of the internal circuit 81 and the signal level of an external peripheral device.

As described above, the multiple power supply integrated circuit device of the present invention facilitates connection with external peripheral devices.

The internal circuit and the second input/output buffer circuit operate at a second power supply voltage lower than the first power supply voltage, so power consumption is reduced.

[Effects of the Invention] As described in detail above, according to the present invention, the first input/output buffer 7 circuit operated by the first power supply voltage and the first input/output buffer circuit connected to the first input/output buffer circuit Since it is equipped with an internal circuit that operates at a second power supply voltage that is lower than the power supply voltage of Power can be reduced.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a multiple power supply integrated circuit device as an embodiment of the present invention, FIG. 2 is a circuit diagram showing an example of the input/output buffer shown in FIG. 1, and FIG. 3 is a circuit diagram showing an example of the input/output buffer shown in FIG. FIG. 4 is a block diagram of another embodiment of the present invention, FIG. 5 is a block diagram of a conventional integrated circuit device of this type, and FIG. 6 is another conventional example. 1 shows a block diagram of an integrated circuit device. 42.43.47... Input/output buffer, 44.
45...Level conversion circuit, 48...Internal circuit.

Claims (1)

[Claims] a first input/output buffer circuit that operates with a first power supply voltage; an internal circuit that is connected to the first input/output buffer circuit and operates with a second power supply voltage that is lower than the first power supply voltage; and a second input/output buffer circuit connected to the internal circuit and operated at the second power supply voltage.