JPH0457108B2 - - Google Patents

Info

Publication number
JPH0457108B2
JPH0457108B2 JP59247608A JP24760884A JPH0457108B2 JP H0457108 B2 JPH0457108 B2 JP H0457108B2 JP 59247608 A JP59247608 A JP 59247608A JP 24760884 A JP24760884 A JP 24760884A JP H0457108 B2 JPH0457108 B2 JP H0457108B2
Authority
JP
Japan
Prior art keywords
chip
film
layer
chips
contact film
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP59247608A
Other languages
English (en)
Japanese (ja)
Other versions
JPS61129835A (ja
Inventor
Satoru Tanizawa
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP59247608A priority Critical patent/JPS61129835A/ja
Publication of JPS61129835A publication Critical patent/JPS61129835A/ja
Publication of JPH0457108B2 publication Critical patent/JPH0457108B2/ja
Granted legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/82Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected by forming build-up interconnects at chip-level, e.g. for high density interconnects [HDI]
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/18High density interconnect [HDI] connectors; Manufacturing methods related thereto
    • H01L2224/23Structure, shape, material or disposition of the high density interconnect connectors after the connecting process
    • H01L2224/24Structure, shape, material or disposition of the high density interconnect connectors after the connecting process of an individual high density interconnect connector
    • H01L2224/2405Shape
    • H01L2224/24051Conformal with the semiconductor or solid-state device
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/50Tape automated bonding [TAB] connectors, i.e. film carriers; Manufacturing methods related thereto
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/80Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L2224/81Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H01L2224/818Bonding techniques
    • H01L2224/81801Soldering or alloying

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Wire Bonding (AREA)
JP59247608A 1984-11-22 1984-11-22 半導体装置 Granted JPS61129835A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP59247608A JPS61129835A (ja) 1984-11-22 1984-11-22 半導体装置

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP59247608A JPS61129835A (ja) 1984-11-22 1984-11-22 半導体装置

Publications (2)

Publication Number Publication Date
JPS61129835A JPS61129835A (ja) 1986-06-17
JPH0457108B2 true JPH0457108B2 (pl) 1992-09-10

Family

ID=17166034

Family Applications (1)

Application Number Title Priority Date Filing Date
JP59247608A Granted JPS61129835A (ja) 1984-11-22 1984-11-22 半導体装置

Country Status (1)

Country Link
JP (1) JPS61129835A (pl)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2817553B2 (ja) * 1992-10-30 1998-10-30 日本電気株式会社 半導体パッケージ構造及びその製造方法
DE102010039824B4 (de) * 2010-08-26 2018-03-29 Semikron Elektronik Gmbh & Co. Kg Leistungsbaugruppe mit einer flexiblen Verbindungseinrichtung

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146874A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochino seizohoho
JPS5734777U (pl) * 1980-07-31 1982-02-24
JPS5734777A (en) * 1980-08-08 1982-02-25 Mitsubishi Electric Corp Inverter device
JPS59205747A (ja) * 1983-05-09 1984-11-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5146874A (en) * 1974-10-18 1976-04-21 Mitsubishi Electric Corp Handotaisochino seizohoho
JPS5734777U (pl) * 1980-07-31 1982-02-24
JPS5734777A (en) * 1980-08-08 1982-02-25 Mitsubishi Electric Corp Inverter device
JPS59205747A (ja) * 1983-05-09 1984-11-21 Matsushita Electric Ind Co Ltd 半導体装置の製造方法

Also Published As

Publication number Publication date
JPS61129835A (ja) 1986-06-17

Similar Documents

Publication Publication Date Title
US7056807B2 (en) Barrier structure against corrosion and contamination in three-dimensional (3-D) wafer-to-wafer vertical stack
US7556983B2 (en) Thin planar semiconductor device having electrodes on both surfaces and method of fabricating same
US5786628A (en) Method and workpiece for connecting a thin layer to a monolithic electronic modules surface and associated module packaging
JP3356821B2 (ja) 積層マルチチップモジュール及び製造方法
US7247518B2 (en) Semiconductor device and method for manufacturing same
KR20140061225A (ko) 브리징 블록들에 의한 다중-칩 모듈 연결
US20020074637A1 (en) Stacked flip chip assemblies
US20060033194A1 (en) Methods for stacking wire-bonded integrated circuit dice on flip-chip bonded integrated circuit dice
JPH08213543A (ja) マルチダイパッケージ装置
JP2004172323A (ja) 半導体パッケージ及び積層型半導体パッケージ
US7700409B2 (en) Method and system for stacking integrated circuits
JPS5892230A (ja) 半導体装置
US7928549B2 (en) Integrated circuit devices with multi-dimensional pad structures
EP1756867A1 (en) Method and system for stacking integrated circuits
JP4538830B2 (ja) 半導体装置
TWI826339B (zh) 2.5d封裝結構及製備方法
US20230230902A1 (en) Semiconductor package structure and manufacturing method thereof
JPH0457108B2 (pl)
TWI409933B (zh) 晶片堆疊封裝結構及其製法
US9721928B1 (en) Integrated circuit package having two substrates
JPH11289047A (ja) マルチチップモジュールおよびその製造方法
TW202416482A (zh) 半導體封裝體、半導體接合結構及其形成方法
KR20230045661A (ko) 반도체 패키지의 제조 방법
TW457673B (en) Multi-chip module
TW202414716A (zh) 半導體互連橋封裝

Legal Events

Date Code Title Description
LAPS Cancellation because of no payment of annual fees