JPH0455536B2 - - Google Patents

Info

Publication number
JPH0455536B2
JPH0455536B2 JP61185913A JP18591386A JPH0455536B2 JP H0455536 B2 JPH0455536 B2 JP H0455536B2 JP 61185913 A JP61185913 A JP 61185913A JP 18591386 A JP18591386 A JP 18591386A JP H0455536 B2 JPH0455536 B2 JP H0455536B2
Authority
JP
Japan
Prior art keywords
sheet
powder
green sheet
ceramic substrate
metallized
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61185913A
Other languages
English (en)
Japanese (ja)
Other versions
JPS6342148A (ja
Inventor
Takashi Shoji
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Resonac Holdings Corp
Original Assignee
Showa Denko KK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Showa Denko KK filed Critical Showa Denko KK
Priority to JP18591386A priority Critical patent/JPS6342148A/ja
Publication of JPS6342148A publication Critical patent/JPS6342148A/ja
Publication of JPH0455536B2 publication Critical patent/JPH0455536B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805—Shape
    • H01L2224/4809—Loop shape
    • H01L2224/48091—Arched
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/481—Disposition
    • H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
    • H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item

Landscapes

  • Structure Of Printed Boards (AREA)
  • Parts Printed On Printed Circuit Boards (AREA)
JP18591386A 1986-08-07 1986-08-07 導電性シ−ト及びそれによるメタライズ方法 Granted JPS6342148A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP18591386A JPS6342148A (ja) 1986-08-07 1986-08-07 導電性シ−ト及びそれによるメタライズ方法

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP18591386A JPS6342148A (ja) 1986-08-07 1986-08-07 導電性シ−ト及びそれによるメタライズ方法

Publications (2)

Publication Number Publication Date
JPS6342148A JPS6342148A (ja) 1988-02-23
JPH0455536B2 true JPH0455536B2 (enrdf_load_stackoverflow) 1992-09-03

Family

ID=16179069

Family Applications (1)

Application Number Title Priority Date Filing Date
JP18591386A Granted JPS6342148A (ja) 1986-08-07 1986-08-07 導電性シ−ト及びそれによるメタライズ方法

Country Status (1)

Country Link
JP (1) JPS6342148A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2866962B2 (ja) * 1988-11-21 1999-03-08 京セラ株式会社 半導体素子収納用パッケージの製造方法

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62276703A (ja) * 1986-05-26 1987-12-01 住友金属鉱山株式会社 金被膜形成方法

Also Published As

Publication number Publication date
JPS6342148A (ja) 1988-02-23

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