JPH0454259B2 - - Google Patents

Info

Publication number
JPH0454259B2
JPH0454259B2 JP61289551A JP28955186A JPH0454259B2 JP H0454259 B2 JPH0454259 B2 JP H0454259B2 JP 61289551 A JP61289551 A JP 61289551A JP 28955186 A JP28955186 A JP 28955186A JP H0454259 B2 JPH0454259 B2 JP H0454259B2
Authority
JP
Japan
Prior art keywords
address
memory
interlock
storage device
data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP61289551A
Other languages
English (en)
Japanese (ja)
Other versions
JPS63141150A (ja
Inventor
Noryuki Toyoki
Shigeru Kusuyama
Yukihiko Kitano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP61289551A priority Critical patent/JPS63141150A/ja
Publication of JPS63141150A publication Critical patent/JPS63141150A/ja
Publication of JPH0454259B2 publication Critical patent/JPH0454259B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Storage Device Security (AREA)
  • Memory System Of A Hierarchy Structure (AREA)
JP61289551A 1986-12-03 1986-12-03 メモリインタロツク制御方式 Granted JPS63141150A (ja)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP61289551A JPS63141150A (ja) 1986-12-03 1986-12-03 メモリインタロツク制御方式

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP61289551A JPS63141150A (ja) 1986-12-03 1986-12-03 メモリインタロツク制御方式

Publications (2)

Publication Number Publication Date
JPS63141150A JPS63141150A (ja) 1988-06-13
JPH0454259B2 true JPH0454259B2 (enrdf_load_stackoverflow) 1992-08-28

Family

ID=17744703

Family Applications (1)

Application Number Title Priority Date Filing Date
JP61289551A Granted JPS63141150A (ja) 1986-12-03 1986-12-03 メモリインタロツク制御方式

Country Status (1)

Country Link
JP (1) JPS63141150A (enrdf_load_stackoverflow)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2507544B2 (ja) * 1988-06-29 1996-06-12 富士通株式会社 記憶制御装置

Also Published As

Publication number Publication date
JPS63141150A (ja) 1988-06-13

Similar Documents

Publication Publication Date Title
US6587931B1 (en) Directory-based cache coherency system supporting multiple instruction processor and input/output caches
US4394731A (en) Cache storage line shareability control for a multiprocessor system
US5249284A (en) Method and system for maintaining data coherency between main and cache memories
JPH0743670B2 (ja) ストアスルーキャッシュ管理システム
JPH0668735B2 (ja) キヤツシユメモリ−
JPS6284350A (ja) 階層キヤツシユメモリ装置および方法
JPH0250237A (ja) マルチプロセッサ・データ処理システムおよびそれに用いられるキャッシュ装置
JPH0137773B2 (enrdf_load_stackoverflow)
US4930106A (en) Dual cache RAM for rapid invalidation
WO1997004392A1 (en) Shared cache memory device
JPH0551937B2 (enrdf_load_stackoverflow)
JPH0454259B2 (enrdf_load_stackoverflow)
JPS60237553A (ja) キヤツシユコヒ−レンスシステム
JP2786124B2 (ja) 共有メモリ型マルチプロセッサシステム
JPH055137B2 (enrdf_load_stackoverflow)
JPH07234819A (ja) キャッシュメモリ
JPS6329297B2 (enrdf_load_stackoverflow)
JPH03230238A (ja) キャッシュメモリ制御方式
JP3564343B2 (ja) キャッシュバイパス時のデータ転送装置と方法
JP2946942B2 (ja) ベクトルデータ処理装置
JP3293872B2 (ja) キャッシュ一致化方式
JPH05342101A (ja) 階層キャッシュ・メモリ
JP2982197B2 (ja) キャッシュ用バスモニタ回路
KR950000389B1 (ko) 다중 프로세서 시스템에서 메모리 모듈의 상태변화 시험방법
JP2588547B2 (ja) マルチcpuシステム