JPH0453238A - Manufacture of insulation-sealed semiconductor device - Google Patents
Manufacture of insulation-sealed semiconductor deviceInfo
- Publication number
- JPH0453238A JPH0453238A JP16321290A JP16321290A JPH0453238A JP H0453238 A JPH0453238 A JP H0453238A JP 16321290 A JP16321290 A JP 16321290A JP 16321290 A JP16321290 A JP 16321290A JP H0453238 A JPH0453238 A JP H0453238A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor device
- oxide film
- resin
- pulse voltage
- etchant
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 28
- 238000004519 manufacturing process Methods 0.000 title claims description 10
- 238000000034 method Methods 0.000 claims abstract description 27
- 239000011347 resin Substances 0.000 claims abstract description 21
- 229920005989 resin Polymers 0.000 claims abstract description 21
- 238000007789 sealing Methods 0.000 claims description 5
- 238000007747 plating Methods 0.000 claims description 2
- 238000005538 encapsulation Methods 0.000 claims 1
- 238000005530 etching Methods 0.000 abstract description 14
- 238000003486 chemical etching Methods 0.000 abstract description 5
- 239000002184 metal Substances 0.000 abstract description 5
- 229910052751 metal Inorganic materials 0.000 abstract description 5
- 239000002253 acid Substances 0.000 abstract description 3
- 239000003513 alkali Substances 0.000 abstract 1
- 239000002585 base Substances 0.000 abstract 1
- 238000007598 dipping method Methods 0.000 abstract 1
- 150000002739 metals Chemical class 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 5
- 239000007788 liquid Substances 0.000 description 3
- 230000008961 swelling Effects 0.000 description 3
- 239000004020 conductor Substances 0.000 description 2
- 238000005868 electrolysis reaction Methods 0.000 description 2
- 238000005498 polishing Methods 0.000 description 2
- MYMOFIZGZYHOMD-UHFFFAOYSA-N Dioxygen Chemical compound O=O MYMOFIZGZYHOMD-UHFFFAOYSA-N 0.000 description 1
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 229910001882 dioxygen Inorganic materials 0.000 description 1
- 230000005684 electric field Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 239000007789 gas Substances 0.000 description 1
- 239000001257 hydrogen Substances 0.000 description 1
- 229910052739 hydrogen Inorganic materials 0.000 description 1
- 238000007654 immersion Methods 0.000 description 1
- 239000002198 insoluble material Substances 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
- 238000003756 stirring Methods 0.000 description 1
Landscapes
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
この発明は、絶縁刺止型半導体装置の製造方法に関する
ものである。DETAILED DESCRIPTION OF THE INVENTION [Industrial Field of Application] The present invention relates to a method of manufacturing an insulating pierced type semiconductor device.
説明の都合］二、従来およびこの発明に係る半導体装置
とエツチングの対象となる層及び樹脂バリの位置とその
状態について、第３図によって概略説明する。[Convenience of Explanation] 2. The conventional semiconductor device and the semiconductor device according to the present invention, the layers to be etched, and the positions and conditions of resin burrs will be schematically explained with reference to FIG.
第３図において、半導体装置の絶縁封止部（５）から突
出する外部リード（６）上に、半導体装置の製造中にで
きた酸化膜、等のエツチング対象層（７）が存在し、そ
の層上で半導体装置の絶縁封止部（５）近傍に樹脂バリ
（８）が存在している。In FIG. 3, there is a layer (7) to be etched, such as an oxide film formed during the manufacturing of the semiconductor device, on the external lead (6) protruding from the insulating sealing part (5) of the semiconductor device. A resin burr (8) exists on the layer near the insulating sealing part (5) of the semiconductor device.
次に従来の半導体装置の外装処理（樹脂バリ取り、化学
エツチング、外装加工〕工程を第４１図によって説明す
る。Next, the conventional exterior processing (resin deburring, chemical etching, exterior processing) process of a semiconductor device will be explained with reference to FIG.
第４図に示す樹脂バリ取り工程においては、半導体素子
（図示せず〕を樹脂によシ絶縁封止した時に発生した樹
脂バリ（８）を、樹脂膨潤液に浸漬或は、電解印加する
ことで、樹脂膨潤液が電気分解をおこし、水素・酸素ガ
スの発生で樹脂バリを除去する。In the resin deburring process shown in FIG. 4, resin burrs (8) generated when a semiconductor element (not shown) is insulated and sealed with resin are immersed in a resin swelling liquid or electrolytically applied. The resin swelling liquid undergoes electrolysis, and the resin burr is removed by the generation of hydrogen and oxygen gas.
次に、化学エツチング、酸化膜除去工程で、外部リード
（６）上に所在する酸化膜等エツチング対象層（７）を
化学エツチング液に浸漬或は電解印加し研磨して除去す
る。その後、外装加工工程で、めっきを施した後次工程
送シとされていた。Next, in a chemical etching and oxide film removal process, the layer (7) to be etched, such as an oxide film, located on the external lead (6) is removed by immersion in a chemical etching solution or by electrolytic application and polishing. After that, in the exterior processing process, plating was applied and then sent to the next process.
従来の半導体装置の製造方法は、以上の様に行われてい
たので、樹脂バ！Ｊ Ｉｆ１２Ｄ用の樹脂膨潤液と、エ
ツチング対象層を研磨するエツチング液の２つが必要で
あり、また、工程が複雑である等の問題点があった。The conventional manufacturing method for semiconductor devices was carried out as described above, so the resin bar! This method requires two components: a resin swelling solution for JIf12D and an etching solution for polishing the layer to be etched, and there are also problems in that the process is complicated.
この発明は、上記のような問題点を解消するためになさ
れたもので、工程の簡略化、処理液数の減少、工期短縮
等を図ることができる半導体装置の製造方法を得ること
を目的とする。This invention was made to solve the above-mentioned problems, and aims to provide a method for manufacturing a semiconductor device that can simplify the process, reduce the number of processing liquids, shorten the construction period, etc. do.
〔課題を解決するだめの手段コ
この発明に係るや導体装鉦の製造方法は、エツチング液
に所定の電界を印加して、樹脂バリ取り工程と酸化膜エ
ツチング工程とを同時に行うようにしたものである。[Means for solving the problem] The method for manufacturing a conductor mounting rod according to the present invention is such that a predetermined electric field is applied to an etching solution to perform a resin deburring process and an oxide film etching process at the same time. It is.
この発明における半導体装置の製造方法は、酸或はアル
カリ糸の酸化膜等をエツチングするエツチング液中で製
品にパルス糸の電解を印加することでその液が′市気分
解を起こし、水素・酸素ガスを発生することにより、リ
ード上の樹脂バリを除去し、またかつ、エツチング液の
働きで酸化膜等も化学的エツチングが行える。The method of manufacturing a semiconductor device according to the present invention involves applying pulsed electrolysis to the product in an etching solution that etches the oxide film, etc. of acid or alkaline thread. By generating gas, resin burrs on the leads can be removed, and oxide films and the like can also be chemically etched by the action of the etching solution.
以下、この発明の一実施例を図について説明する。第コ
ー図において、（］）は絶縁封圧型半導体装置（以下、
半導体装置と略す） 、（２＞は不溶性金属の電極、（
３）は半導体装置（１）内のリードフレーム表面に存在
する酸化膜等をエツチングする酸或はアルカリ系のエツ
チング溶液、（４）はエツチング？＆ （３）が満たさ
れた槽である。An embodiment of the present invention will be described below with reference to the drawings. In the diagram, (]) indicates an insulated pressure type semiconductor device (hereinafter referred to as
(abbreviated as semiconductor device), (2> is an insoluble metal electrode, (
3) is an acid or alkaline etching solution that etches the oxide film etc. present on the surface of the lead frame in the semiconductor device (1), and (4) is etching? & (3) is a filled tank.
第２図において、（９）はパルス電圧である。In FIG. 2, (9) is a pulse voltage.
次に動作について説明する。第１図において、第３図に
示すように外部リード（６）上に酸化膜等エツチング対
象層（７）及び樹脂バリ（８ンが発生している半導体装
ｔ （１）と電極とする不溶性金員（２）とをエツチン
グ液（３）が満たされた槽（４）内に浸漬する。Next, the operation will be explained. In Fig. 1, as shown in Fig. 3, there is a layer to be etched (7) such as an oxide film on the external lead (6) and a semiconductor device (1) on which resin burrs (8) are generated, and an insoluble material to be used as an electrode. The metal member (2) is immersed in a tank (4) filled with an etching solution (3).
次に、槽（４）内のエツチング液（３）を撹拌しながら
その半導体装置（１）に負極（或は正極〕、不溶性金属
の電極（２）に第２図（ａ）に示す正極（或は第２図（
ｂ）に示す負極）となるような直流のパルス電圧（９）
を印加する０特にバルヌ電圧（９）を使用するのは、通
電中は、樹脂バリ取り工程の働きを、また、停電中は化
学エツチング工程の働きをするためにパルスを用いる。Next, while stirring the etching solution (3) in the tank (4), a negative electrode (or positive electrode) is attached to the semiconductor device (1), and a positive electrode (or positive electrode) is attached to the insoluble metal electrode (2) as shown in FIG. 2(a). Or Figure 2 (
DC pulse voltage (9) that results in the negative electrode shown in b)
In particular, the Varne voltage (9) is used to apply pulses to perform the resin deburring process during power supply and to perform the chemical etching process during power outage.
以上のように、この発明によれば、酸化膜エツチング用
のエツチング液に半導体装置を浸漬しながらパルス電圧
を印加するように構成しだので、工程の簡略化ができ、
処理液の数が減少し、また半導体装置の製造工期の短縮
等が得られる効果がある。As described above, according to the present invention, the pulse voltage is applied while the semiconductor device is immersed in the etching solution for etching the oxide film, so the process can be simplified.
This has the effect of reducing the number of processing solutions and shortening the manufacturing period for semiconductor devices.
第１図はこの発明の一実施例による半導体装置の製造方
法概略図、第２図（ａ） 、 （ｔ：））は用いるパル
ス電圧の波形画、第３図は酸化膜等のエツチング対象層
及び樹脂バリ等の状態を示す半導体装置の断面図、第４
図は従来の半導体装置の外装処理工程経路図である。
図（′こおいて、（１）ｌｊ、絶縁封止型、′１″導体
装良、（２）は不溶性金属の′［ＩＬ極、（３）はエツ
チング液、（４）は槽、（５）は半導体装置の絶縁封止
部、（６）は外部リード、（７）は酸化膜等エツチング
対象層、（３）は樹脂バリ、（９）はパルス電圧である
。
なお、図中、同一符号は同一、又は相当部分を示す。FIG. 1 is a schematic diagram of a method for manufacturing a semiconductor device according to an embodiment of the present invention, FIG. 2 (a) and (t:)) are waveform diagrams of the pulse voltage used, and FIG. 3 is a diagram of a layer to be etched such as an oxide film. and a cross-sectional view of the semiconductor device showing the state of resin burrs, etc., No. 4
The figure is a conventional semiconductor device exterior processing process route diagram. Figure ('Here, (1) lj, insulated sealing type, '1'' conductor equipped, (2) insoluble metal '[IL pole, (3) etching solution, (4) tank, ( 5) is an insulating sealing part of a semiconductor device, (6) is an external lead, (7) is a layer to be etched such as an oxide film, (3) is a resin burr, and (9) is a pulse voltage. The same reference numerals indicate the same or equivalent parts.
Claims (1)
封止工程により発生したリード上のバリを除去する工程
と、めつきを析出させるリード上の酸化膜を除去する工
程を所定のパルス電圧を印加して同一工程で行うことを
特徴とする絶縁封止型半導体装置の製造方法。In the exterior processing process of an insulating sealed semiconductor device, a predetermined pulse voltage is applied to remove burrs on the leads caused by the resin sealing process and to remove oxide films on the leads that cause plating. 1. A method for manufacturing an insulating encapsulation type semiconductor device, characterized in that the steps are performed in the same process.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16321290A JPH0453238A (en) | 1990-06-20 | 1990-06-20 | Manufacture of insulation-sealed semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16321290A JPH0453238A (en) | 1990-06-20 | 1990-06-20 | Manufacture of insulation-sealed semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0453238A true JPH0453238A (en) | 1992-02-20 |
Family
ID=15769431
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16321290A Pending JPH0453238A (en) | 1990-06-20 | 1990-06-20 | Manufacture of insulation-sealed semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0453238A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060065A (en) * | 2004-08-20 | 2006-03-02 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same |
-
1990
- 1990-06-20 JP JP16321290A patent/JPH0453238A/en active Pending
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2006060065A (en) * | 2004-08-20 | 2006-03-02 | Mitsubishi Electric Corp | Semiconductor device and method for manufacturing the same |
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