JPH0452577A - Pattern generator for ic test - Google Patents

Abstract

PURPOSE:To enable test operation frequency to be increased by supplying output of a plurality of multiplexers to a separate transmission path, differentiating each by a differentiation circuit and by multiplexing the outputs. CONSTITUTION:Eight output pulses of a waveform formatter 12 are supplied to multiplexers 21 - 24, two at a time. Then, output of the multiplexers 21 - 24 is supplied to differentiation circuits 31 - 34 through transmission paths 25 - 28 and is differentiated. Then, each output of the circuits 31 and 32 is multiplexed by a multiplexer 35 and each output of the circuits 33 and 34 is multiplexed by a multiplexer 36. Further, the output of the multiplexer 35 sets a flip-flop 16 and the output of a multiplexer 36 resets the flip-flop 16. Then, the output of the flip-flop 16 is supplied to a driver 18. Thus, by performing differentiation and multiplexing the differentiation pulses, the driver 18 can be driven at a high frequency, namely test operation frequency can be increased.

Description

[Detailed Description of the Invention] "Industrial Application Field" This invention is applicable to testing ICs (semiconductor integrated circuits).
This invention relates to an IC test pattern generator that generates test signals (test patterns, clock patterns) to be applied to the IC, and is intended to be able to generate particularly high-speed patterns.

"Prior Art" FIG. 3 shows a conventional IC test pattern generator. A plurality of patterns generated from a pattern generation section 11 are waveform-shaped into pulses by a waveform formatter 12 according to the timing from a timing generator 13. be done. Two sets of outputs from the waveform formatter 12 are supplied to a multiplexer 14 and combined, and two sets of other outputs are combined at a multiplexer 15. The output of the multiplexer 14 sets the flip-flop 16.
is reset by the output of multiplexer 15. The output of the flip-flop 16 is supplied to the driver 1B through a transmission line 17 such as a cable, and the output of the driver 18 is
Although not shown in the figure, the IC element under test is driven.

The highest frequency of the pattern that can be generated from the pattern generator 11 is determined by the test equipment, and a pattern with a higher frequency than that frequency is generated. By combining the two sets using multiplexers 14 and 15, a pattern with a frequency twice as high as the highest frequency that can be generated by the pattern generating section 11 is created.

"Problem to be Solved by the Invention" As shown in FIG. 4A, if the pulse width Pw of the output waveform of the flip-flop 16 is wide, the input waveform of the driver 18 exceeds the threshold value, so that the IC element under test is correctly driven. However, if the pulse width P- of the output waveform of the flip-flop 16 is narrow as shown in FIG. , it becomes impossible to drive the IC device under test. For this reason, the highest test operation frequency was determined by the output pulse width of the flip-flop 16.

Particularly in large-sized semiconductor test equipment, the transmission line 17 connecting the mounting part of the IC element under test and the measurement part is relatively long, making it impossible to increase the maximum test operation frequency.

"Means for Solving the Problem" According to the present invention, a plurality of first multiplexers are provided for synthesizing two sets of output pulses of a waveform format, and each output of these first multiplexers is transmitted to a separate transmission source. The outputs of these transmission lines are differentiated by differentiating circuits, and two sets of second multiplexers are provided to combine the two sets of output pulses of these differentiating circuits, and the output of one of the second multiplexers is used as a flip-flop The output of the other second multiplexer resets the flip-flop, and the output of this flip-flop drives the driver.

"Embodiment" FIG. 1 shows an embodiment of the present invention, and parts corresponding to those in FIG. 3 are given the same reference numerals. In this example, the eight output pulses of the waveform formatter 1208 are supplied two by two to the first multiplexers 21.22, 23.24, respectively, and are combined. These first multiplexers 21 to 2
Each of the outputs of 4 is supplied to one end of each of transmission lines 25 to 28, respectively. The outputs from the other ends of these transmission lines 25 to 28 are respectively supplied to differentiating circuits 31 to 34 and differentiated. The outputs of the differentiating circuits 31 and 32 are combined by a second multiplexer 35, and the outputs of the differentiating circuits 33 and 34 are combined by a second multiplexer 36.

The output of the second multiplexer 35 sets the flip-flop 16, and the output of the second multiplexer 36 resets the flip-flop 16. The output of flip-flop 16 is provided to driver 18.

When the input waveform of the differentiating circuit 31 is as shown in FIG. 2A, for example, the output waveform of the differentiating circuit 31 is a differentiated pulse at the leading edge of the input waveform, as shown in FIG. 2B. On the other hand, differentiator circuit 3
If the input waveform of the differential circuit 32 is delayed by approximately half a period with respect to the input waveform of the differentiating circuit 310 as shown in FIG. 2C, the output waveform of the differentiating circuit 32 will be as shown in the second figure. The output waveform of the second multiplexer 35 is as shown in FIG.
This is a composite of the waveforms shown in FIG. 2B and D. Similarly, the output waveform of the second multiplexer 36 becomes a waveform shown in FIG. 2F, for example, which is delayed with respect to the waveform shown in FIG. 2E. Therefore, the output waveform of the flip-flop 16 becomes as shown in FIG. 2G, and the output waveform of the driver 1st is also the same.

Now, the pulse width Pw of the input waveform of the differentiating circuit 31 is the transmission line 2.
In the conventional pattern generator shown in FIG. 3, this pulse width P- becomes the pulse width of the input waveform of the driver 18, and this determines the highest test frequency. In this invention, by differentiating and further synthesizing the differentiated pulses, the driver 18 is driven at twice the frequency of the input waveform of the differentiating circuit 31, that is, the conventional driver drive waveform, as shown in FIG. 2G. can do. In other words, the test operating frequency can be doubled compared to the conventional method.

Note that the differentiating circuits 31 to 34 and the second multiplexer 35.3
6. The flip-flop 16 and driver 18 are all placed close together. Alternatively, the output pulses of the waveform formatter 12 may be directly supplied to the transmission lines 25 to 28, respectively.

"Effects of the Invention" As described above, according to the present invention, the measurement side and the
A clock having a frequency twice as high as the maximum clock frequency that can be transmitted through the transmission lines 25 to 28 connecting to the C element side can be applied to the IC element under test.

[Brief explanation of drawings]

Fig. 1 is a block diagram showing an embodiment of the present invention, Fig. 2 is a time chart showing an example of its operation, Fig. 3 is a block diagram showing a conventional pattern generator, and Fig. 4 explains its problems. FIG.

Claims (1)

[Claims] (1) A plurality of first multiplexers that combine two sets of output pulses of the waveform format, a plurality of transmission lines to which the outputs of these first multiplexers are supplied, and a plurality of transmission lines that differentiate the output of each of these transmission lines. a differentiating circuit, two sets of second multiplexers that combine the two sets of output pulses of these differentiating circuits, one of which is set by the output of the second multiplexer, and the other of which is reset by the output of the second multiplexer; A pattern generator for IC testing, comprising: a flip-flop that supplies a signal to a driver; and a pattern generator for IC testing.