JPH0452246U - - Google Patents

Info

Publication number
JPH0452246U
JPH0452246U JP9598190U JP9598190U JPH0452246U JP H0452246 U JPH0452246 U JP H0452246U JP 9598190 U JP9598190 U JP 9598190U JP 9598190 U JP9598190 U JP 9598190U JP H0452246 U JPH0452246 U JP H0452246U
Authority
JP
Japan
Prior art keywords
digital control
control device
memory
program
programming device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9598190U
Other languages
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9598190U priority Critical patent/JPH0452246U/ja
Publication of JPH0452246U publication Critical patent/JPH0452246U/ja
Pending legal-status Critical Current

Links

Description

【図面の簡単な説明】[Brief explanation of the drawing]

第1図はこの考案の一実施例によるプログラミ
ング装置のメモリ構成図、第2図は従来のプログ
ラミング装置のメモリ構成図、第3図はこの考案
の一実施例及び従来のデイジタル制御装置及びプ
ログラミング装置のハードウエア構成図、第4図
はこの考案の一実施例及び従来のプログラミング
装置の動作フロー図である。 図において、1はデイジタル制御装置、2はプ
ログラミング装置、3aはデイジタル制御装置1
のCPU、3bはプログラミング装置2のCPU
、4aはデイジタル制御装置1のメモリ、4bは
プログラミング装置2のメモリである。なお、図
中同一符号は同一、又は相当部分を示す。
FIG. 1 is a memory configuration diagram of a programming device according to an embodiment of this invention, FIG. 2 is a memory configuration diagram of a conventional programming device, and FIG. 3 is a memory configuration diagram of an embodiment of this invention and a conventional digital control device and programming device. FIG. 4 is an operational flow diagram of an embodiment of this invention and a conventional programming device. In the figure, 1 is a digital control device, 2 is a programming device, and 3a is a digital control device 1.
3b is the CPU of programming device 2.
, 4a is a memory of the digital control device 1, and 4b is a memory of the programming device 2. Note that the same reference numerals in the figures indicate the same or equivalent parts.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] メモリに格納されたプログラムを使用して各種
制御を実行するデイジタル制御装置の上記プログ
ラムの作成、修正、複写、及び照合等の加工処理
を行うデイジタル制御装置用プログラミング装置
において、上記デイジタル制御装置のメモリの全
プログラム格納容量よりも上記プログラミング装
置のメモリの容量を大きくし、上記デイジタル制
御装置から独立した状態で上記プログラムの加工
処理を行うことを特徴とするデイジタル制御装置
用プログラミング装置。
In a programming device for a digital control device that performs processing such as creation, modification, copying, and collation of the program of a digital control device that executes various controls using a program stored in a memory, the memory of the digital control device A programming device for a digital control device, characterized in that the memory capacity of the programming device is larger than the total program storage capacity of the programming device, and the program is processed independently from the digital control device.
JP9598190U 1990-09-11 1990-09-11 Pending JPH0452246U (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9598190U JPH0452246U (en) 1990-09-11 1990-09-11

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9598190U JPH0452246U (en) 1990-09-11 1990-09-11

Publications (1)

Publication Number Publication Date
JPH0452246U true JPH0452246U (en) 1992-05-01

Family

ID=31835152

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9598190U Pending JPH0452246U (en) 1990-09-11 1990-09-11

Country Status (1)

Country Link
JP (1) JPH0452246U (en)

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159148A (en) * 1982-03-18 1983-09-21 Toshiba Corp Program loader

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS58159148A (en) * 1982-03-18 1983-09-21 Toshiba Corp Program loader

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