JPH0451339A - Setting processing system for address conversion value - Google Patents

Abstract

PURPOSE:To quickly set a new address conversion value by issuing busy display from a memory controller to an access generator when the new address conversion value is set from an external setting device. CONSTITUTION:When an address conversion value is set on an address conversion register 13, the external setting device 4 performs processing as if a port 14 connected to a memory device 2 is in use by supplying a busy signal to a port 11 via an OR gate 15. In such a way, a method to make a following access request await is employed by displaying the busy signal to the access generator 3 via the port 11, not cutting off the access request when the address conversion value is set by the external setting device 4, therefore, the address conversion value can be set independently from the access request.

Description

[Detailed Description of the Invention] (Summary) Regarding an address translation value setting processing method for setting an address translation value necessary for address translation processing executed by a storage control device, the present invention relates to an address translation value setting processing method during access processing to a storage device. Also, again
The purpose is to allow new address translation values to be set quickly even when there are access requests that cannot be blocked. However, by configuring the access generating device to issue a busy indication to the access generating device, a new address translation value can be set quickly.

[Industrial application field]

The present invention relates to an address translation value setting processing method for setting address translation values necessary for address translation processing executed by a storage control device, and in particular, even during access processing to a storage device. The present invention relates to an address translation value setting processing method that allows a new address translation value to be quickly set even when there is an access request that cannot be blocked.

A storage control device that controls a storage device performs a conversion process on an address sent from a CPU or a channel device based on an address conversion value to create address information for accessing the storage device. The address translation value required for this address translation process will be set by the service processor, etc., but this setting can be done even during access processing to the storage device, and when an access request that cannot be blocked occurs. Even when there is
Be able to execute quickly (preferably).

[Conventional technology]

FIG. 3 illustrates the system configuration of a storage control device to which the present invention is applied. As shown in this figure, one or more storage devices 2 to be controlled are connected to a storage control device 1 to which the present invention is applied, as well as a CPU 3a, a channel device 3b, etc. one or more access generators such as
a will be connected.

The storage control device 1 includes a connection circuit 10 that executes connection processing with the CPU 3a and the channel device 3b, and a boat that receives and receives access requests from the CPU 3a and the channel device 3b provided via the connection circuit 10. 11, an address for creating address information for accessing the storage device 2 by executing a conversion process using the address information received by the boat 11 and the address conversion value set by the service processor 4a. A conversion circuit 12;
An address translation register 13 is provided corresponding to the address translation circuit 12 and stores an address translation value set from the service processor 4a, and an address translation register 13 that receives and receives address information created by the address translation circuit 12 and stores it in the storage device 2. A port 14 for transfer is provided. Although not shown in this figure, a priority circuit for performing priority control is further provided between the port 14 and the storage device 2.

In the storage control device 1 configured as described above, conventionally, the service processor 4a controls the address translation register 1.
When setting a new address conversion value to 3, first, the processing of access requests from the CPU 3a and the channel device 3b is stopped by shutting off the connection circuit 10,
Next, the address translation registers 13 are sequentially selected and new address translation values are set.

[Problem to be solved by the invention]

However, in such conventional technology, there is a problem in that when access requests from the CPU 3a or the channel device 3b are being accepted, a new address conversion value cannot be set until the access requests are completed. Since systems connected to a network must accept and accept access requests from other systems, they may receive and accept access requests that cannot be blocked. The problem was that it could not be configured.

The present invention has been made in view of such circumstances, and even during access processing to the storage device 2,
The purpose of the present invention is to provide a new address translation value setting processing method that allows a new address translation value to be quickly set in an address translation register 13 even when there is an access request that cannot be blocked.

[Means to solve the problem] FIG. 1 is a diagram showing the basic configuration of the present invention.

In the figure, 1 is a storage control device equipped with the present invention, 2 is one or more storage devices to be controlled by the storage control device 1, and 3
4 is one or more access generation devices that issue access requests to the storage device 2, and 4 is an external setting device that executes address conversion value setting processing for the storage control device 1.

This storage control device 1 is provided with a boat 11 that is compatible with the access generation device 3 and receives and receives access requests input from the access generation device 3; An address conversion circuit 1 that creates address information for accessing the storage device 2 by performing a conversion process using the taken address information and the address conversion value set by the external setting device 4.
2, an address translation register 13 for storing an address translation value set from the external setting device 4, and an address translation register 13 corresponding to the address translation circuit 12, which receives and receives address information created by the address translation circuit 12, and serves as a storage device. When the external setting device 4 sets an address translation value in the address translation register 13,
4 to the boat 11.

[Operation] In the present invention, when setting an address translation value to the address translation register 13, the external setting device 4 gives a busy signal to the baud I/11 via the OR gate 15, as if it were a storage device. Processing is performed as if the boat 14 connected to 2 is in use. In this way, in the present invention, when the external setting device 4 sets an address translation value, it displays a busy signal to the access generating device 3 via the boat 11 instead of blocking the access request. By doing so, the address translation value can be set independently of the access request, since it uses a method of making subsequent access requests wait.

From now on, a new address translation value can be set quickly even during access processing to the storage device 2 or even when there is an access request that cannot be blocked.

(Example) Hereinafter, the present invention will be explained in detail according to examples.

FIG. 2 illustrates an embodiment of the storage control device 1 equipped with the present invention. In the figure, the same parts as those explained in FIGS. 1 and 3 are indicated by the same symbols.

11a is a boat that receives and receives logical address information sent from the channel device 3b; llb is a boat that receives and receives valid information of the sent address information; 13-i;
(i=1 to n) are n address translation registers that hold address translation values used for address translation processing, 14
A is a port that receives and receives address information created by the address conversion circuit 12, 14b is a port that receives valid information from the boat Ilb associated with the created address information, and 16 is a port that receives the valid information from the boat llb that is associated with the created address information. a priority circuit that controls the priority of access requests sent from a plurality of channel devices 3b, etc.; 17 is a selector that selects the address translation value held in the address translation register 13-i and supplies it to the address translation circuit 12;
19 is an AND gate that calculates and outputs the logical product of the busy signal issued by the priority circuit 16 and the valid signal output from the boat 14b, and 19 is the logic between the output of the AND gate 18 and the par-and-do signal output from the boat llb. This is an AND gate that calculates and outputs the product.

As shown in this figure, the OR gate 15 is connected to the service processor 4a that is input to the address conversion register 13-1.
, and the output signal of the AND gate 19, and the logical sum output is sent to the channel device 3b.
is output as a busy signal to the boat I.
Processing is performed to output a hold signal for holding the operation of la and b. And A.N.
The D gate 18 outputs the logical product output to the A and ND gates 19, and also outputs it as a hold signal to hold the operation to the boats 14a and 14b.

Next, the operation processing of the present invention configured as described above will be explained.

When there is an access request from the channel device 3b, the boat 11a holds the address information of the access request sent from the channel device 3b, and also
1lb operates to hold valid information for its address information. When the boat lla holds the address information in this way, the address conversion circuit 12 converts the held address information and the address conversion value held by the address conversion register 13-1 input via the selector 17. The address information is used to create address information for accessing the storage device 2, and the created address information is sent to the boat 14a. And pot □ 14
When a holds this created address information and the boat 14b holds valid information associated with this address information, the priority circuit 16
Processing is performed to access the storage device 2 according to the priority of the access request.

During this process, when the priority circuit 16 indicates a busy state, the AND gate 18 is
By outputting the L level, the operations of the boats 14a and 14b are held, and the AND gate 19 outputs the H level that indicates the logical product is established.
By outputting the l level, the operations of the ports lla and llb are held, and the OR gate 15 outputs a busy signal to the channel Wsb to make it wait for the subsequent access request. Process.

When controlling access processing in this way, the service processor 4a
When changing the address conversion value of 3 heat, a cent signal is sent to the address conversion register 13-1, so the OR gate 15 changes the address conversion register 13-1.
The set signal input to j is treated in the same way as the busy signal sent from the AND gate 19, and when this set signal is input, the operations of the ports lla and b are held, and the Then, a busy signal is output to make the subsequent access request wait. By outputting this busy signal, access requests to the storage device 2 are temporarily interrupted, allowing the service processor 4a to perform address conversion value setting processing. Then, when the setting of the address conversion value is completed, OR gate 1
5 cancels the busy display, so the access process is immediately restarted.

According to this busy indication, the address conversion value setting process can be performed even during the access process to the storage device 2 or even when there is an access request that cannot be blocked.

[Effects of the Invention] As explained above, according to the present invention, the storage control device can prevent access to the storage device even during access processing to the storage device or when there is an access request that cannot be blocked. This makes it possible to quickly set the address conversion value required for executing address conversion processing.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing the principle configuration of the present invention, FIG. 2 is an embodiment of the present invention, and FIG. 3 is a system configuration diagram of a storage control device. In the figure, ■ is a storage control device, 2 is a storage device, 3 is an access generation device, 3a is a CPU, 3b is a channel device, 4 is an external setting device, and 4a is a service processor.

Claims (1)

[Claims] One or more storage devices (2) are connected, and one
one or more access generating devices (3) are connected, and
An address conversion circuit (12) that converts address information sent from the access generation device (3), and an address conversion register (13) that stores an address conversion value used in the address conversion process of the address conversion circuit (12). ), the storage control device (1) is configured to control access processing to the storage device (2) according to address information converted by the address conversion circuit (12). ) is configured to issue a busy indication to the access generating device (3) when an address translation value is set in the address translation register (13) from the external setting device (4). An address translation value setting processing method characterized by processing so that a new address translation value can be quickly set in the address translation register (13).