JPH0450935U - - Google Patents

Info

Publication number
JPH0450935U
JPH0450935U JP9371090U JP9371090U JPH0450935U JP H0450935 U JPH0450935 U JP H0450935U JP 9371090 U JP9371090 U JP 9371090U JP 9371090 U JP9371090 U JP 9371090U JP H0450935 U JPH0450935 U JP H0450935U
Authority
JP
Japan
Prior art keywords
pulse signal
pass filter
low
output
charge pump
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9371090U
Other languages
English (en)
Japanese (ja)
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed filed Critical
Priority to JP9371090U priority Critical patent/JPH0450935U/ja
Publication of JPH0450935U publication Critical patent/JPH0450935U/ja
Pending legal-status Critical Current

Links

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
JP9371090U 1990-09-06 1990-09-06 Pending JPH0450935U (zh)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9371090U JPH0450935U (zh) 1990-09-06 1990-09-06

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9371090U JPH0450935U (zh) 1990-09-06 1990-09-06

Publications (1)

Publication Number Publication Date
JPH0450935U true JPH0450935U (zh) 1992-04-28

Family

ID=31831132

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9371090U Pending JPH0450935U (zh) 1990-09-06 1990-09-06

Country Status (1)

Country Link
JP (1) JPH0450935U (zh)

Cited By (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002190734A (ja) * 2000-11-28 2002-07-05 Texas Instruments Inc Ａｄｓｌ周波数ロック・アプリケーション用のフェーズ・ロックド・ループ及びその制御方法
WO2008078452A1 (ja) * 2006-12-26 2008-07-03 Nihon Dempa Kogyo Co., Ltd. 発振周波数制御回路
WO2009081516A1 (ja) * 2007-12-25 2009-07-02 Nihon Dempa Kogyo Co., Ltd. 発振周波数制御回路
JP2010273299A (ja) * 2009-05-25 2010-12-02 Furuno Electric Co Ltd 基準周波数発生装置
JP2011024274A (ja) * 2010-11-05 2011-02-03 Nippon Dempa Kogyo Co Ltd 発振周波数制御回路
CN107005245A (zh) * 2014-12-08 2017-08-01 古野电气株式会社 基准信号产生装置

Cited By (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002190734A (ja) * 2000-11-28 2002-07-05 Texas Instruments Inc Ａｄｓｌ周波数ロック・アプリケーション用のフェーズ・ロックド・ループ及びその制御方法
WO2008078452A1 (ja) * 2006-12-26 2008-07-03 Nihon Dempa Kogyo Co., Ltd. 発振周波数制御回路
CN101490960B (zh) * 2006-12-26 2013-01-02 日本电波工业株式会社 振荡频率控制电路及其校正方法
WO2009081516A1 (ja) * 2007-12-25 2009-07-02 Nihon Dempa Kogyo Co., Ltd. 発振周波数制御回路
JP2009159013A (ja) * 2007-12-25 2009-07-16 Nippon Dempa Kogyo Co Ltd 発振周波数制御回路
JP4625494B2 (ja) * 2007-12-25 2011-02-02 日本電波工業株式会社 発振周波数制御回路
JP2010273299A (ja) * 2009-05-25 2010-12-02 Furuno Electric Co Ltd 基準周波数発生装置
WO2010137419A1 (ja) * 2009-05-25 2010-12-02 古野電気株式会社 基準周波数発生装置
CN102388536A (zh) * 2009-05-25 2012-03-21 古野电气株式会社 基准频率产生装置
JP2011024274A (ja) * 2010-11-05 2011-02-03 Nippon Dempa Kogyo Co Ltd 発振周波数制御回路
CN107005245A (zh) * 2014-12-08 2017-08-01 古野电气株式会社 基准信号产生装置
CN107005245B (zh) * 2014-12-08 2020-08-25 古野电气株式会社 基准信号产生装置

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