JPH04505841A - Frequency synthesizer with FM modulation - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

[Detailed description of the invention] Background of the invention of frequency synthesizer with FM modulation This is application number 7/32 filed on March 27, 1989 and now abandoned. This is a continuation-in-part application of No. 8,834.

The present invention relates generally to frequency synthesizers, and more particularly to frequency synthesizers. Related to Isa modulation.

A frequency synthesizer whose frequency division circuit is a phase-locked loop (PLL) used in circuits. Output frequency of voltage controlled oscillator (vCO) in PLL circuit (fO) is divided (56°) and applied to a phase detector. The phase detector is To control the output frequency of vCO, the phase of the divided output signal is determined from the reference oscillator. It operates to compare with the reference frequency (fr) of . The output frequency (fo) is fo= MXfr, where M is the degree to which the output frequency is divided before being compared with the reference frequency. is the frequency division ratio code to be determined. This relationship relates to the reference frequency of the reference oscillator. As is known, M can be generated by a signal processor.

One direction in the design of frequency synthesizers is the nature of PLL frequency synthesizers. The goal is to improve performance by expanding the loop bandwidth. wider loop zone A narrow loop band improves transient response and reduces noise better than a narrow loop band. but However, a wider loop bandwidth has a resulting lower division ratio (M). , requires a higher reference frequency. Lower division ratios result in traditional frequency modulation required in the phase modulator (which is typically coupled to the single power of the phase detector) for The required phase excursion (ph’ase excursion) is limited (i.e. radians (the linear operating range of the modulator). this The problem is accentuated by low frequency modulated signals that require even larger phase rotations. So Therefore, it is easy to modulate via a low frequency modulation signal in a PLL with a high reference frequency. There is a need to increase the maximum amount around the phase.

Summary of the invention comprising an FM modulator operative to vary the frequency division rate code as a function of the modulating signal; OBJECT OF THE INVENTION It is an object of the present invention to provide a frequency synthesizer.

In summary, according to the invention, the synthesizer generates the integrated signal and the first control signal. and an accumulator for integrating the modulated signal to provide the modulated signal. product The divided signal is the control signal for further integration to provide a second control signal. This is the result of differentiation. Processes first, second and third control signals and division ratio codes Then, the signal processor changes the frequency division rate code according to the modulation signal.

According to another aspect of the invention, a wireless The frequency synthesizer in the machine is a phase-locked loop containing a reference frequency signal source, The phase detector, voltage controlled oscillator, and divisor of the voltage controlled oscillator. operatively connected to either the output or the output of the signal source at a reference frequency. A programmable frequency divider is provided. The first to integrate the modulated signal An integrator provides an integrated signal and a first control signal. Similarly, the integrated confidence a second integrator coupled to the first integrator for integrating the second control signal; provide. A differentiator coupled to the second integrator to provide a third control signal Differentiating the second control signal. Finally, connect the first integrator, second integrator and differentiator. The integrated processor processes the first, second, and third control signals and the division ratio code. Understand.

A processor coupled to a programmable frequency divider is modulated to provide a divisor. Change the divider code depending on the signal, and thereby The frequency of the output signal is modulated by the modulation signal.

Brief description of the drawing FIG. 1 shows a preferred embodiment of a frequency synthesizer with FM modulation according to the present invention. It is a block diagram.

Figure 2 is a block diagram of the signal processor of the frequency synthesizer in Figure 1. .

Figures 3A to 31 show signal waveforms at various points of the signal processor in Figure 2. FIG.

FIG. 4 is a block diagram of another embodiment of the frequency synthesizer with FM modulation according to the present invention. This is a diagram.

Figure 5 is a block diagram of the signal processor of the frequency synthesizer in Figure 4. .

Description of the preferred embodiment Referring to FIG. 1, a frequency synthesizer 10 according to the present invention is connected to a reference oscillator 1. It will be understood that this includes 1. The output (f r) of the reference oscillator 11 is Output coupled to voltage controlled oscillator (VCO) 14 via low pass filter 13 is applied to the phase detector 12 having . A fixed reference divider (not shown here) Not referenced to the output frequency of the oscillator to provide a reference frequency (fr) Dividing by a divisor may be optionally performed. As a second input, VCO 14 is A modulating signal that directly modulates the vCO using known dual-port modulation techniques. Receive number 9.

The output (f　o) of VCO 14 (whether it is modulated or not) is Connected to the output port 15 of the frequency synthesizer 10 and the programmable splitter 16. Continued. The output of the frequency divider 16 transmits the frequency-divided signal (fd) to the phase detector 12 and the frequency-divided signal (fd). The information is provided to the GNAL processor 17. Signal processor 17 is programmable Provides the division ratio code of the frequency divider connected to frequency divider 16 and lowering from fo to fd do.

Two inputs are provided to signal processor 17. One input is the division ratio code and another input is for A/D converter 18. A/D conversion 18 has an input for the modulation signal and a sampling signal (F samples) 19. Therefore, a clock can be set. The signal processor 17 converts analog modulation into digital In order to change the division factor M according to the modulation signal 9, and the output of the A/D converter 18.

Referring to FIG. 2, the output of A/D converter 18 (A/D word) is 24, said first accumulator 24 having means for integrating the modulated signal. Equipped with.

The output of one of the first accumulators (contents) is connected to the input of the second accumulator 25; The second accumulator 25 comprises means for integrating the integrated signal. in this way The output of the accumulator then depends on the A/D word. Each of accumulators 24 and 25 preferably have the same capacity, however the two accumulators have the same resolution It is not necessary to have Resolution is the amount of carry that occurs. When the contents overflow, the accumulator increases to the smallest value before it approaches capacity. This is the step size. The positive and negative carry outputs of accumulator 24 are the first control signal. including. Similarly, the positive and negative outputs of accumulator 25 include a second control signal. Accumulator 2 The positive carry (P) output of 4 is output by a 6-3 binary encoder (binary encoder). order) 41's single power (A). Similarly, Motorola's 74LSO The negative carry output (N) has a sign after being inverted by a 4 (34) type inverting gate. is supplied to another input (B) of the device 41.

The positive carry output of the second accumulator 25 is the other input (C) of the binary encoder 41. and the (D) input of the flip-flop 42. flip flop 42 The Q-bar output is coupled to the input (D) of binary encoder 41. After reversing (36) The negative carry output of the accumulator 25 is connected to the input (E) of the binary encoder 41 and to another frame. It is coupled to the (D) input of flip-flop 38. Q bar of flip flop 38 The output is coupled to the final input (F) of binary encoder 41. Motorola 74LSO J type inverting gate (36) and 74LS74 type flip-flops (38 and 4 2) can be used as a means of differentiation. Flip-flop (38 and The delay and inversion operation of By decreasing (increasing) the division ratio code after adding (or decreasing) This produces a differential effect. This continuous approximation method uses the output power produced in the divider. The pulse is the instantaneous differential impulse created each time the integrator 25 overflows. simulate Thus two accumulators (2 4 and 25) is required to achieve linear modulation in digital techniques. Provides fine resolution.

The clock inputs of flip-flops 38 and 42 and accumulators 24 and 25 are is coupled to the output of a programmable frequency divider 16 (fd). These clocks instead. Since fd and fr are phase-locked, the clock signal is directly transmitted by the reference oscillator 11. may be provided. Also, even if the signals were not phase-locked, However, usually small changes between the signals will make either signal usable.

6-3 After being converted by the encoder 41, the ball output NO.

N1 and N2 are applied to adder 43 (as word B inputs). Frequency division The rate (M) (which is the word A input) subtracts the divisor of the programmable splitter 16. is added to word B to output.

The present invention will be described in detail with reference to FIGS. 3A to 31. The circuit is A/D conversion response to any waveform within the resolution of the device 18, but with a rectangular shape having amplitude A. The example of a wave modulated signal is considered. One representation of this waveform is shown in Figure 3A. 3rd A The waveform in the figure has a fundamental frequency of the waveform that is much lower than the unity gain frequency of the loop. It is assumed that the waveform is a periodic waveform.

Figure 3B shows how the output signal fO of the VCO is applied to produce the desired FM modulated signal. shows the phase adjustment required from the steady state. This waveform changes as shown in Figure 3A. It is noted that it is proportional to the integral of the waveform of the tonal signal. Steady state vCo output Phase adjustment for the force signal is important, but the reason for this is due to the large transient time and frequency division ratio. Apply or cause a phase adjustment to the loop by changing the This is because the present invention works depending on the following.

For each pulse of the fd multiplied signal, the first accumulator 24 receives the input from the A/D converter 18. is added to the value already stored inside the accumulator 24. Output of A/D converter 18 is proportional to the amplitude of the modulating signal and is the addition of the signal to itself at fixed intervals. Since the repetition of the calculation can be regarded as integration, the contents of the accumulator 24 are equal to the modulated signal. It can be treated as an integral. In the present invention, the accumulator 24 has a capacity of vCO output. The scale is changed to be equivalent to a change of 2π radians in phase from the steady state of the force signal fo. will be changed. In this way, the difference between the amplitude of the modulating signal and the frequency deviation of the FM modulated signal is A relationship is established.

A carry is generated each time accumulator 24 reaches its capacity. Carry is , increases the divisor of the programmable frequency divider 16 during one cycle of the frequency divider output fd. It has a soothing effect. Taking the modulation waveform shown in FIG. 3A as an example, the first accumulator 2 The change in frequency division ratio as a result of the activity of 4 is shown in FIG. 3C. The first accumulator 24 is Both positive and negative carry signals are generated, and the negative carry signal is sent to the inverting gate 34. is inverted, so the divisor is increased or decreased from its steady state value. It can be done.

FIG. 3D shows the phase adjustment to the loop due to the action of the first accumulator 24. the Although the waveform cannot be measured directly in a circuit, in signal flow notation it can be measured in a frequency divider. Before the input, but after the output branch of the signal fO, it is added as an input (15'). Dew. As Figure 3D shows, the first accumulator is connected to the signal at the input of the divider (15°). Causes large step changes in phase. Additional refinement of the signal can be done by the synthesizer output. Required to reduce distortion in power.

The second accumulator 25, along with flip-flops 38 and 42, M serves to reduce distortion on the modulated signal. The second accumulator input for each pulse of fd The force adds the contents of first accumulator 24 to the contents of accumulator 25 . Inside the accumulator 25 The volume can be thought of as the integral of the quantity in the contents of the accumulator 24. accumulation The capacity of reservoir 25 is typically the same as the capacity of accumulator 24. second accumulator 25 and Due to the action of the positive carry output of flip-flop 42, each This positive carry sets the division ratio code of loop divider 16 for one cycle of fd. Increase by one from the steady-state value of and decrease by one from the steady-state value in the next cycle. vinegar. Similarly, a negative carry causes a decrease in the divider code and the next cycle. causes an increase between files.

This action transfers the content in the second accumulator through the loop divider to the content in the first accumulator. is equivalent to the value in, but can be treated as being pulled out and added to the loop. Wear. The action caused by the carry of the second accumulator is always paired (decreasing the divisor Since the average of the divisor due to the action of the second accumulator 25 is There is no substantial change in value. However, the amount of phase adjustment applied to the loop is zero. Rather, it tracks the amount of phase adjustment required by the modulating signal.

In FIG. 3E, the effect of the second accumulator on the divisor of loop divider 16 is shown in FIG. The modulation waveform shown in the figure is shown as an example. In Figure 3F, the phase in the loop from the stable state is The effect of the divisor on the adjustment is shown. As shown in Figure 3D, the waveform in Figure 3F is divided It can be considered as the summed input at the device input (15').

In the present invention, the actions of two accumulators are combined, and the sum of those two actions is applied to the loop divider. The overall phase adjustment for the loop for this operation is An example of the modulation signal of FIG. 3A is illustrated in FIG. 3G. Loop low-pass function The remaining phase adjustment for the loop, measured in vCO, is due to the low distortion of the modulated signal. Modify the frequency divider to track the phase adjustment required to create the FM modulated signal. removes high-frequency disturbances in the waveform generated by

This is illustrated in Figure 3H for the modulation waveform of Figure 3A. ■CO output The deviation of the FM signal at is shown in FIG. 3I.

Referring to FIG. 4, another embodiment of the invention is shown. Line of the invention Loop divider 5 whose digital technique for shape modulation maintains the same division ratio code M 6 is applied to a reference programmable frequency divider 16'. this The reference programmable frequency divider 16' has a divisor Mref and has a reference frequency oscillation. 11 and a phase detector 12. Similar to the preferred embodiment of FIG. The signal processor 17 uses the reference The programmed frequency division ratio M r e f and the digitization of the A/D converter 18 process the modulated signal output.

Referring to FIG. 5, the signal processor block of the frequency synthesizer of FIG. A diagram is shown. Regarding the internal structure, the structure of the signal processor 17 shown in FIG. The configuration remains the same as the configuration in FIG. Inputs and outputs of signal processor 17 The only difference is the starting point and the ending point. Signal processor 17 is now programmed by the reference programmed division factor Mref, and A clock is given by the frequency fd. Output of signal processor 17 is a reference programmable frequency divider 16 according to the remainder of the invention already described. is applied next.

Although the invention is implemented using two accumulators, It was described as Add additional accumulators or other more complex Other configurations, such as using advanced algorithms, can be used to improve distortion reduction. I can do it.

FIG.4 international search report

Claims (22)

[Claims] 1. A frequency synthesizer for providing a modulated output signal, the frequency synthesizer comprising: means for generating a reference frequency signal, a voltage controlled oscillator; voltage to divide the frequency of the output signal from the voltage controlled oscillator by a certain divisor. programmable frequency divider means coupled to the output of the controlled oscillator; a first input coupled to said means for generating a reference frequency signal; a second input coupled to the output of the voltage-controlled oscillator; A phase-locked loop in which the frequency of the output signal is equal to the frequency of the reference frequency signal multiplied by the divisor. phase detector means having an output coupled to an input of the voltage controlled oscillator for producing a voltage controlled oscillator; a first control signal for integrating the modulated signal to provide an integrated signal and a first control signal; an integrating means for integrating said integrated signal to provide a second control signal; a second integrating means coupled to the first integrating means for providing a third control signal; differentiating means coupled to a second integrating means for differentiating said second control signal; and the first for processing the first, second, and third control signals and the division ratio code; processing means coupled to the integrating means, the second integrating means and the differentiating means, the processing means being coupled to the integrating means; Program to change the divider code in response to the modulation signal and provide said divisor. the output signal from the voltage controlled oscillator. processing means whose wave number is modulated by the modulation signal; A frequency synthesizer comprising: 2. Furthermore, the processing means encoding means having inputs for said first, second and third control signals; an adder coupled to said encoding means and having an input for said dividing factor code; means, and said processing means coupled to said first integrating means for digitizing an input modulated signal; an analog-to-digital means for changing said divider code in response to said input modulating signal; Tal conversion means, A frequency synthesizer according to claim 1, comprising: 3. As claimed in claim 1, wherein said means for integrating comprises accumulator means. frequency synthesizer. 4. 2. A method according to claim 1, wherein said means for integrating comprises addition means. frequency synthesizer. 5. Each of the first, second and third control signals comprises a first output and a second output. A frequency synthesizer according to claim 1, wherein the frequency synthesizer is made of: 6. The first integrating means is a first carrier for providing a first control signal to change the division ratio code; a carry output and a second carry output, wherein the first integrating means receives a first control signal. accumulating the modulated signal into its contents to provide a first accumulated sum to generate a a first carry output and a second carry output operable to add productively; , and a third output for providing the integrable signal to a second integrating means. A frequency synthesizer according to claim 1, comprising: 7. The second integrating means is an input connected to a third output of said second integrating means; and a first carrier for providing a second control signal to change the division ratio code; a carry output and a second carry output, the second integrating means generating a second control signal. accumulating the integrand signal into its contents to provide a second accumulated sum to generate a first carry output and a second carry output operable to apply a The frequency synthesizer according to claim 6, comprising: 8. The differentiating means is configured to provide a first inverted output of the third control signal. a first delaying and inverting means coupled to the first carry output of the second control signal; a second capacitor of the second control signal to provide a second inverted output of the third control signal; Claim 7 further comprising a second delaying and inverting means coupled to the output of the claim 7. Frequency synthesizer described. 9. The claimed first delaying and inverting means comprises a first flip-flop. A frequency synthesizer according to range 8. 10. The second delaying and inverting means provides a second carry output of the second control signal. a second frame for providing a second inverted output of the third control signal; as claimed in claim 9, comprising an inverting gate coupled to a flip-flop. frequency synthesizer. 11. The first carry output of the control signal is such that the first cumulative sum is at least predetermined. claim 1, which increases the divider code when the determined positive threshold is reached. The frequency synthesizer according to item 6. 12. when the first cumulative sum reaches at least a predetermined negative threshold; A second carry output of the first control signal decreases the division ratio code. The frequency synthesizer according to item 6 of the desired range. 13. when the second cumulative sum reaches at least a predetermined positive threshold; a first carry output of the second control signal and a first inverted output of the third control signal; 8. The frequency according to claim 8, wherein the frequency division factor code is increased and then decreased. Number synthesizer. 14. A first carry output of said second control signal in turn reduces said frequency divider code. a circuit according to claim 8, which is coupled to the first delay and reversal means for Wavenumber synthesizer. 15. When the second cumulative sum reaches at least a predetermined negative threshold, the second cumulative sum reaches at least a predetermined negative threshold. The second carry output of the second control signal and the second inverted output of the third control signal are A frequency synthesizer according to claim 8, wherein the frequency division code is reduced and then increased. Cyza. 16. A second carry output of the second control signal increases the division ratio code to the next value. The circuit according to claim 8 is coupled to the second delaying and reversing means for facilitating Wavenumber synthesizer. 17. The first and second integrating means and the first and second flip-flops are The frequency according to claim 10, which is clocked by the reference frequency. synthesizer. 18. A method of modulating a synthesizer, the method comprising: generating a reference frequency signal; Generates an output frequency signal from a voltage controlled oscillator and programs the frequency of the output frequency signal. Divide the frequency by a divisor using a gram-capable frequency dividing means, divided by said reference frequency in phase detector means to generate a phase control signal. the output frequency signals are compared, and the output frequency signal is a divisor times the reference frequency signal. controlling the voltage controlled oscillator with the phase control signal to be equal to integrating the modulated signal with a first integrating means to provide an integrated signal and a first control signal; divided, a second integrating means for providing a second control signal; integrating said second integrated signal with differentiating means to provide a third control signal; differentiating said second control signal from the integrating means and said first, second and third control signals; The control signal and the frequency division ratio code are transmitted to the first integrating means, the second integrating means, and the differentiating means. processing means coupled to the modulation signal; coupled to a programmable divider means for changing the code and providing said divisor. , whereby the frequency of the output signal from the voltage controlled oscillator is changed by the modulating signal. to be modulated, A method of modulating a synthesizer, comprising stages. 19. A frequency synthesizer in a radio for providing a modulated output signal. So, voltage controlled oscillator, Means for generating a reference frequency signal, the frequency of the output signal from a voltage controlled oscillator A program coupled to the output of the voltage controlled oscillator to divide the frequency by some divisor. frequency dividing means, a first input coupled to said means for generating a reference frequency signal; a second input coupled to the output of the rammable divider means, and from the voltage controlled oscillator; Phase-locked where the frequency of the output signal is equal to the frequency of the reference frequency signal multiplied by the said divisor. A phase detector with an output coupled to the input of a voltage controlled oscillator to generate a loop. output means for receiving a modulated signal and converting said modulated signal into a digital signal; a signal converting means for adjusting the modulated signal; A cascade connection for processing said digital signal to introduce it into a phase-locked loop. a plurality of integrating means converted by said signal converting means and providing said divisor; dividing the frequency in response to said digital signal processed by a plurality of integrating means to change the rate code, thereby changing the frequency of the output signal from the voltage controlled oscillator. said programmable frequency dividing means to be modulated by said signal; divisor means coupled to the plurality of cascaded integration means; A frequency synthesizer in a radio device, comprising: 20. Frequency synthesizer in radio to provide modulated output signal And, Means for generating a reference frequency signal, a phase detector, a voltage controlled oscillator, and a divisor said voltage controlled oscillator and one of said means for generating a reference frequency signal; including programmable divider means operably connected to apply to the output of the phase-locked loop, a first for integrating the modulated signal to provide an integratable signal and a first control signal; the integral means of, a first integrator to integrate said integrable signal to provide a second control signal; a second integrator means coupled to the stage, a second control signal for providing a third control signal; differentiating means coupled to the second integrating means for differentiating the the first, second and third control signals coupled to the dividing means, the second integrating means and the differentiating means; processing means for processing the modulation signal and the frequency division rate code, the processing means for processing the modulation code; The program changes the divider code in response to the signal and provides the divisor in parentheses. the output signal from the voltage controlled oscillator. processing means for modulating the frequency of the signal by the modulation signal. frequency synthesizer. 21. Said programmable frequency dividing means comprises said programmable frequency dividing means for generating a reference frequency signal. and the phase detector for dividing the frequency of the reference frequency by the divisor. wherein the reference frequency signal is modulated by the modulating signal. A frequency synthesizer according to paragraph 20. 22. The programmable frequency dividing means divides the frequency of the output signal from the voltage controlled oscillator. is inserted between the voltage controlled oscillator and the phase detector in order to divide the number by the divisor. 21. The frequency synthesizer according to claim 20, wherein the frequency synthesizer includes: