JPH045028Y2 - - Google Patents
Info
- Publication number
- JPH045028Y2 JPH045028Y2 JP1986001472U JP147286U JPH045028Y2 JP H045028 Y2 JPH045028 Y2 JP H045028Y2 JP 1986001472 U JP1986001472 U JP 1986001472U JP 147286 U JP147286 U JP 147286U JP H045028 Y2 JPH045028 Y2 JP H045028Y2
- Authority
- JP
- Japan
- Prior art keywords
- fet
- channel power
- terminal
- power mos
- printed wiring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000007689 inspection Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 238000009413 insulation Methods 0.000 description 3
- 238000012360 testing method Methods 0.000 description 3
- 235000014676 Phragmites communis Nutrition 0.000 description 2
- 238000004519 manufacturing process Methods 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 239000000523 sample Substances 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000002195 synergetic effect Effects 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Description
【考案の詳細な説明】
（産業上の利用分野）
この考案はプリント配線板上の回路パターンの
電気的な導通特性及び絶縁特性の検査に使用され
るプリント配線板の検査用ブリツジに関するもの
である。[Detailed description of the invention] (Industrial application field) This invention relates to a printed wiring board inspection bridge used for testing the electrical continuity and insulation properties of circuit patterns on printed wiring boards. .
（従来の技術）
電子機器等に内蔵されるプリント配線板はその
機能の信頼性を保証するため、この配線板上に部
品を実装する前の時点でチエツクが必要である。
即ち、そのプリント配線板上の部品間・端子間の
各回路・配線パターンについてそれぞれ電気的な
導通特性チエツク及び絶縁特性チエツクがそれぞ
れ個別に実施されるのであるが、この様なチエツ
ク乃至検査は従来、被検査部位を切り替えるため
の接点としてリードリレーを用いたチエツク装置
で実施されていた。多数のリードリレーを用い
る、この様なチエツク装置ではプリント配線板上
の配線１本当たりのチエツク時間は10msec程度
を必要としている。(Prior Art) In order to guarantee the reliability of a printed wiring board built into an electronic device or the like, it is necessary to check the printed wiring board before mounting components on the wiring board.
That is, each circuit and wiring pattern between components and terminals on the printed wiring board is individually checked for electrical continuity characteristics and insulation characteristics. The test was carried out using a check device that used a reed relay as a contact point to switch the part to be inspected. Such a check device using a large number of reed relays requires a check time of about 10 msec for each wire on a printed wiring board.
従つて、例えば、寸法300mm×300mmの４層プリ
ント配線板では、その１枚当たりの配線本数は
1000〜2000本となり、そのプリント配線板１枚の
総チエツク時間は10〜20秒程度となる。 Therefore, for example, in a 4-layer printed wiring board with dimensions of 300 mm x 300 mm, the number of wires per board is
There will be 1000 to 2000 lines, and the total check time for one printed wiring board will be about 10 to 20 seconds.
しかして、上記の如き、プリント配線板の部品
実装密度は、上記にとどまるものではなく、更に
著しく高密度になつてきている。特に、中、大型
コンピュータ等に使用されるプリント配線板で
は、前記の４層を超えて６層、８層（更には12
層）となり、又こうなる趨勢になつている。そし
てその配線パターン密度はこのプリント配線板上
に実装される部品の集積化・小型化の相乗効果
で、前記の４層の場合の５〜６倍になつているの
が実状である。従つて、この様に多層度・パター
ン密度が高くなるにつれ、製造ラインに比して、
より多くの検査部門における作業の遅延が生じ
て、全生産ラインが円滑に進行せず、故に現状よ
り高速のチエツク手段の出現が要請されていた。 However, the component mounting density of printed wiring boards as described above is not limited to the above, but is becoming even more dense. In particular, for printed wiring boards used in medium and large computers, etc., the number of layers exceeds the four layers mentioned above to six, eight (and even 12 layers).
layer), and this is the trend. In reality, the wiring pattern density is five to six times that of the four-layer case described above, due to the synergistic effects of the integration and miniaturization of components mounted on the printed wiring board. Therefore, as the degree of multilayering and pattern density increases, compared to the production line,
Delays in work in more inspection departments occur, preventing the entire production line from proceeding smoothly.Therefore, there is a need for a faster checking method than the current one.
（考案が解決しようとする問題点）
この考案は上記に鑑み、プリント配線板、特に
多層かつ高パターン密度のプリント配線板を高速
で、前記の導通及び絶縁チエツクを実施するプリ
ント配線板の検査用ブリツジを提供するものであ
る。(Problems to be solved by the invention) In view of the above, this invention is designed for testing printed wiring boards, especially printed wiring boards with multilayers and high pattern densities, for performing the aforementioned continuity and insulation checks at high speed. It provides bridges.
（問題点を解決するための手段）
この考案を一実施例を示す図に基づいて説明す
れば以下の通りである。即ち、この考案のプリン
ト配線板の検査用ブリツジは、第１図において、
第１のｐチヤンネルパワー（power）MOS
（metal oxide semiconductor）−FET（field
effect transistor）１のソース（source）端子２
及び第２のｐチヤンネルパワーMOS−FET６の
ソース端子７のそれぞれを電源の一方の電極の端
子５と接続し、前記第１のｐチヤンネルパワー
MOS−FET１のドレイン（drain）端子３の第３
のｐチヤンネルパワーMOS−FET１０のソース
端子１１と接続し、前記第２のｐチヤンネルパワ
ーMOS−FET６のドレイン端子８を第４のｐチ
ヤンネルパワーMOS−FET１４のソース端子１
５に接続し、前記第３のｐチヤンネルパワー
MOS−FET１０のドレイン端子１２及び第４の
ｐチヤンネルパワーMOS−FET１４のドレイン
端子１６を前記電源の他方の電極の端子１８と接
続し、そして前記第１のｐチヤンネルパワー
MOS−FET１のドレイン端子３（又は第３のｐ
チヤンネルパワーMOS−FET１０のソース端子
１１）を一方の出力端子２０とし、第２のｐチヤ
ンネルパワーMOS−FET６のドレイン端子８
（又は第４のｐチヤンネルパワーMOS−FET１
４のソース端子１５）を他方の出力端子１９と
し、そして前記各ｐチヤンネルパワーMOS−
FETの各ゲート端子をその電流導通のコントロ
ール端子としたことを特徴としている。(Means for Solving the Problems) This invention will be explained as follows based on the drawings showing one embodiment. That is, the bridge for inspecting printed wiring boards of this invention is shown in FIG.
First p-channel power MOS
(metal oxide semiconductor) − FET (field
source terminal 2 of effect transistor) 1
and the source terminal 7 of the second p-channel power MOS-FET 6 are connected to the terminal 5 of one electrode of the power supply, and the first p-channel power
3rd terminal of drain terminal 3 of MOS-FET1
The drain terminal 8 of the second p-channel power MOS-FET 6 is connected to the source terminal 11 of the fourth p-channel power MOS-FET 14.
5 and the third p-channel power
The drain terminal 12 of the MOS-FET 10 and the drain terminal 16 of the fourth p-channel power MOS-FET 14 are connected to the terminal 18 of the other electrode of the power supply, and the first p-channel power
Drain terminal 3 of MOS-FET1 (or third p
The source terminal 11) of the channel power MOS-FET 10 is used as one output terminal 20, and the drain terminal 8 of the second p-channel power MOS-FET 6
(or 4th p-channel power MOS-FET1
4 as the source terminal 15) of the other output terminal 19, and each of the p-channel power MOS-
The feature is that each gate terminal of the FET is used as a control terminal for current conduction.
第１図に示す実施例は上記したようにパワー
MOS−FETとしてｐチヤンネルのそれを使用し
ており、この場合、上記の電源の一方の電極の端
子５は＋（プラス）極に接続し、電極の他方の端
子１８は−（マイナス）極に接続する。 The embodiment shown in FIG.
A p-channel MOS-FET is used. In this case, terminal 5 of one electrode of the above power supply is connected to the + (plus) pole, and terminal 18 of the other electrode is connected to the - (minus) pole. Connecting.
（作用）
次に本考案のプリント配線板の検査用ブリツジ
の作用を説明すると、第１図において、第１のｐ
チヤンネルパワーMOS−FET１のゲート端子４
及び第４のｐチヤンネルパワーMOS−FET１４
のゲート端子１７の電圧をそれぞれ、例えば
Lowにして各ゲートをONにし、第２のｐチヤン
ネルパワーMOS−FET６のゲート端子及び第３
のｐチヤンネルパワーMOS−FET１０のゲート
端子１３のいずれもがHigh電圧の状態にしてそ
の各ゲートOFFにすると、一方の出力１９及び
他方の出力端子２０にプローブ等を介してこの回
路に接続されたプリント配線板２１上の回路のあ
る配線２２には一方の出力端子２０から他方の出
力端子１９へと電流がながれる。(Function) Next, to explain the function of the inspection bridge for printed wiring boards of the present invention, in FIG.
Channel power MOS-FET1 gate terminal 4
and fourth p-channel power MOS-FET14
For example, the voltage at the gate terminal 17 of
Turn on each gate by setting it to Low, and connect the gate terminal of the second p-channel power MOS-FET6 and the third
When all of the gate terminals 13 of the p-channel power MOS-FET 10 are in a high voltage state and each gate is turned off, one output 19 and the other output terminal 20 are connected to this circuit via a probe etc. A current flows from one output terminal 20 to the other output terminal 19 in a wiring 22 on a printed wiring board 21 with a circuit.
つぎに、上記と逆の操作を実施して、すなわち
第２のｐチヤンネルパワーMOS−FET６のゲー
ト端子９及び第３のｐチヤンネルパワーMOS−
FET１０のゲート端子１３をLowの電圧にして
その各ゲートをONにし、一方第１のｐチヤンネ
ルパワーMOS−FET１のゲート端子４及び第４
のｐチヤンネルパワーMOS−FET１４のゲート
端子１７の電圧をHighにした場合は前記のプリ
ント配線板２１上の回路の或る配線２２には他方
の出力端子１９から一方の出力端子２０に電流が
流れる。 Next, the operation opposite to the above is performed, that is, the gate terminal 9 of the second p-channel power MOS-FET 6 and the third p-channel power MOS-FET 6 are connected to each other.
The gate terminal 13 of the FET 10 is set to a low voltage to turn on each gate, while the gate terminal 4 of the first p-channel power MOS-FET 1 and the fourth
When the voltage of the gate terminal 17 of the p-channel power MOS-FET 14 is set to High, a current flows from the other output terminal 19 to one output terminal 20 in a certain wiring 22 of the circuit on the printed wiring board 21. .
（考案の効果）
この考案は上述したように、ｐチヤンネルパワ
ーMOS−FETを用いたものであるから、高速か
つ廉価でスイツチング動作をすることができる。
すなわち、配線チエツク時間は配線１本当たり
100μsec以下であり、前記した従来のそれと比較
してその1/100の所要時間で検査をすることが出
来る。(Effects of the invention) As described above, this invention uses a p-channel power MOS-FET, so it can perform switching operations at high speed and at low cost.
In other words, the wiring check time is per wiring.
It takes less than 100 μsec, and can perform an inspection in 1/100 of the time required for the conventional method described above.
また、これらｐチヤンネルパワーMOS−FET
の複数を特定のブリツジ状に接続して、上記のｐ
チヤンネルパワーMOS−FETの導通をそのゲー
ト端子で制御するものであるから、被検査体であ
るプリント配線板上の回路・配線に両方向から電
流を流すことができる等々の顕著な効果がある。 In addition, these p-channel power MOS-FET
The above p is connected in a specific bridge shape.
Since the conduction of the channel power MOS-FET is controlled by its gate terminal, it has remarkable effects such as allowing current to flow from both directions to the circuits and wiring on the printed wiring board that is the object to be inspected.
第１図はこの考案のプリント配線板の検査用ブ
リツジの１実施例の回路図である。
図中、１……第１のｐチヤンネルパワーMOS
−FET、５……電源の＋極の端子、６……第２
のｐチヤンネルパワーMOS−FET、１０……第
３のｐチヤンネルパワーMOS−FET、１４……
第４のｐチヤンネルパワーMOS−FET、１８…
…電源の−極の端子、２０……一方の出力端子、
１９……他方の出力端子。
FIG. 1 is a circuit diagram of one embodiment of the bridge for inspecting printed wiring boards of this invention. In the figure, 1...first p-channel power MOS
-FET, 5...+ terminal of power supply, 6...2nd
p-channel power MOS-FET, 10...Third p-channel power MOS-FET, 14...
Fourth p-channel power MOS-FET, 18...
...the negative terminal of the power supply, 20...one output terminal,
19...The other output terminal.
Claims (1)
ス端子及び第２のｐチヤンネルパワーMOS−
FETのソース端子のそれぞれを電源の一方の電
極の端子と接続し、前記第１のｐチヤンネルパワ
ーMOS−FETのドレイン端子を第３のｐチヤン
ネルパワーMOS−FETのソース端子と接続し、
前記第２のｐチヤンネルパワーMOS−FETのド
レイン端子を第４のｐチヤンネルパワーMOS−
FETのソース端子に接続し、前記第３のｐチヤ
ンネルパワーMOS−FETのドレイン端子及び第
４のｐチヤンネルパワーMOS−FETのドレイン
端子を前記電源の他方の電極の端子と接続し、そ
して前記第１のｐチヤンネルパワーMOS−FET
のドレイン端子を一方の出力端子とし、第２のｐ
チヤンネルパワーMOS−FETのドレイン端子を
他方の出力端子とし、そして前記各ｐチヤンネル
パワーMOS−FETの各ゲート端子をその電流導
通のコントロール端子としたことを特徴とするプ
リント配線板の検査用ブリツジ。 The source terminal of the first p-channel power MOS-FET and the second p-channel power MOS-FET
each of the source terminals of the FETs is connected to a terminal of one electrode of a power supply, and the drain terminal of the first p-channel power MOS-FET is connected to the source terminal of a third p-channel power MOS-FET;
The drain terminal of the second p-channel power MOS-FET is connected to the fourth p-channel power MOS-FET.
FET, the drain terminal of the third p-channel power MOS-FET and the drain terminal of the fourth p-channel power MOS-FET are connected to the terminal of the other electrode of the power supply. 1 p-channel power MOS-FET
The drain terminal of p is one output terminal, and the second p
1. A bridge for inspecting a printed wiring board, characterized in that the drain terminal of a channel power MOS-FET is used as the other output terminal, and each gate terminal of each of the p-channel power MOS-FETs is used as a control terminal for current conduction.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986001472U JPH045028Y2 (en) | 1986-01-09 | 1986-01-09 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP1986001472U JPH045028Y2 (en) | 1986-01-09 | 1986-01-09 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS62114374U JPS62114374U (en) | 1987-07-21 |
| JPH045028Y2 true JPH045028Y2 (en) | 1992-02-13 |
Family
ID=30779413
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP1986001472U Expired JPH045028Y2 (en) | 1986-01-09 | 1986-01-09 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH045028Y2 (en) |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS5245214Y2 (en) * | 1972-10-20 | 1977-10-14 |
-
1986
- 1986-01-09 JP JP1986001472U patent/JPH045028Y2/ja not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| JPS62114374U (en) | 1987-07-21 |
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