JPH04115173A - Method and apparatus for testing connection state of electronic part - Google Patents
Method and apparatus for testing connection state of electronic partInfo
- Publication number
- JPH04115173A JPH04115173A JP2233411A JP23341190A JPH04115173A JP H04115173 A JPH04115173 A JP H04115173A JP 2233411 A JP2233411 A JP 2233411A JP 23341190 A JP23341190 A JP 23341190A JP H04115173 A JPH04115173 A JP H04115173A
- Authority
- JP
- Japan
- Prior art keywords
- voltage
- current
- section
- test
- measuring
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000012360 testing method Methods 0.000 title claims abstract description 42
- 238000000034 method Methods 0.000 title claims abstract description 7
- 238000005259 measurement Methods 0.000 claims abstract description 28
- 239000000523 sample Substances 0.000 claims description 6
- 238000010998 test method Methods 0.000 claims description 6
- 239000000758 substrate Substances 0.000 abstract 1
- 238000010586 diagram Methods 0.000 description 6
- 238000001514 detection method Methods 0.000 description 2
- 230000006866 deterioration Effects 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 238000005476 soldering Methods 0.000 description 1
Landscapes
- Testing Of Short-Circuits, Discontinuities, Leakage, Or Incorrect Line Connections (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野〕
本発明は電子部品の搭載された実装基板上の電子部品の
接続状態の試験方法およびこの試験方法を実施する装置
に関するものである。DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a method for testing the connection state of electronic components on a mounting board on which electronic components are mounted, and an apparatus for implementing this testing method.
従来、この種の試験方法は実装基板を動作状態にし、試
験パターンを印加し、実装基板からの出カバターンと期
待値パターンとを比較し、実装基板に搭載した電子部品
の接続状態、例えば半田付部分や基板パターンのオープ
ン状態や、ショート状態を試験してい次。また、接続状
態を目視で試験していた。Conventionally, this type of test method puts the mounted board in operation state, applies a test pattern, compares the output pattern from the mounted board with the expected value pattern, and evaluates the connection status of electronic components mounted on the mounted board, such as soldering. Next, we test the open and shorted states of parts and board patterns. The connection status was also visually tested.
上述した従来の試験方法では、試験パターンの検出力に
よって、接続部分を試験するため、電子部品そのものの
集積度の向上や、実装基板の集積度の向上によシ、試験
バター7の検出力の低下が、接続部分の試験を困難にし
ているという課題があった。また、実装基板の集積度の
向上や、表面実装技術の出・現によシ、接続部分が目視
で見ることが不可能な構造となっているため、目視で接
続状態の試験ができないという課題があった。In the conventional test method described above, the detection power of the test pattern 7 is used to test the connection part using the detection power of the test pattern. There was a problem in that the deterioration made it difficult to test the connection parts. In addition, with the increase in the degree of integration of mounting boards and the emergence of surface mounting technology, the problem of not being able to visually test the connection status has arisen due to the structure in which it is impossible to visually see the connection parts. there were.
本発明の電子部品の接続状態の試験方法は、印加電圧と
印加時間を設定できる電圧設定部と、この電圧設定部で
指定された電圧を発生する電圧発生部と、上記印加電圧
の極性を切換える極性切換部と、被試験物に流れた電流
を測定する電流測定部を有し、上記被試験物に異なる電
圧を短時間印加し、それぞれの電流値を測定することに
ょシミ子部品を破壊することなく試験を行うようにした
本のである。The method for testing the connection state of electronic components according to the present invention includes a voltage setting section that can set the applied voltage and application time, a voltage generating section that generates the voltage specified by this voltage setting section, and switching the polarity of the applied voltage. It has a polarity switching section and a current measurement section that measures the current flowing through the test object, and destroys the shimiko parts by applying different voltages to the test object for a short time and measuring the respective current values. This is a book that allows you to take the exam without having to worry about it.
また、本発明の別の発BAKよる電子部品の接続状態の
試験装置は、上記の試験方法を用いた電圧印加測定部と
、被試験物の測定箇所に直接接触するグローブ付き2ス
テージと、上記被試験物を移動するX−Yテーブルと、
これら電圧印加測定部とグローブ付き2ステージおよび
X−Yテーブルを制御する制御部を備えてなるものであ
る。In addition, another test device of the present invention for testing the connection state of electronic components using the BAK is provided with a voltage application measuring section using the above test method, two stages with gloves that directly contact the measurement point of the test object, and the above-described an X-Y table for moving the test object;
The apparatus is equipped with a control section that controls these voltage application and measurement sections, two stages with gloves, and an XY table.
本発明においては、実装基板の電子部品に異なる電圧全
短時間印加し、それぞれの電流値を測定する。In the present invention, different voltages are applied to electronic components on a mounting board for a full time period, and the respective current values are measured.
以下、図面に基づき本発明の実施例を詳mK説明する。 Embodiments of the present invention will be described in detail below based on the drawings.
第1図は本発明による電子部品の接続状態の試験方法の
一実施例を説明する九めのブロック図であり。FIG. 1 is a ninth block diagram illustrating an embodiment of the method for testing the connection state of electronic components according to the present invention.
この第1図において、1は印加電圧と印加時間を設定で
きる電圧設定部、2はこの電圧設定部1で指定された電
圧を発生する電圧発生部、3は印加電圧の極性を切換え
る極性切換部、4は被試験物に流れた電流を測定する電
流測定部、5および6は被試験物に接続する測定端子で
ある。In FIG. 1, 1 is a voltage setting section that can set the applied voltage and application time, 2 is a voltage generation section that generates the voltage specified by this voltage setting section 1, and 3 is a polarity switching section that switches the polarity of the applied voltage. , 4 is a current measuring section that measures the current flowing through the test object, and 5 and 6 are measurement terminals connected to the test object.
そして、被試験物に異なる電圧を短時間印加し、それぞ
れの電流値を測定することにより電子部品を破壊するこ
となく試験を行うように構成されている。The device is configured to apply different voltages to the test object for a short period of time and measure the respective current values to perform the test without destroying the electronic components.
第2図および第3図は本発明の説明に供する被試験物の
構成例を示す回路構成図である。FIGS. 2 and 3 are circuit configuration diagrams showing an example of the configuration of a test object for explaining the present invention.
この第2図および第3図において第1図と同一符号のも
のは相当部分を示し、第2図における7゜8はECLの
オアゲート、9は接続パターンで、これらは電子回路を
構成し、この接続パターン9は抵抗R1を持ち、ECL
のオアゲートT、8と接続パターン9は第3図に示す等
価回路14で表わされる。15はGNDである。In FIGS. 2 and 3, the same reference numerals as in FIG. 1 indicate corresponding parts. In FIG. Connection pattern 9 has a resistor R1, and ECL
The OR gate T, 8 and the connection pattern 9 are represented by an equivalent circuit 14 shown in FIG. 15 is GND.
この第3図に示す等価回路14は、オアゲート1のNP
N )ランジスタ12CTz)と抵抗10(R+)およ
びオアゲート8のNPN )ランジスタ13(T+)と
抵抗l 1 (R2)とその他の回路から構成される。The equivalent circuit 14 shown in FIG.
NPN) transistor 12CTz), resistor 10 (R+), and OR gate 8 NPN) transistor 13 (T+), resistor l1 (R2), and other circuits.
つぎに第1図に示す実施例の動作を第2図および第3図
を参照して説明する。Next, the operation of the embodiment shown in FIG. 1 will be explained with reference to FIGS. 2 and 3.
まず、測定端子5をオアゲート8の入力部に接続し、測
定端子6をGND 15に接続し、電圧設定部1よシミ
圧0.3V、印加時間1秒を指定し、電圧発生部2より
1秒間0,3■の電圧を発生する。極性切換部3は測定
端子5に+(プラス)電位、測定端子6に−(マイナス
)電位をそれぞれ設定する。First, connect the measurement terminal 5 to the input part of the OR gate 8, connect the measurement terminal 6 to the GND 15, specify the stain pressure of 0.3V and the application time of 1 second from the voltage setting part 1, and set the voltage of 1 second from the voltage generation part 2. Generates a voltage of 0.3 cm per second. The polarity switching section 3 sets the measurement terminal 5 to a + (plus) potential and the measurement terminal 6 to a - (minus) potential.
そして、電圧が印加されると電流は測定端子5から接続
パターン9を通り抵抗10(T1)を通って測定端子6
へ流れる。ここで、印加電圧が0゜3vと低いため、N
PN )ランジスタ13(T+)の方へは電流I′i流
れない。測定端子6に流れた電流は電流測定部4で測定
され、0.3/(H,+Rz)Aの電fItが流れてい
ればオアゲー)7の出力ライ/の接続状態を確認するこ
とができる。When a voltage is applied, the current flows from the measurement terminal 5 through the connection pattern 9 and through the resistance 10 (T1) to the measurement terminal 6.
flows to Here, since the applied voltage is as low as 0°3V, N
PN) Current I'i does not flow toward transistor 13 (T+). The current flowing through the measurement terminal 6 is measured by the current measurement unit 4, and if a current of 0.3/(H, +Rz)A is flowing, it is possible to check the connection state of the output wire/of OR game) 7. .
つぎに、同様に印加電圧2.OV、印加時間1秒を設定
し測定すると、電流は同様に2/ (Rt + R1)
Aオアゲート1に流れるが、印加電圧が高いため、NP
Nトランジスタ13(T+)のPN接合が導通状態とな
る。そして、このNPN )う/ラスタ13(T+)の
導通によシ、オアゲート8内のNPN )ランジスタ1
3(T1)を通シさらに抵抗11 (R2)を通って電
流2/R,Aが流れるため、電流測定部4で(2/(R
t+R,)+2/Rz) Aの電流が測定できれはオア
ゲート8の入力ラインの接続状態を確認することができ
る。Next, apply voltage 2. When measuring by setting OV and application time for 1 second, the current is similarly 2/ (Rt + R1)
A flows to OR gate 1, but because the applied voltage is high, NP
The PN junction of the N transistor 13 (T+) becomes conductive. Then, due to the conduction of this NPN transistor 13 (T+), the NPN transistor 1 in the OR gate 8
3 (T1), and further through the resistor 11 (R2), the current 2/R, A flows in the current measuring section 4 (2/(R
If the current of t+R, )+2/Rz) A can be measured, the connection state of the input line of the OR gate 8 can be confirmed.
第4図は本発明による電子部品の接続状態の試験装置の
実施例を示すブロック図である。FIG. 4 is a block diagram showing an embodiment of a test device for testing the connection state of electronic components according to the present invention.
この第4図において、16は被試験物、17は第1図に
示す試験方法を用いた電圧印加測定部、18は被試験物
16の測定箇所に亘接接触するプローブ付きZステージ
、19は被試験物16を移動するX−Yテーブル、20
ばこれら電圧印加測定部11とプローブ付き2ステージ
18およびX−Yテーブル19を制御する制御部である
。そして、電圧印加測定部17の一方の端子は、被試験
物16のGND部21に接続されている。In this FIG. 4, 16 is a test object, 17 is a voltage application measurement unit using the test method shown in FIG. X-Y table 20 for moving the test object 16
For example, it is a control section that controls the voltage application and measurement section 11, the two stages 18 with probes, and the XY table 19. One terminal of the voltage application and measurement section 17 is connected to the GND section 21 of the test object 16.
つぎにこの第4図に示す実施例の動作を説明する。Next, the operation of the embodiment shown in FIG. 4 will be explained.
まず、制御部20の指示にしたがいX−Yテーブル19
は被試験物16内の測定箇所に移動させる。First, according to the instructions from the control section 20, the X-Y table 19
is moved to the measurement location within the test object 16.
つぎに、グローブ付き2ステージ18を動かし、測定箇
所にプローブを接続する。制@部20は電圧印加測定部
1Tに前述の試験方法で電圧を印加して電流を測定し、
良否判断を実施する。そして、測定が完了すると制御部
20は次の測定箇所を試験するため、グローブ付き2ス
テージ18のプローブを測定箇所よシ離し、X−Yテー
ブル19を移動させ、上記動作を繰シ返す。Next, the two stages 18 with gloves are moved and the probe is connected to the measurement location. The control unit 20 applies a voltage to the voltage application and measurement unit 1T according to the above-described test method and measures the current,
Perform pass/fail judgment. When the measurement is completed, the control section 20 separates the probe of the two-stage gloved stage 18 from the measurement point, moves the XY table 19, and repeats the above operation in order to test the next measurement point.
以上説明したように本発明は、実装基板の電子部品に異
なる電圧を短時間印加し、それぞれの電流値を測定する
ことにより、目視不可能な電子部品の接続部を電子部品
を破壊することなく試験することができる効果がある。As explained above, the present invention applies different voltages to electronic components on a mounting board for a short time and measures the respective current values, thereby connecting the electronic components that are invisible to the naked eye without destroying the electronic components. There are effects that can be tested.
第1図は本発明による電子部品の接続状態の試験方法の
一実施例を説明するためのブロック図、第2図、第3図
は本発明の説明に供する被試験物の構成例を示す回路構
成図、第4図は本発明による電子部品の接続状態の試験
装置の実施例を示すブロック図である。
1・・・・電圧設定部、2・・・・電圧発生部、3・・
・・極性切換部、4・・・・電流測定部、5.6・・・
・測定端子、16・・・・被試験物、17・・・・電圧
印加測定部、18・・・・プローブ付きzステージ、1
9・曇011X−Yテーブル、20・・・・制御部。
第1図FIG. 1 is a block diagram for explaining an embodiment of the method for testing the connection state of electronic components according to the present invention, and FIGS. 2 and 3 are circuit diagrams showing an example of the configuration of a test object used for explaining the present invention. FIG. 4 is a block diagram showing an embodiment of a test device for testing the connection state of electronic components according to the present invention. 1... Voltage setting section, 2... Voltage generating section, 3...
...Polarity switching section, 4...Current measurement section, 5.6...
・Measurement terminal, 16... Test object, 17... Voltage application measurement section, 18... Z stage with probe, 1
9. Cloudy 011X-Y table, 20...control unit. Figure 1
Claims (2)
この電圧設定部で指定された電圧を発生する電圧発生部
と、前記印加電圧の極性を切換える極性切換部と、被試
験物に流れた電流を測定する電流測定部を有し、前記被
試験物に異なる電圧を短時間印加し、それぞれの電流値
を測定することにより電子部品を破壊することなく試験
を行うようにしたことを特徴とする電子部品の接続状態
の試験方法。(1) A voltage setting section that can set the applied voltage and application time,
The voltage generating section generates the voltage specified by the voltage setting section, the polarity switching section switches the polarity of the applied voltage, and the current measuring section measures the current flowing through the test object. A method for testing the connection state of an electronic component, characterized in that the test is performed without destroying the electronic component by applying different voltages for a short period of time and measuring the respective current values.
と、被試験物の測定箇所に直接接触するプローブ付きZ
ステージと、前記被試験物を移動するX−Yテーブルと
、これら電圧印加測定部とプローブ付きZステージおよ
びX−Yテーブルを制御する制御部を備えてなることを
特徴とする電子部品の接続状態の試験装置。(2) A voltage application and measurement section using the test method according to claim 1, and a Z with a probe that directly contacts the measurement location of the test object.
A connection state of an electronic component characterized by comprising a stage, an X-Y table for moving the object under test, and a control section for controlling the voltage application and measurement section, the Z stage with a probe, and the X-Y table. test equipment.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2233411A JPH04115173A (en) | 1990-09-05 | 1990-09-05 | Method and apparatus for testing connection state of electronic part |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2233411A JPH04115173A (en) | 1990-09-05 | 1990-09-05 | Method and apparatus for testing connection state of electronic part |
Publications (1)
Publication Number | Publication Date |
---|---|
JPH04115173A true JPH04115173A (en) | 1992-04-16 |
Family
ID=16954645
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2233411A Pending JPH04115173A (en) | 1990-09-05 | 1990-09-05 | Method and apparatus for testing connection state of electronic part |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH04115173A (en) |
-
1990
- 1990-09-05 JP JP2233411A patent/JPH04115173A/en active Pending
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