JPH0449649A - Lead frame for semiconductor device - Google Patents
Lead frame for semiconductor deviceInfo
- Publication number
- JPH0449649A JPH0449649A JP15949390A JP15949390A JPH0449649A JP H0449649 A JPH0449649 A JP H0449649A JP 15949390 A JP15949390 A JP 15949390A JP 15949390 A JP15949390 A JP 15949390A JP H0449649 A JPH0449649 A JP H0449649A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- semiconductor
- semiconductor element
- semiconductor device
- lead
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 83
- 239000011347 resin Substances 0.000 abstract description 23
- 229920005989 resin Polymers 0.000 abstract description 23
- 238000007789 sealing Methods 0.000 abstract description 8
- 238000009413 insulation Methods 0.000 abstract description 5
- 238000005476 soldering Methods 0.000 abstract description 4
- 239000000853 adhesive Substances 0.000 description 18
- 230000001070 adhesive effect Effects 0.000 description 18
- 239000000463 material Substances 0.000 description 8
- 239000003566 sealing material Substances 0.000 description 8
- 238000000034 method Methods 0.000 description 6
- 229920001721 polyimide Polymers 0.000 description 4
- 239000000725 suspension Substances 0.000 description 4
- 230000008646 thermal stress Effects 0.000 description 4
- 229910000640 Fe alloy Inorganic materials 0.000 description 3
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 239000004642 Polyimide Substances 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 230000008020 evaporation Effects 0.000 description 2
- 238000001704 evaporation Methods 0.000 description 2
- 238000004806 packaging method and process Methods 0.000 description 2
- 229910052710 silicon Inorganic materials 0.000 description 2
- 239000010703 silicon Substances 0.000 description 2
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000004593 Epoxy Substances 0.000 description 1
- NIXOWILDQLNWCW-UHFFFAOYSA-N acrylic acid group Chemical group C(C=C)(=O)O NIXOWILDQLNWCW-UHFFFAOYSA-N 0.000 description 1
- 239000003795 chemical substances by application Substances 0.000 description 1
- 230000000052 comparative effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000010292 electrical insulation Methods 0.000 description 1
- 239000008393 encapsulating agent Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 229910052759 nickel Inorganic materials 0.000 description 1
- 230000002265 prevention Effects 0.000 description 1
- 230000035939 shock Effects 0.000 description 1
- 230000035882 stress Effects 0.000 description 1
- 229920001169 thermoplastic Polymers 0.000 description 1
- 229920001187 thermosetting polymer Polymers 0.000 description 1
- 239000004416 thermosoftening plastic Substances 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/4826—Connecting between the body and an opposite side of the item with respect to the body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73215—Layer and wire connectors
Abstract
Description
【発明の詳細な説明】
〈産業上の利用分野〉
本発明は、樹脂封止される半導体装置に用いられるリー
ドフレームに関するものである。DETAILED DESCRIPTION OF THE INVENTION <Industrial Application Field> The present invention relates to a lead frame used in a resin-sealed semiconductor device.
〈従来の技術〉
従来、樹脂封止型の半導体装置に用いられるリードフレ
ーム１としては、第５図に示すように、外枠２と、リー
ド部３と、素子支持部４とを具え、素子支持部４は吊リ
ード５を介して外枠２に支持される。 かかるリードフ
レーム１の素子支持部４に接着剤を介して半導体素子６
を搭載したのち、半導体素子６とリードフレーム１のり
−ド３のインナリード７の間をボンディングワイヤ８で
接続し、さら、に封止材９で封止されている。 このよ
うにして得られた半導体装置の従来断面構造図を第６図
に示す。<Prior Art> Conventionally, as shown in FIG. 5, a lead frame 1 used in a resin-sealed semiconductor device includes an outer frame 2, a lead part 3, and an element support part 4, and is used to support an element. The support part 4 is supported by the outer frame 2 via a hanging lead 5. A semiconductor element 6 is attached to the element support portion 4 of the lead frame 1 via an adhesive.
After mounting, the semiconductor element 6 and the inner leads 7 of the lead frame 1 and the board 3 are connected by bonding wires 8, and further sealed with a sealing material 9. A conventional cross-sectional structural diagram of a semiconductor device thus obtained is shown in FIG.
近年、半導体素子が高集積化し、これと共に大型化して
いる。 しかしメモリ系などでは、高密度実装のために
、パッケージをできる限り小型化したいという要求があ
る。In recent years, semiconductor devices have become highly integrated and have also become larger. However, in memory systems and the like, there is a demand for packages to be as small as possible in order to achieve high-density packaging.
このために例えば、素子支持部４を、ポリイミドのよう
な、樹脂フィルムとし、このフィルムに接着剤を予め被
覆するか、組立工程中に塗布して、半導体素子を接着固
定する方式が提唱されている。For this purpose, for example, a method has been proposed in which the element support part 4 is made of a resin film such as polyimide, and this film is coated with an adhesive in advance or applied during the assembly process to adhesively fix the semiconductor element. There is.
例えば特開昭第６１−２４１９５９号には、リードを半
導体素子上に這わせることにより、収納効率を高めたも
のが開示されている。 このパッケージ構造において、
半導体素子の主表面にリードフレームを接着しているが
、実際には半導体素子とリードとの電気的な絶縁をとる
ために、ポリイミドフィルムに接着剤を被覆して接着し
ている。 また、例えば特開昭第６０−１６７４５４号
には、同様の目的のもとに樹脂フィルムにあらかじめ接
着剤を被覆してお（か、あるいは組み立て工程中で接着
剤を塗布して、これによりリードフレームおよび半導体
素子の両方を接着固定するものが開示されている。For example, Japanese Patent Application Laid-Open No. 61-241959 discloses a device in which the storage efficiency is improved by extending the leads over the semiconductor element. In this package structure,
A lead frame is bonded to the main surface of the semiconductor element, but in reality, in order to provide electrical insulation between the semiconductor element and the leads, a polyimide film is coated with an adhesive and bonded. For example, Japanese Patent Application Laid-Open No. 60-167454 discloses that for the same purpose, a resin film is coated with an adhesive in advance (or the adhesive is applied during the assembly process, and this leads to Adhesive fixation of both the frame and the semiconductor device is disclosed.
また、例えば、特開昭第６３−２１３６５号には、半導
体素子とリード先端との接着性を良好とし、これらの間
に水分が入り込むのを防止するため、リードの先端部に
樹脂フィルムと接着層とを介して半導体素子を固定する
構造が開示されている。For example, in JP-A No. 63-21365, in order to improve the adhesion between the semiconductor element and the lead tips and to prevent moisture from entering between them, a resin film and an adhesive are attached to the tips of the leads. A structure for fixing a semiconductor element through a layer is disclosed.
〈発明が解決しようとする課題〉
しかし、リードフレームに絶縁剤として用いられる樹脂
フィルムには吸湿性および保湿性があり、この性質が半
導体装置に多大な影響を与えることがある。 例えば通
常使用されるポリイミドフィルムは、重量比で最大約２
％程度の水分を取り込む。 この水分を保有する樹脂フ
ィルムが、樹脂封止された半導体装置内に存在する場合
に、この半導体装置を例えばプリント配線基板に半田付
けする際に、この装置の中の樹脂フィルムが約２００℃
以上の高温にさらされ、このとき樹脂フィルム中の水分
が気化して半導体装置内で急激に膨張し、封止樹脂にク
ラックを発生させることがあるという問題点がある。<Problems to be Solved by the Invention> However, the resin film used as an insulating agent in the lead frame has hygroscopic and moisture-retaining properties, and these properties can have a great influence on semiconductor devices. For example, commonly used polyimide films have a weight ratio of up to about 2
It takes in about % of water. When a resin film that retains moisture is present in a resin-sealed semiconductor device, when this semiconductor device is soldered to a printed wiring board, for example, the resin film inside this device is heated to about 200°C.
When exposed to such high temperatures, moisture in the resin film evaporates and rapidly expands within the semiconductor device, which may cause cracks in the sealing resin.
また、上記半田付は工程時に半導体装置が高温にさらさ
れた場合、半導体素子と樹脂フィルム製の素子支持部と
の間、または半導体素子と封止材との間の熱膨張差に起
因する熱応力が加わり、封止材および／または半導体素
子にクラックが発生するという問題点がある。In addition, when the semiconductor device is exposed to high temperatures during the soldering process, heat generated due to the difference in thermal expansion between the semiconductor element and the element support made of resin film, or between the semiconductor element and the encapsulant may be generated. There is a problem in that stress is applied and cracks occur in the sealing material and/or the semiconductor element.
本発明の目的は、上述した従来のリードフレームの問題
点を解消し、かかる半導体装置の実装時に半導体装置の
パッケージにクラックが発生するのを防止することがで
きる半導体装置用のリードフレームを提供することにあ
る。An object of the present invention is to provide a lead frame for a semiconductor device that can solve the above-mentioned problems of conventional lead frames and prevent cracks from occurring in the package of the semiconductor device when the semiconductor device is mounted. There is a particular thing.
く課題を解決するための手段〉
上記目的を達成するため本発明によれば、半導体素子を
坦持する素子支持部を有する、樹脂封止される半導体装
置用のリードフレームにおいて、
前記素子支持部は、前記半導体素子を安定に支持しえる
複数の支持部分を有し、前記リードフレームは、前記半
導体素子をリードフレームの占める平面から離間する側
にオフセットするための腕部を有することを特徴とする
半導体装置用のリードフレームが提供される。Means for Solving the Problems> In order to achieve the above object, the present invention provides a lead frame for a resin-sealed semiconductor device, which has an element support part that supports a semiconductor element, the element support part is characterized in that it has a plurality of support parts capable of stably supporting the semiconductor element, and the lead frame has arm parts for offsetting the semiconductor element away from a plane occupied by the lead frame. A lead frame for a semiconductor device is provided.
上記のように素子支持部をリードフレームからオフセッ
ト配置することにより、リードフレームの占める平面と
半導体素子との間に隙間が生じ、この隙間に、樹脂封止
の際に、樹脂が満たされて、半導体素子とリードフレー
ムとの間の絶縁が保たれる。 したがって、絶縁のため
の樹脂フィルムを使用する必要がなくなり、樹脂フィル
ムに起因する半田付は時の水分の蒸発、膨張が無くなり
、半導体パッケージのクラックの発生を防止できる。By arranging the element support part offset from the lead frame as described above, a gap is created between the plane occupied by the lead frame and the semiconductor element, and this gap is filled with resin during resin sealing. Insulation between the semiconductor element and the lead frame is maintained. Therefore, there is no need to use a resin film for insulation, and there is no moisture evaporation or expansion during soldering caused by the resin film, and cracks in the semiconductor package can be prevented.
ここで、前記素子支持部のオフセット量が０．１〜０．
７ｍｍであるのが好ましい。 このように数値限定した
のは、１．７ｍｍより大きい部分は、オフセット加工そ
のものが難しくなると共にパッケージの厚みがそれだけ
厚くなり、最近の薄肉化の要求に逆行することになる。Here, the offset amount of the element support portion is 0.1 to 0.
Preferably, it is 7 mm. The reason for this numerical limitation is that if the part is larger than 1.7 mm, offset processing itself becomes difficult and the thickness of the package increases accordingly, which goes against the recent demand for thinning.
また０、１ｍｍより小さくなると、リードフレームのわ
ずか（０，１ｍｍ程度）の変形によりリードと半導体素
子とが接触することになり、電気的な短絡及び半導体素
子の破損の問題を生じる。 また、モールドでレジンが
十分溝たされるためには０．１ｍｍ程度の隙間が必要で
あるという理由からである。If it is smaller than 0.1 mm, the lead and the semiconductor element will come into contact with each other due to slight (about 0.1 mm) deformation of the lead frame, causing problems of electrical short circuit and damage to the semiconductor element. Another reason is that a gap of about 0.1 mm is required in order for the resin to be sufficiently grooved in the mold.
以下に本発明をさらに詳細に説明する。The present invention will be explained in more detail below.
第１図は、本発明のリードフレームの１実施例を示す平
面図である。FIG. 1 is a plan view showing one embodiment of the lead frame of the present invention.
リードフレーム１１は、外枠１３、リード部１５および
素子支持部１７を有する。The lead frame 11 has an outer frame 13, a lead part 15, and an element support part 17.
リード部１５は、樹脂封止時に封止材に封止されるイン
ナーリード１９と、外側に出るアウターリード２１とを
有する。 インナーリード１９の先端部は、できだけ内
部に伸延するほど好ましく、樹脂封止される際に、ワイ
ヤボンディング部分が封止樹脂の中心に位置することに
なるので、作製された半導体装置に耐湿性の大幅な向上
をもたらすことができる。The lead portion 15 has an inner lead 19 that is sealed with a sealing material during resin sealing, and an outer lead 21 that extends outside. It is preferable that the tips of the inner leads 19 extend as far inward as possible, and since the wire bonding portion will be located in the center of the sealing resin when resin-sealed, the fabricated semiconductor device will have moisture resistance. can bring about a significant improvement in
素子支持部１７は、外枠１３の２個の短辺中央から支持
部吊リード２３を介してそれぞれ連続的に延設されてい
る。 支持部吊リード２３は、素子支持部１７に半導体
素子を載置しても充分な保持強度を有するものである。The element support portions 17 extend continuously from the centers of the two short sides of the outer frame 13 via support portion suspension leads 23 . The support part suspension lead 23 has sufficient holding strength even when a semiconductor element is placed on the element support part 17.
素子支持部１７は、第２図の側面図に示すように、半
導体素子を支持する平坦部３５ａ、３５ｂを有し、支持
部吊リード２３には、リードフレーム１１が占める平面
から平坦部３５ａ、３５ｂを離間させる腕部３３ａ、３
３ｂを有する。As shown in the side view of FIG. 2, the element support part 17 has flat parts 35a and 35b that support the semiconductor element. Arm parts 33a, 3 that separate 35b
3b.
この発明において、素子支持部１７平坦部３５ ａ、
３５ ｂおよび支持吊リード２３の腕部３３ａ、３３
ｂは第１図および第２図に示すような形状、寸法に限定
されず、実際に半導体素子が安定に載置され、熱応力に
強いような形状、寸法であればよい。In this invention, the flat part 35a of the element support part 17,
35b and the arm portions 33a, 33 of the support suspension lead 23
b is not limited to the shape and dimensions shown in FIGS. 1 and 2, but may be any shape or dimension that allows the semiconductor element to be stably mounted and is resistant to thermal stress.
例えば、第４図に示すような他の実施例では、図の上下
方向の頬部が残るように、各々の平坦部３５ａ、３５ｂ
の内側に切り欠きを設けて、平坦部の支持に関与する部
分が全体で４個形成されて、平坦部３５ｃ〜３５ｆが形
成されるようにしたものである。For example, in another embodiment as shown in FIG. 4, each flat portion 35a, 35b is
A notch is provided on the inside of the holder, so that a total of four parts involved in supporting the flat part are formed, and flat parts 35c to 35f are formed.
ただし、平坦部３５ａ〜３５ｂ、３５ｃ〜３５ｆの長手
方向の長さは、短ければ短いほど、リードフレーム１１
と載置される半導体素子との間の熱膨張差に起因する熱
応力の影響を小さ（することができる。 この素子支持
部１７の長手方向の長さは、素子固着強度との兼ね合い
から、経験的に５ｍｍ以内であれば固着強度およびクラ
ック防止性の双方に対して良好な結果が得られている。However, the shorter the length of the flat portions 35a to 35b, 35c to 35f in the longitudinal direction, the shorter the length of the lead frame 11.
The influence of thermal stress caused by the difference in thermal expansion between the semiconductor element and the mounted semiconductor element can be reduced. The length of the element support part 17 in the longitudinal direction is determined from the viewpoint of the element fixing strength. Experience has shown that good results have been obtained for both adhesion strength and crack prevention when the thickness is within 5 mm.
この理由としては、加熱時に生じる熱応力がもっばら
長手方向の長さに依存して決まるため、この長さを減少
させると、リードフレームと半導体素子（シリコン）と
の間並びにリードフレームと封止部材との間の熱応力を
減少させる作用がある。 ちなみに、これら材料の熱膨
張係数は、リードフレーム材において鉄系で５〜１５Ｘ
１０−’１／ ’Ｃ、シリコンでは４〜５Ｘ１０−’１
／”Ｃ１封止樹脂でＩＯ〜３０ｘｌＯ−＠１／”Ｃであ
る。The reason for this is that the thermal stress generated during heating depends mostly on the length in the longitudinal direction, so if this length is reduced, the gap between the lead frame and the semiconductor element (silicon) as well as the seal between the lead frame and the It has the effect of reducing thermal stress between components. By the way, the coefficient of thermal expansion of these materials is 5 to 15X for iron-based lead frame materials.
10-'1/'C, 4-5X10-'1 for silicon
/"C1 sealing resin is IO~30xlO-@1/"C.
このため、これらの部材間の熱膨張差に起因する半導体
装置のパッケージにクラックが発生するのを防止する一
要素となる。Therefore, it becomes an element for preventing cracks from occurring in the package of the semiconductor device due to the difference in thermal expansion between these members.
素子支持部１７の長手方向の長さの下限は特に設けない
が、リードフレームの加工上の制約からインナーリード
１９の幅寸法（はぼ０． １〜０．３ｍｍ）とほぼ同等
の長さと考えてよい。Although there is no particular lower limit for the length of the element support part 17 in the longitudinal direction, it is considered to be approximately the same length as the width dimension of the inner lead 19 (approximately 0.1 to 0.3 mm) due to constraints in processing the lead frame. It's fine.
このようなリードフレーム１１の素子支持部１７に、第
３図の断面図にて示すように、素子支持部１７のインナ
ーリード側とは反対側に半導体素子２５が載置され、さ
らにそれらが接着され、ボンディングワイヤ２７がイン
ナーリード１９の先端部および半導体素子２５の電極端
子の間で設けられ、最後に封止材２９で樹脂封止されて
半導体装置３１が形成される。 この場合にインナーリ
ード１９が半導体素子２５の上に延在するため、半導体
素子２５の電極端子へ接続されるボンディングワイヤ２
７の長さが短くなり、すなわちワイヤの取り回し長さが
短くなるため、配線の集積密度を高めることができる。As shown in the cross-sectional view of FIG. 3, the semiconductor element 25 is placed on the element support part 17 of the lead frame 11 on the side opposite to the inner lead side of the element support part 17, and is further bonded. Then, a bonding wire 27 is provided between the tip of the inner lead 19 and the electrode terminal of the semiconductor element 25, and finally the semiconductor device 31 is resin-sealed with a sealing material 29. In this case, since the inner lead 19 extends above the semiconductor element 25, the bonding wire 2 connected to the electrode terminal of the semiconductor element 25
Since the length of the wire 7 is shortened, that is, the wire routing length is shortened, the wiring integration density can be increased.
この第３図から分かるように、半導体素子２５は、素子
支持部１７のリードフレーム１１から離間する側に載置
されている。 こ の ため、リードフレーム１１およ
び半導体素子２５の間に封止材２９が満たされる。As can be seen from FIG. 3, the semiconductor element 25 is placed on the side of the element support section 17 that is spaced apart from the lead frame 11. Therefore, the sealing material 29 is filled between the lead frame 11 and the semiconductor element 25.
リードフレーム１１と半導体素子２５との接着について
は、リードフレーム作製段階でリードフレーム側すなわ
ち素子支持部１７に接着剤を塗布している。 この方が
製品の精度、歩留り等の観点で良好な結果が得られるた
めである。 ひいては、素子接着工程が簡単になり、半
導体パッケージの組立コストを間接的に低減できる。
接着剤を塗布する部分については、少なくとも半導体素
子２５と接触する部分に塗布すればよく、もしも充分な
接着強度が得られるのならば、さらに少ない面積に塗布
してもよい。Regarding adhesion between the lead frame 11 and the semiconductor element 25, an adhesive is applied to the lead frame side, that is, the element support portion 17, at the lead frame manufacturing stage. This is because better results can be obtained in terms of product accuracy, yield, etc. As a result, the element bonding process is simplified, and the assembly cost of the semiconductor package can be indirectly reduced.
Regarding the parts to be coated with the adhesive, it is sufficient to apply the adhesive to at least the parts that come into contact with the semiconductor element 25, and if sufficient adhesive strength can be obtained, the adhesive may be applied to an even smaller area.
接着剤としては、アクリル系、エポキシ系、ポリイミド
系の熱硬化型のものを、半硬化状態で用いるか、または
ポリエーテルアミドイミド等の熱可塑型のものを用いる
こともできる。As the adhesive, a thermosetting adhesive such as acrylic, epoxy, or polyimide may be used in a semi-cured state, or a thermoplastic adhesive such as polyetheramideimide may be used.
本発明に用いられるリードフレーム１１の材料としては
、Ｃｕ、Ｃｕ合金およびＦｅ合金等の通常のリードフレ
ーム材として用いられるものであれば何でもよい。 例
えば４２％Ｎｉ−Ｆｅ合金は低熱膨張化がある程度なさ
れているので、本発明のリードフレーム材料として有効
である。The material of the lead frame 11 used in the present invention may be any material that is used as a normal lead frame material, such as Cu, Cu alloy, and Fe alloy. For example, 42% Ni--Fe alloy has a certain degree of low thermal expansion and is therefore effective as the lead frame material of the present invention.
〈実施例〉 以下に本発明を実施例に基づき具体的に説明する。<Example> The present invention will be specifically explained below based on Examples.
（実施例１）
リードフレーム材として板厚０．２５ｍｍの４２％Ｎｉ
−Ｆｅ合金を用い、第１図に示すような形状の素子支持
部１７を有する、ビン数２０のＤＩＰ用のリードフレー
ム１１を作製した。 各素子支持部１７の長手方向の長
さは搭載する素子の短辺の長さにほぼ等しい５ｍｍとし
、幅方向の長さは２ｍｍとした。 素子支持部１７は、
その平坦部がリードフレーム１１から０．２ｍｍ離間さ
れるようにして、リードフレーム平面と半導体素子２５
との間に０．２ｍｍの隙間が形成されるようにした。(Example 1) 42% Ni with a plate thickness of 0.25 mm as lead frame material
A lead frame 11 for DIP with 20 bins and having an element support portion 17 shaped as shown in FIG. 1 was manufactured using a -Fe alloy. The length in the longitudinal direction of each element support part 17 was set to 5 mm, which was approximately equal to the length of the short side of the mounted element, and the length in the width direction was set to 2 mm. The element support part 17 is
The flat part of the lead frame 11 is separated from the semiconductor element 25 by 0.2 mm.
A gap of 0.2 mm was formed between the two.
このリードフレーム１１を用い、素子支持部１７に半導
体素子を搭載したのち、直径２５マイクロメートルの金
製のボンディングワイヤでインナーリード４との間をボ
ンディングし、樹脂封止して１メガビツトのＤＲＡＭ相
当の半導体装置を作製した。After mounting a semiconductor element on the element support part 17 using this lead frame 11, it is bonded to the inner lead 4 using a gold bonding wire with a diameter of 25 micrometers, and is sealed with resin to form a device equivalent to a 1 megabit DRAM. A semiconductor device was fabricated.
この半導体装置について一５５℃〜１５０℃の温度差で
３００サイクルのヒートサイクル試験および一６５℃〜
１５０℃の温度差で１５サイクルの熱衝撃試験を行った
が半導体素子および封止材にクラックが生じなかった。This semiconductor device was subjected to a heat cycle test of 300 cycles with a temperature difference of -55℃ to 150℃ and a temperature difference of -65℃ to 150℃.
A thermal shock test was conducted for 15 cycles at a temperature difference of 150° C., but no cracks occurred in the semiconductor element or the sealing material.
比較のため、第５図に平面図で示すような形状および寸
法、即ち長さ１３ｍｍＸ幅５ｍｍの矩形の素子支持部を
有する他は、上述した実施例と同様のリードフレームを
使用した半導体装置を作製して同様な試験を行ったとこ
ろ、供試サンプルの約１０％に封止材の外部にまで達す
るクラックが観察され、さらに供試サンプルの約７０％
に内部クラックが観察された。For comparison, a semiconductor device using a lead frame similar to that of the above-mentioned embodiment was used, except that it had a rectangular element support part with the shape and dimensions as shown in the plan view in FIG. When fabricated and subjected to similar tests, cracks reaching the outside of the sealing material were observed in about 10% of the test samples, and in about 70% of the test samples.
Internal cracks were observed.
（実施例２）
実施例１と同じリードフレーム材を用い、第４図に示す
ような素子支持部１７を有し、半導体素子と接触する面
にデイスペンサを用いてポリエーテルアミドイミド接着
剤（日立化成工業社製）を塗布した、ビン数２０のＤＩ
Ｐ用のリードフレーム１７を作製した。 素子支持部１
７８〜１７ｄはそれぞれ１．５Ｘ１．５ｍｍとした。
上記接着剤の塗布は極めて容易にできた。(Example 2) The same lead frame material as in Example 1 was used, it had an element support part 17 as shown in FIG. 4, and a dispenser was used to apply polyetheramide-imide adhesive (Hitachi DI with 20 bottles coated with Kasei Kogyo Co., Ltd.)
A lead frame 17 for P was produced. Element support part 1
78 to 17d were each 1.5×1.5 mm.
Application of the above adhesive was extremely easy.
このリードフレーム１１を用い、素子支持部１７に半導
体素子を搭載したのち、実施例１と同様にして１メガビ
ットＤＲＡＭ相当の半導体装置を作製した。After mounting a semiconductor element on the element support part 17 using this lead frame 11, a semiconductor device equivalent to a 1 megabit DRAM was manufactured in the same manner as in Example 1.
この半導体装置について、実施例１と同じ試験を行った
が、半導体素子および封止部材にクラックが観察されな
かった。This semiconductor device was subjected to the same test as in Example 1, but no cracks were observed in the semiconductor element or the sealing member.
〈発明の効果〉
以上の説明から理解できるように、本発明のリードフレ
ームでは、素子支持部をリードフレームからオフセット
配置することにより、リードフレームの占める平面と半
導体素子との間に隙間が生じ、この隙間に、樹脂封止の
際に、樹脂が満たされて、半導体素子とリードフレーム
との間の絶縁が保たれる。 したがって、絶縁のための
樹脂フィルムを使用する必要がなくなり、実装時の半田
付けの際に、樹脂フィルムに起因する水分の蒸発、膨張
が無（なり、したがって半導体パッケージのクラックを
防止することができる。<Effects of the Invention> As can be understood from the above description, in the lead frame of the present invention, by arranging the element support portion offset from the lead frame, a gap is created between the plane occupied by the lead frame and the semiconductor element. This gap is filled with resin during resin sealing to maintain insulation between the semiconductor element and the lead frame. Therefore, there is no need to use a resin film for insulation, and there is no evaporation or expansion of moisture caused by the resin film during soldering during mounting, thus preventing cracks in the semiconductor package. .
さらに、リードが半導体素子の上を延在することにより
、リードの引き回しが容易になり、リードフレームの設
計上の余裕が生じ有利になるとともにボンディングワイ
ヤの長さを短くできることにより、実装密度を高めるこ
とができる。 素子支持部にあらかじめ接着剤を塗布し
ておくことにより、素子接着工程が簡単になるため、半
導体パッケージ組み立てのコストの低減につながる。Furthermore, since the leads extend above the semiconductor element, it becomes easier to route the leads, creating more margin in the design of the lead frame, which is advantageous, and the length of the bonding wire can be shortened, increasing packaging density. be able to. By applying adhesive to the element support portion in advance, the element bonding process is simplified, leading to a reduction in the cost of assembling the semiconductor package.
【図面の簡単な説明】
第１図は、本発明のリードフレームの一実施例を示す平
面図である。
第２図は、−第１図に示すリードフレームを示す側面図
である。
第３図は、本発明のリードフレームを用いて作製した半
導体装置を示す断面図である。
第４図は、本発明のリードフレームの他の実施例を示す
平面図である。
第５図は、リードフレームの比較例を示す平面図である
。
第６図は、従来のリードフレームを用いて作製した半導
体装置を示す断面図である。
符号の説明
１１・・・リードフレーム、
１３・・・外枠、
１５・・・リード部、
１７・・・素子支持部、
１９・・・インナーリード、
２１・・・アウターリード、
２３・・・素子吊リード、
２５・・・半導体素子、
２７・・・ボンディングワイヤ、
２９・・・封止材、
３３ａ、３３ｂ・・・腕部、
３５ａ〜３５ｆ・・・平坦部
ＦＩＧ、１
ＦＩＧ、２
ＦＩＧ、３
Ｆ Ｉ Ｇ、 ４
ＦＩＧ、６BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view showing an embodiment of the lead frame of the present invention. 2 is a side view of the lead frame shown in FIG. 1; FIG. FIG. 3 is a cross-sectional view showing a semiconductor device manufactured using the lead frame of the present invention. FIG. 4 is a plan view showing another embodiment of the lead frame of the present invention. FIG. 5 is a plan view showing a comparative example of a lead frame. FIG. 6 is a cross-sectional view showing a semiconductor device manufactured using a conventional lead frame. Explanation of symbols 11... Lead frame, 13... Outer frame, 15... Lead portion, 17... Element support portion, 19... Inner lead, 21... Outer lead, 23... Element suspension lead, 25... Semiconductor element, 27... Bonding wire, 29... Sealing material, 33a, 33b... Arm part, 35a to 35f... Flat part FIG, 1 FIG, 2 FIG , 3 FIG, 4 FIG, 6
Claims (2)
封止される半導体装置用のリードフレームにおいて、 前記素子支持部が、前記半導体素子を安定に支持しえる
複数の支持部分を有し、前記リードフレームは、前記半
導体素子をリードフレームの占める平面から離間する側
にオフセットするための腕部を有することを特徴とする
半導体装置用のリードフレーム。(1) In a lead frame for a resin-sealed semiconductor device that has an element support part that supports a semiconductor element, the element support part has a plurality of support parts that can stably support the semiconductor element. . A lead frame for a semiconductor device, wherein the lead frame has an arm portion for offsetting the semiconductor element away from a plane occupied by the lead frame.
ｍｍである請求項１記載の半導体装置用のリードフレー
ム。(2) The offset amount of the element support part is 0.1 to 0.7
2. The lead frame for a semiconductor device according to claim 1, wherein the lead frame has a diameter of mm.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15949390A JPH0449649A (en) | 1990-06-18 | 1990-06-18 | Lead frame for semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15949390A JPH0449649A (en) | 1990-06-18 | 1990-06-18 | Lead frame for semiconductor device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0449649A true JPH0449649A (en) | 1992-02-19 |
Family
ID=15694972
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15949390A Pending JPH0449649A (en) | 1990-06-18 | 1990-06-18 | Lead frame for semiconductor device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0449649A (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4318727A1 (en) * | 1992-06-05 | 1993-12-09 | Mitsubishi Electric Corp | Semiconductor device with lead-on-chip-structure - has brazing solder material with no moisture absorption, formed on surface of semiconductor component and fixed to support plate |
| EP0807972A3 (en) * | 1996-05-09 | 2000-05-31 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of its fabrication |
-
1990
- 1990-06-18 JP JP15949390A patent/JPH0449649A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| DE4318727A1 (en) * | 1992-06-05 | 1993-12-09 | Mitsubishi Electric Corp | Semiconductor device with lead-on-chip-structure - has brazing solder material with no moisture absorption, formed on surface of semiconductor component and fixed to support plate |
| US5724726A (en) * | 1992-06-05 | 1998-03-10 | Mitsubishi Denki Kabushiki Kaisha | Method of making leadframe for lead-on-chip (LOC) semiconductor device |
| DE4318727C2 (en) * | 1992-06-05 | 1998-03-12 | Mitsubishi Electric Corp | Process for the production of a semiconductor device with LOC structure and associated leadframe |
| US5900582A (en) * | 1992-06-05 | 1999-05-04 | Mitsubishi Denki Kabushiki Kaisha | Lead frame including frame-cutting slit for lead-on-chip (LOC) semiconductor device and semiconductor device incorporating the lead frame |
| EP0807972A3 (en) * | 1996-05-09 | 2000-05-31 | Oki Electric Industry Co., Ltd. | Semiconductor device and method of its fabrication |
| US6258621B1 (en) | 1996-05-09 | 2001-07-10 | Oki Electric Industry Co., Ltd. | Method of fabricating a semiconductor device having insulating tape interposed between chip and chip support |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| TW473946B (en) | Semiconductor device and its manufacture method | |
| EP0502710B1 (en) | Flexible film semiconductor package | |
| US5585600A (en) | Encapsulated semiconductor chip module and method of forming the same | |
| JP2702219B2 (en) | Semiconductor device and manufacturing method thereof | |
| JPH0613502A (en) | Semiconductor integrated circuit chip | |
| JPH06236946A (en) | Heat spreader and semiconductor device having strengthened connection between lead and plastic package | |
| KR950005450B1 (en) | Plastic-molded-type semiconductro device and producing method therefor | |
| JPS60167454A (en) | Semiconductor device | |
| US6297544B1 (en) | Semiconductor device and method for manufacturing the same | |
| JPH0449649A (en) | Lead frame for semiconductor device | |
| JPH04158556A (en) | Reasin-sealed type semiconductor device | |
| JPS59207646A (en) | Semiconductor device and lead frame | |
| JPH0415947A (en) | Semiconductor device lead frame and semiconductor device | |
| JPH0475355A (en) | Joining method of semiconductor element to lead frame | |
| US5969410A (en) | Semiconductor IC device having chip support element and electrodes on the same surface | |
| JPH0437050A (en) | Resin seal type semiconductor device | |
| JPH03195052A (en) | Lead frame and manufacture thereof | |
| JPH02143449A (en) | Semiconductor sealing vessel | |
| JP2737332B2 (en) | Integrated circuit device | |
| KR0155441B1 (en) | Semiconductor package | |
| JPH03109757A (en) | Resin-sealed semiconductor device | |
| JPH02178953A (en) | Resin-sealed semiconductor device | |
| JPH03236249A (en) | Semiconductor chip module | |
| JPH05291739A (en) | Connecting terminal and connecting method for device using same | |
| JPH03228358A (en) | Resin-sealed semiconductor device |