JPH0449630A - Alloy brazing material for semiconductor device assembly - Google Patents

Alloy brazing material for semiconductor device assembly

Info

Publication number
JPH0449630A
JPH0449630A JP15884390A JP15884390A JPH0449630A JP H0449630 A JPH0449630 A JP H0449630A JP 15884390 A JP15884390 A JP 15884390A JP 15884390 A JP15884390 A JP 15884390A JP H0449630 A JPH0449630 A JP H0449630A
Authority
JP
Japan
Prior art keywords
brazing material
alloy
nitrogen atmosphere
casted
semiconductor device
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15884390A
Other languages
Japanese (ja)
Inventor
Hirotaka Minami
浩尚 南
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sumitomo Metal Mining Co Ltd
Original Assignee
Sumitomo Metal Mining Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sumitomo Metal Mining Co Ltd filed Critical Sumitomo Metal Mining Co Ltd
Priority to JP15884390A priority Critical patent/JPH0449630A/en
Publication of JPH0449630A publication Critical patent/JPH0449630A/en
Pending legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L24/26Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
    • H01L24/31Structure, shape, material or disposition of the layer connectors after the connecting process
    • H01L24/32Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Die Bonding (AREA)

Abstract

PURPOSE:To enable reliability of a semiconductor device to be improved by allowing Ni, Cu, and P to be contained together and by specifying a composition of Ni, Cu, and P in an Sb-Sn alloy brazing material for effectively restricting growth of an intermetallic compound layer between Ni-Sn or Cu-Sn metal. CONSTITUTION:Although a title item is an Sb-Sn alloy brazing material, it contains Ni, Cu, and P together, a sum of the Ni and Cu is 0.05-1.0wt.%, and P is 0.005-0.5wt.%. The Sn-P mother alloy is melted in nitrogen atmosphere previously and Sn, Sb, Ni, and Cu are ingot together for blending, it is put into a graphite crucible, it is dissolved within atmospheric air at a high-frequency induction heating furnace, and then it is casted into a mold for forming a casted mass. A molded brazing material is obtained from that casted mass by extrusion machining, rolling machining, and punching. These molded brazing materials are placed on a non-oxygen steel plate and is heated and dissolved in nitrogen atmosphere. Then, the molded brazing materials are welded to a Cu plate and a Cu plate which is subjected to Ni plating in nitrogen atmosphere.

Description

【発明の詳細な説明】 〔産業上の利用分野〕 本発明は、半導体装置の組立てに使用する合金ろう材に
関する。
DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a brazing alloy material used in the assembly of semiconductor devices.

〔従来の技術〕[Conventional technology]

半導体装置の組立てにおいては、シリコンチップをリー
ドフレームなどの基板にろう材を用いて固定することが
行われる。すなわち、第1図の拡大断面図に示すように
、基板1にシリコンチップ2を、ろう材3によって接合
する。半導体装置の断続動作により熱サイクルがかかる
が、この際生じる応力によりろう材と基板の接合界面近
傍にクラックなどの欠陥が発生し、その信親性を損なう
場合がある。これは、ろう材と基板との界面に生成する
金属間化合物層4が原因である。すなわち基板にNiめ
っきが施されている場合には4i−Sn、めっきが施さ
れていないCu基板の場合にはCu−Snの金属間化合
物層が生成し、またこれが生成することにより接合が成
されるわけであるが、金属間化合物層は、接合が完了し
た後も、その後の熱履歴により成長を続ける。これらの
金属間化合物は、いずれも機械的に硬くて脆いため、成
長して必要以上に厚くなると、ろう材が基板の熱膨張率
と半導体素子の熱膨張率との差を緩和することができな
くなり、上記の欠陥を招くことになる。
In assembling a semiconductor device, a silicon chip is fixed to a substrate such as a lead frame using a brazing material. That is, as shown in the enlarged sectional view of FIG. 1, a silicon chip 2 is bonded to a substrate 1 using a brazing material 3. The intermittent operation of a semiconductor device causes a thermal cycle, and the stress generated during this process may cause defects such as cracks near the bonding interface between the brazing material and the substrate, impairing its reliability. This is caused by the intermetallic compound layer 4 generated at the interface between the brazing material and the substrate. In other words, an intermetallic compound layer of 4i-Sn is formed when the substrate is plated with Ni, and a layer of Cu-Sn is formed when the substrate is not plated with Cu, and this formation also leads to the formation of the bond. However, even after the bonding is completed, the intermetallic compound layer continues to grow due to subsequent thermal history. All of these intermetallic compounds are mechanically hard and brittle, so if they grow and become thicker than necessary, the brazing filler metal will not be able to alleviate the difference between the coefficient of thermal expansion of the substrate and the coefficient of thermal expansion of the semiconductor element. This results in the above-mentioned defects.

〔発明が解決しようとする課題〕[Problem to be solved by the invention]

本発明の目的は、上記のような従来の問題点を解消して
、Ni−SnあるいはCu −Snの金属間化合物層の
成長を効果的に抑制し、半導体装置の信韻性を向上する
ことができる合金ろう材を提供するものである。
An object of the present invention is to solve the above-mentioned conventional problems, effectively suppress the growth of Ni-Sn or Cu-Sn intermetallic compound layers, and improve reliability of semiconductor devices. The purpose is to provide a brazing alloy material that can be used.

【課題を解決するための手段〕[Means to solve the problem]

本発明は上記目的を達成するために、Sb−Sn系合金
ろう材であって、Ni、CuおよびPを共に含有し、N
iとCuの和が、0.05〜1.0重量%であり、Pが
0.005〜0.5重量%である点に特徴がある。
In order to achieve the above object, the present invention is an Sb-Sn alloy brazing filler metal containing both Ni, Cu and P, and N
It is characterized in that the sum of i and Cu is 0.05 to 1.0% by weight, and P is 0.005 to 0.5% by weight.

〔作 用〕[For production]

該Sb−Sn系合金ろう材においてsbは、ろう材自身
の機械的強度を向上するために添加するが、1.0重量
%未満では充分な強度を確保することができず、10重
量%を越えるとろう材が脆くなり塑性加工が困難となる
ため実用的範囲は通常1.0〜10重量%である。Ni
およびCuは、接合に際してろう材と基板の界面に生成
するNi−SnあるいはCu−Snの金属間化合物層の
成長を抑制するために添加する。金属間化合物の成長を
抑制するには、接合する相手側の材質と同じ元素を添加
することが最も効果的であり、あらかじめそれが解って
いる場合には、その材質と同じ元素のみ、すなわちNi
またはCuのいずれかのみを添加しておけばよい。
In the Sb-Sn alloy brazing filler metal, sb is added to improve the mechanical strength of the brazing filler metal itself, but if it is less than 1.0% by weight, sufficient strength cannot be ensured. If it exceeds this, the brazing filler metal becomes brittle and plastic working becomes difficult, so the practical range is usually 1.0 to 10% by weight. Ni
and Cu are added to suppress the growth of an intermetallic compound layer of Ni--Sn or Cu--Sn that is generated at the interface between the brazing material and the substrate during bonding. The most effective way to suppress the growth of intermetallic compounds is to add the same element as the material to be joined, and if this is known in advance, add only the same element as the material, i.e. Ni.
Alternatively, only either Cu may be added.

しかし、実際には、半導体素子の多品種化に対応するた
め、基板の種類が違っていても、同じ組成のろう材で賄
われることが一般的である。このため、NiとCuの両
方を添加しておくことにより、いずれの種類の基板でも
効率的に金属間化合物層の成長を抑えることができる。
However, in reality, in order to accommodate the diversification of semiconductor devices, it is common to use brazing filler metals with the same composition even if the types of substrates are different. Therefore, by adding both Ni and Cu, the growth of the intermetallic compound layer can be efficiently suppressed on any type of substrate.

NiとCuを添加すると、ろう材中には当然金属間化合
物が生成することになるが、この場合の金属間化合物は
、ろう材中に均一に微細分散し、化合物層を形成するわ
けではないため、半導体装置の信鯨性維持の妨げとはな
らない、また、金属間化合物が微細分散することによる
二次的な効果として、ろう材の高温強度が向上すること
があげられる。NiとCuO量が、合計して0.05重
量%未満では、化合物層の抑制効果に乏しく、また、1
.0重量%を越えると、ろう材中に、金属間化合物の粗
大粒ができ、脆くなるため、実用的範囲は0.06〜0
.7重量%である。また、NiおよびCuを添加したろ
う材は、基板上への濡れ広がり性が低下してしまうが、
これは、さらにPを添加することにより改善できる。こ
の濡れ広がり性を改善できるPの濃度は、0.005〜
0.5重量%の範囲であり、これを外れる添加量では効
果がない。また、Bi、Fe等の不可避不純物を含んで
も何ら差し支えない。
When Ni and Cu are added, intermetallic compounds are naturally generated in the brazing material, but in this case, the intermetallic compounds are uniformly and finely dispersed in the brazing material and do not form a compound layer. Therefore, it does not interfere with maintaining the reliability of the semiconductor device, and a secondary effect of finely dispersing the intermetallic compound is that the high-temperature strength of the brazing filler metal is improved. If the total amount of Ni and CuO is less than 0.05% by weight, the suppressing effect of the compound layer will be poor, and
.. If it exceeds 0% by weight, coarse grains of intermetallic compounds will form in the brazing filler metal, making it brittle, so the practical range is 0.06 to 0.
.. It is 7% by weight. In addition, brazing filler metals containing Ni and Cu have a reduced ability to spread on the substrate.
This can be improved by further adding P. The concentration of P that can improve this wettability is from 0.005 to
The amount is within the range of 0.5% by weight, and amounts added outside this range have no effect. Further, there is no problem even if unavoidable impurities such as Bi and Fe are included.

本発明のろう材はあらかじめ不活性ガス雰囲気中で溶製
したSn−P母合金を用い、これにSn、Sb、Ni。
The brazing filler metal of the present invention uses a Sn--P master alloy that has been previously melted in an inert gas atmosphere, and contains Sn, Sb, and Ni.

Cuを所望の組成に配合し、黒鉛ルツボ内で溶解後、撹
拌の後鋳型に鋳込み合金を得る。この合金を通常の押出
加工、圧延加工、打抜加工等により所望のフォイル状線
状、打抜品のろう材に成型すればよい。
Cu is blended into a desired composition, melted in a graphite crucible, stirred, and cast into a mold to obtain an alloy. This alloy may be formed into a desired foil-shaped, wire-shaped, or stamped brazing material by conventional extrusion, rolling, punching, or the like.

〔実施例〕〔Example〕

あらかじめ窒素雰囲気中で溶製したSn−P母合金とS
n、Sb、NiおよびCuを用いて第1表に示す組成に
配合し、黒鉛ルツボにいれ、高周波誘導加熱炉にて大気
中で溶解した後鋳型に鋳込み鋳塊とした。
A Sn-P master alloy melted in advance in a nitrogen atmosphere and S
The compositions shown in Table 1 were blended using Ni, Sb, Ni and Cu, placed in a graphite crucible, melted in the atmosphere in a high frequency induction heating furnace, and then cast into a mold to form an ingot.

その鋳塊から、押出し加工・圧延加工・打ち抜き加工に
より、縦4+w+、横4閣、厚さ0.1閣の成型ろう材
を得た。これらの成型ろう材を、縦10■、横105m
、厚さ0.5腫の無酸素鋼板にのせ、窒素雰囲気中で加
熱溶解し、濡れ広がり性を調査した結果を第1表に示す
0次に成型ろう材をCu板およびNiめっきを施したC
u板に、窒素雰囲気で300℃で溶着した。その後、各
試料を150℃に保持した恒温槽内に保管し、2,4.
8,25.64および100日後に抜き取り、X線マイ
クロアナライザー(EDX)により金属間化合物を同定
し、その成長幅を測定した。その結果を第2図(A)お
よび(B)に示す。第2図より、本発明合金ろう材No
9,10,11.12は、基板とろう材の接合界面に生
成する金属間化合物の成長を効果的に抑制することが解
る。
From the ingot, a molded brazing material having a length of 4+w+, a width of 4 mm, and a thickness of 0.1 mm was obtained by extrusion, rolling, and punching. These molded brazing materials are 10cm long and 105m wide.
, placed on an oxygen-free steel plate with a thickness of 0.5 mm, heated and melted in a nitrogen atmosphere, and investigated the wettability. Table 1 shows the results. C
It was welded to the U plate at 300°C in a nitrogen atmosphere. Thereafter, each sample was stored in a constant temperature bath kept at 150°C, and 2, 4.
8, 25, 64 and 100 days later, the intermetallic compounds were identified using an X-ray microanalyzer (EDX) and their growth width was measured. The results are shown in FIGS. 2(A) and 2(B). From FIG. 2, the present invention alloy brazing material No.
It can be seen that samples Nos. 9, 10, 11, and 12 effectively suppress the growth of intermetallic compounds generated at the bonding interface between the substrate and the brazing material.

〔発明の効果〕 本発明により、Ni−SnあるいはCu−Snの金属間
化合物層の成長を抑制することができ、半導体装置の信
頼性を向上することができる。
[Effects of the Invention] According to the present invention, growth of a Ni-Sn or Cu-Sn intermetallic compound layer can be suppressed, and the reliability of a semiconductor device can be improved.

【図面の簡単な説明】[Brief explanation of the drawing]

第1図は半導体装置の断面図、第2図(A)および(B
)は金属間化合物成長幅を示す図である。 1・・・基板、2・・・シリコンチップ、3・・・ろう
材、4・・・金属間化合物層。 特許出願人 住友金属鉱山株式会社
Figure 1 is a cross-sectional view of a semiconductor device, Figures 2 (A) and (B)
) is a diagram showing the intermetallic compound growth width. DESCRIPTION OF SYMBOLS 1...Substrate, 2...Silicon chip, 3...Brazing material, 4...Intermetallic compound layer. Patent applicant Sumitomo Metal Mining Co., Ltd.

Claims (1)

【特許請求の範囲】[Claims]  Sb−Sn系合金ろう材であって、Ni、Cuおよび
Pを共に含有し、NiとCuの和が0.05〜1.0重
量%であり、Pが0.005〜0.5重量%であること
を特徴とする半導体装置組立て用合金ろう材。
Sb-Sn alloy brazing material containing both Ni, Cu and P, the sum of Ni and Cu is 0.05 to 1.0% by weight, and P is 0.005 to 0.5% by weight An alloy brazing material for semiconductor device assembly, characterized by:
JP15884390A 1990-06-19 1990-06-19 Alloy brazing material for semiconductor device assembly Pending JPH0449630A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15884390A JPH0449630A (en) 1990-06-19 1990-06-19 Alloy brazing material for semiconductor device assembly

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15884390A JPH0449630A (en) 1990-06-19 1990-06-19 Alloy brazing material for semiconductor device assembly

Publications (1)

Publication Number Publication Date
JPH0449630A true JPH0449630A (en) 1992-02-19

Family

ID=15680623

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15884390A Pending JPH0449630A (en) 1990-06-19 1990-06-19 Alloy brazing material for semiconductor device assembly

Country Status (1)

Country Link
JP (1) JPH0449630A (en)

Cited By (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005119755A1 (en) * 2004-06-01 2005-12-15 Senju Metal Industry Co., Ltd Soldering method, solder pellet for die bonding, method for manufacturing solder pellet for die bonding and electronic component
JP2007110016A (en) * 2005-10-17 2007-04-26 Denso Corp Semiconductor device and method of manufacturing same
KR100898896B1 (en) * 2004-06-01 2009-05-21 센주긴조쿠고교 가부시키가이샤 Soldering method, solder pellet for die bonding, method for manufacturing solder pellet for die bonding and electronic component
CN108637030A (en) * 2018-05-08 2018-10-12 安徽科技学院 The liquid extrusion molding device of brittleness solder band
CN111916344A (en) * 2020-09-09 2020-11-10 合肥工业大学 Copper-copper low-temperature bonding method based on graphene/tin modified copper nanoparticles

Cited By (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
WO2005119755A1 (en) * 2004-06-01 2005-12-15 Senju Metal Industry Co., Ltd Soldering method, solder pellet for die bonding, method for manufacturing solder pellet for die bonding and electronic component
JPWO2005119755A1 (en) * 2004-06-01 2008-04-03 千住金属工業株式会社 Die bonding pellets and electronic components
KR100898896B1 (en) * 2004-06-01 2009-05-21 센주긴조쿠고교 가부시키가이샤 Soldering method, solder pellet for die bonding, method for manufacturing solder pellet for die bonding and electronic component
JP4844393B2 (en) * 2004-06-01 2011-12-28 千住金属工業株式会社 Die bonding method and electronic parts
JP2007110016A (en) * 2005-10-17 2007-04-26 Denso Corp Semiconductor device and method of manufacturing same
CN108637030A (en) * 2018-05-08 2018-10-12 安徽科技学院 The liquid extrusion molding device of brittleness solder band
CN108637030B (en) * 2018-05-08 2024-03-12 安徽科技学院 Liquid extrusion forming device for brittle solder strip
CN111916344A (en) * 2020-09-09 2020-11-10 合肥工业大学 Copper-copper low-temperature bonding method based on graphene/tin modified copper nanoparticles

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