JPH0447492B2 - - Google Patents
Info
- Publication number
- JPH0447492B2 JPH0447492B2 JP62075742A JP7574287A JPH0447492B2 JP H0447492 B2 JPH0447492 B2 JP H0447492B2 JP 62075742 A JP62075742 A JP 62075742A JP 7574287 A JP7574287 A JP 7574287A JP H0447492 B2 JPH0447492 B2 JP H0447492B2
- Authority
- JP
- Japan
- Prior art keywords
- signals
- binary
- configurable
- receiving
- output signal
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 238000003860 storage Methods 0.000 claims description 62
- 239000000872 buffer Substances 0.000 claims description 12
- 239000011159 matrix material Substances 0.000 claims 1
- 230000006870 function Effects 0.000 description 64
- 210000000352 storage cell Anatomy 0.000 description 8
- 238000003708 edge detection Methods 0.000 description 5
- 230000003068 static effect Effects 0.000 description 5
- 101100452680 Arabidopsis thaliana INVC gene Proteins 0.000 description 4
- 230000000630 rising effect Effects 0.000 description 4
- 101000998711 Homo sapiens Inversin Proteins 0.000 description 3
- 102100033257 Inversin Human genes 0.000 description 3
- 230000002457 bidirectional effect Effects 0.000 description 3
- 210000004027 cell Anatomy 0.000 description 3
- 238000010586 diagram Methods 0.000 description 3
- WABPQHHGFIMREM-IGMARMGPSA-N lead-207 Chemical compound [207Pb] WABPQHHGFIMREM-IGMARMGPSA-N 0.000 description 3
- 230000004044 response Effects 0.000 description 3
- 238000003491 array Methods 0.000 description 2
- 230000003213 activating effect Effects 0.000 description 1
- 230000008901 benefit Effects 0.000 description 1
- 230000008859 change Effects 0.000 description 1
- 238000004891 communication Methods 0.000 description 1
- 238000005520 cutting process Methods 0.000 description 1
- 230000001934 delay Effects 0.000 description 1
- 238000013461 design Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000004519 manufacturing process Methods 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000012544 monitoring process Methods 0.000 description 1
- 230000010355 oscillation Effects 0.000 description 1
- 230000008569 process Effects 0.000 description 1
- 239000004065 semiconductor Substances 0.000 description 1
- 230000001360 synchronised effect Effects 0.000 description 1
Landscapes
- Logic Circuits (AREA)
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US845287 | 1986-03-28 | ||
US06/845,287 US4758985A (en) | 1985-02-27 | 1986-03-28 | Microprocessor oriented configurable logic element |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS631114A JPS631114A (ja) | 1988-01-06 |
JPH0447492B2 true JPH0447492B2 (enrdf_load_stackoverflow) | 1992-08-04 |
Family
ID=25294868
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP62075742A Granted JPS631114A (ja) | 1986-03-28 | 1987-03-28 | 構成を変更可能な論理要素 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS631114A (enrdf_load_stackoverflow) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP2746502B2 (ja) * | 1992-08-20 | 1998-05-06 | 三菱電機株式会社 | 半導体集積回路装置の製造装置及び製造方法並びに電子回路装置 |
-
1987
- 1987-03-28 JP JP62075742A patent/JPS631114A/ja active Granted
Also Published As
Publication number | Publication date |
---|---|
JPS631114A (ja) | 1988-01-06 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US4758985A (en) | Microprocessor oriented configurable logic element | |
US4642487A (en) | Special interconnect for configurable logic array | |
USRE34363E (en) | Configurable electrical circuit having configurable logic elements and configurable interconnects | |
US4870302A (en) | Configurable electrical circuit having configurable logic elements and configurable interconnects | |
US5315178A (en) | IC which can be used as a programmable logic cell array or as a register file | |
US4442508A (en) | Storage cells for use in two conductor data column storage logic arrays | |
US4744061A (en) | Dynamic semiconductor memory device having a simultaneous test function for divided memory cell blocks | |
US6014038A (en) | Function block architecture for gate array | |
US6876228B2 (en) | Field programmable gate array | |
EP0204034B1 (en) | Configurable logic array | |
GB1573661A (en) | Digital logic circuit | |
JPH09198874A (ja) | ランダム・アクセス・メモリ・アレイ | |
GB2202355A (en) | Configurable storage circuit | |
JPH01137500A (ja) | 埋込み2進パターンを有するメモリ・アレイ装置 | |
JPH0447492B2 (enrdf_load_stackoverflow) | ||
US6567970B1 (en) | PLD configuration architecture | |
JPH07159498A (ja) | 構成制御システム、構成制御ユニット、fpgaを構成する方法、及び接続ライン上に存在するデータを受け取る方法 | |
CA1274882A (en) | Configurable electrical circuit having configurable logic elements and configurable interconnects | |
JPS61280120A (ja) | コンフイグラブルロジツクアレイ | |
CN116741230A (zh) | 可编程逻辑电路、动态改写可编程逻辑电路的方法和装置 | |
JPS63263943A (ja) | デ−タバス回路 | |
JPH09147597A (ja) | メモリ集積回路チップ、その製造方法及びその試験方法 | |
JPH0973787A (ja) | 半導体記憶装置 | |
JPS63108421A (ja) | プログラマブル論理クロックアーキテクチャ | |
JPS60153555A (ja) | 演算処理装置 |