JPH0447401A - Automatic controller - Google Patents

Abstract

PURPOSE:To change 'the number of control output' and/or the 'control accuracy' by switching whether a part of a comparison output by a comparison operation is outputted to a regular output port or an I/O port in accordance with a flag or not. CONSTITUTION:When a Q output terminal of a flip-flop 24 is '0', a multiplexer 25 outputs a signal on a signal 25-2 onto a signal line 25-3 and it is outputted to an output port 25-4 together with the signal on a signal line 26-3. Subsequently, when a CPU supplies a flag signal of '1' to a signal line 24-1 and supplies an electronic flash signal to a signal line 24-2, the Q output of the D flip-flop is inverted from '0' to '1', the multiplexer 25 outputs signal on a signal line 25-1 onto the signal line 25-3 and outputs it to the output port 25-4 together with the signal on the signal line 26-3. In such a way, the number of control outputs and/or the control accuracy can be changed, and this controller can be used to many applications.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an automatic control device used for controlling a power source, etc.

[Conventional technology]

FIG. 5 shows the block numbers of the entire conventional automatic control device.

This automatic control device is A/D (Analog-Digital)
mode as a converter and PWM (pulse width
There are two types of operating modes: th+*odulation) mode as a control circuit.

FIG. 7 is an example of a timing chart showing the timing of each block in FIG. 5, and FIG. 6 shows the configuration of the chopper type comparator 13 in FIG.

Timing is generated by a timing generator 6 to drive each block. The multiplexer (MPX circuit) 11 is switched so that the timing generator 6 manually inputs external detection data as a comparison value. Next, by turning on SWI and SW3 of the comparator 13 and turning off SW2, the input value selected by the multiplexer 11 is input to the comparator 13. At the same time, D/A conversion data is stored in RAM (random-access
memory) 8 from the D/A conversion table and set it in the D/A converter 12. Next, by turning on SW2 and turning off SWI and SW3, multiplexer 1
1 is compared with the D/A conversion value of the comparison standard, and the result is held in the latch 14. High precision control can be achieved by exchanging the timings of SWI and SW2.

In FIG. 5, the selector 7 selects the output of the normal arithmetic unit 5 manually and outputs it to the RAM 8. Sub PWM
The circuits 16, 17, and 18 are circuits that buffer and output the comparator results of the external detection data corresponding to the respective control terminals and the corresponding D/A conversion values as they are.

First, the operation as an A/D converter will be explained.

The input analog value selected by multiplexer 11 and the D/
The reference voltage from the A converter 12 is compared by the comparator 13, and based on this result, the next reference voltage to be compared with human power is determined by the calculator 5, and compared with the input analog value.

For such comparison, the reference voltage by the D/A converter 12 is
The arithmetic unit 5 determines the bits from the most significant bit to the least significant bit until it is closest to the human analog value, and when all bits are determined, it is latched in the register 3 as an A/D converted value.

Next, the operation as the PWMslIi1 circuit will be explained.

A comparator 13 compares the external input via the multiplexer 11 with the output of the D/A converter 12, which serves as a reference value.
The comparison result is held in latch 14. One of the outputs of the latch 14 is supplied to the main PWM circuit 15, and the others are taken out as sub-PWM outputs via an output buffer. Transfer of data between automatic control device and CPU.

This is done via each register 2, 3.4 (register A, register B, register C) in FIG. Register 2 is RA
This is a register for setting data on the D/A conversion table of M8, register 3 is a register for reading the result of A/D conversion onto CPU lot 1, and register 4 is a register for setting data on the A/D conversion table. - Status setting of D/A conversion operation, etc., RAM 8, multiplexer 11. This is a register for setting each address of the latch 14 and the like.

As described above, this automatic control device is a device having two types of operation modes: an operation mode as an A/D converter and an operation mode as a PWM control circuit.

FIG. 8 shows a block diagram of the main PWM circuit 15 of FIG. 5. In the front stage comparator circuit section, there is a multiplexer! 1 input to analog comparator 13 and DA converter 1
2, and the result is held in the latch 14. In the main PWM circuit 15, the result held in the latch 14 is transferred to the flip-flop 56.
Enter. The input comparison result of the comparator 13 is clock-synchronized by a flip-flop 56 and inputted to an up/down decision terminal of an up/down counter 58 at the next stage. At this time, the up/down counter 58 contains CP
Counter 58 from U bus 1 via 4-bit register 59
The initial value is manually set. The initial value is flip-flop 5
The count is counted up or down according to the up/down value of 6, and the counting result is sent to the up counter 61 at the next stage. The sent count value is read in synchronization with the load signal of the up counter 61,
Counting begins. The output signal of the up counter 61 is sent to the digital comparator 63, and the output signal is sent to the CPU buses 1 to 4.
It is compared with the value set in the bit register 64, and the comparison result is output as a PWM output. That is, while the output of the up counter 61 is smaller than the output of the register 64, the digital comparator 63 outputs a high level, and outputs a low level during other periods. In FIG. 8, the output of the up counter 61 is supplied to a seven-manufactured ant gate, which detects the end of counting, and its output is ORed with the output of the synchronous circuit by the OR circuit 60. is input to the load terminal of the rear counter 61, and the up counter 61 reads the data of the up/down counter 58 based on this signal. Here, the up/down counter 58, up counter 61, and digital comparator 63 are 7
The required accuracy is achieved through the bit configuration.

FIG. 9 is a diagram showing an example of a circuit in which the automatic control device shown in FIG. 5 is applied to power supply control.

In the figure, 66 is the output of the main PWM circuit 15, which drives the main transistor 67 and drives the transformer 72.
Drive the primary side of the secondary side output terminal? 3,74.7
6, the required output is obtained. The output of the output terminal 73, which is the first output, is voltage-divided and fed back as a signal 65 to become one input of the multiplexer 11. The low voltage side output terminal 75 of the second output is connected to the other terminal of the capacitor 82 which is grounded on one side, and the resistor 7 is connected on the other side to the collector of the sub-transistor 80.
It is connected to the other terminal of 9. The emitter of the sub-transistor 80 is connected to the other terminal of a resistor 81 whose one terminal is grounded.

Sub-PWM output 69 drives the base of sub-transistor 80 via resistor 77. The emitter of the sub-transistor 80, ie, the high side of the resistor 81, becomes one input of the multiplexer 11 as a feedback signal 71. Note that the feedback signals 65.71 are sent to multiplexers 11. The voltage is appropriately divided so that it falls within the operating range of the comparator 13, etc., and is pulled up to Vcc or pulled down to Gnd by an appropriate resistor depending on the polarity of the output terminals 73 and 74. 83 is a varistor and a current limiting resistor for protecting the sub-transistor 80 when the output terminal 75 rises excessively. The output of the output terminal 76, which is the third output, is controlled by another sub-PWM output 68 in a configuration similar to the circuit of the sub-transistor 80 described above.

The operation of the circuit shown in FIG. 9 will be described in detail below. In order to simplify the explanation, the comparator 13 will be explained as a normal analog comparator using an operational amplifier.

First, the timing generator 6 is connected to the multiplexer 11.
is driven to manually select the feedback signal 65 and input it to the comparator 13. At the same time, the selector 10 is driven to select the latch 9 (see FIG. 5), and the data in the latch 9 is read out and input to the D/A converter 12. The D/A converter 12 generates an analog voltage according to the human-powered digital data, and provides the other input to the comparator 13 . The comparator 13 compares the output of the multiplexer 11 and the output of the D/A converter 12 in the manner described above, and outputs a high signal when the output of 11>the output of 12, and a low signal when the opposite is true. At this time, the timing generator 6 supplies the latch 14 with a bit selection signal for controlling the main PWM circuit 15, and at the same time outputs a latch signal to latch the high/low output of the comparator 13. The output of the latch 14 is supplied as an input signal to the main PWM circuit 15 to the up/down decision terminal of the up/down counter in the main PWM circuit 15 as described above, and as a result, the main PWM circuit 15 is pulse width modulated.
The output 66 drives the main transistor 67 and controls the output of the output terminal 73 to a constant voltage. This is the main P
This is the operation of WM.

Next, the timing generator 6 drives the multiplexer 11 to select the feedback signal 71 as an input to the comparator 13 . At the same time, the selector 7 is driven to select the RAM 8, and the address storing the control setting value for the output of the output terminal 74 is given to the RAM 8, read out, and inputted to the D/A converter 12. 12 converts the digital input value into an analog voltage and inputs it to the other terminal of the comparator 13. The comparator 13 compares the two in the same way as described above, and depending on the magnitude thereof, generates a λ I/LOW signal, which is used as the manual power of the latch 14. The latch 14 corresponds to the sub-PWM output 69 based on the signal from the timing generator 6. Select bits to latch comparison results. The sub-PWM output 69 drives a sub-transistor 80 via a resistor 77 and a capacitor 78 that is grounded on one side, and performs the operation described below. This is the operation of sub-PWMO, that is, 5UBO.

Next, the main PWM operation described above is performed.

Furthermore, the timing generator 6 drives the multiplexer 11 to select the feedback signal 70 and inputs it to the comparator 13 . At the same time, the selector 10 is driven to select the RAM 8, and an address storing the control setting value for the output of the output terminal 76 is given to the RAM 8, read out, inputted to the D/A converter 12, and the D/A
The converter 12 converts the digital input value into an analog voltage and inputs it to the other terminal of the comparator 13.

The comparator 13 compares the two and generates a signal, which is input to the latch 14. The latch 14 selects and latches the bit corresponding to the sub-PWM output 68 based on the signal from the timing generator 6. Sub PWM output 6
8 drives sub-transistor 80-1, and performs the same operation as a circuit including sub-transistor 80, which will be described later.

This is the operation of sub-PWM1, that is, 5UBI.

Next, a main PWM operation is performed, and then the above-mentioned A/D conversion operation is performed. The above operations are considered as one cycle and repeat.

FIG. 14 shows a timing chart of the above operation. As mentioned above, MAIN4SUBO→MAIN→5
If UBI→MAIN4A/D is one cycle and this cycle is T, sub-PWM (SUBO,
5UBI) compares the control setting value and the output value (feedback signal) every cycle T and selects high/low.
It becomes a russian row. That is, it becomes a 1<) response string in which the high period is nT and the low period is mT (here, n and m are integers).

Now, the output of the output terminal 74 in FIG. 9 is stabilized as follows. A transformer 7 is connected between the output terminals 74 and 75.
Feedback signal 6 from output terminal 73 on the primary side of 2
5, a voltage that follows the output voltage of the output terminal 73 is generated. Assuming that the output of the output terminal 73 is now in a steady state, a certain voltage V is present between the output terminals 74 and 75. It has become. At this time, the output terminal 74
Figure 10 shows the main parts of the output control extracted and rewritten as an equivalent circuit. In Figure 10, output terminal 74-Gn
The output voltage between d is Vout, and the load impedance is RL.
I'll leave it aside.

With the configuration shown in the figure, all the current flowing through the load RL passes through the secondary winding of the transformer 72, and the sub-transistor 8
0. Since the voltage passes through the resistor 81, the voltage across the resistor 81 has a value proportional to the current flowing through the load RL. This value is signal 7
It is fed back as 1, compared with a reference value, and operates to become a pulse train of sub-PWM output 69. As a result, this circuit operates at a constant current.

The pulse train of the sub-PWM output 69 is converted into a DC voltage by a low-pass filter constituted by a resistor 77 and a capacitor 78. If this DC voltage is vd and the sub-transistor 8o is an ideal transistor, then the load R
, the current i flowing through.

can be expressed as io = (Vd VBE)/resistance value of the resistor 81.

Therefore, this circuit operates in the same way as a normal series regulator, and these operations are conceptually shown in FIG. 11. Note that in reality, ripples that cannot be removed by the low-pass filter are superimposed on vd, and io
will include ripple current. Therefore resistance 79
．． A stable output is achieved by smoothing with the filter of the capacitor 82.

Figure 12 shows a microcomputer (CPU), peripheral memory, timer, and other digital circuits, as well as the circuit in Figure 5, the aforementioned main PWM circuit, and three sub-PWM circuits.
An overall configuration diagram of a circuit and a controller integrated on the same chip is shown. This chip can perform most of the controls such as sequence control and power supply control for small, low-speed copying machines and printers, or else there may be a shortage of Ill PWM circuits.

The controller consists of a CPU core, data memory, program memory, interrupt control, etc.
PU37 section 87 and a reset function 83 including a standby function at low voltage in the periphery. Watch dog timer to monitor program runaway 84. A D/A converter 5 that performs digital-to-analog conversion based on CPU information, and an A/D conversion block and D/A conversion that function as an analog-to-digital converter by the D/A converter 5 and comparator circuit 13. D/A-A/D controller 85, which controls the A/D conversion block and each operation timing.
is placed.

In order to A/D convert a plurality of analog values, the A/D conversion block has a built-in multiplexer circuit 11 in the pre-A/D conversion stage that switches inputs according to the operation timing of the D/A/A/D controller 85. Ru.

A/D conversion is used to read various voltages such as a fixing thermistor of a copying machine and polyurethane for adjusting copy density. D/A
The converter is used for PW for fluorescent light dimming control, high voltage control, etc. of copying machines.
It is used as a reference voltage for the comparators of M circuits 15 to 18.

The development AC bias drive pulse generator includes a 4-bit frequency divider 86 to divide the CPU internal clock, and a development AC bias drive pulse generator.
A 1/2 frequency divider 82 is used to set the duty of the C bias drive pulse to 50%.

As mentioned above, the PWM circuits 15 to 18 are used for fluorescent lamp dimming control, high-voltage power supply, and low-voltage power supply control, but the main PWM circuit 15 with a digital 7-bit configuration is used to control the low-voltage power supply.
For other controls, a sub-PW configured such that the output result of the comparator 13 directly becomes the PWM output is used.
M circuits 16 to 18 are used. In addition, P of low voltage power supply control
The WM circuit 15 has a PWM output instantaneous shutdown function in the event of a power failure.The manual power consists of a comparator, and when a certain specified value is exceeded, the PWM output is immediately turned off to protect the circuit and ensure the safety of the copying machine. It enhances sexuality.

The controller also has an input port 92 for inputting various sensor information, key switch information for the operation section such as copy start, setting the number of copies, etc., and an output port 91 for controlling motors, heaters, solenoids, etc.
, an output port 89 for a display LED drive, etc.

In addition, a checker is connected to the main body of the machine to check the operation of the copying machine in factories, markets, etc., and it also has a serial communication port 90 for this purpose, as shown in Figure 12. c, NT85 is the timing generator 6° RAM8. Selector 7, arithmetic unit 5. Contains registers 2-4.

The CPU sets data in each block to control each output of the main PWM and sub-PWM, for example as shown below. Register 2 shown in FIG. Register 3. Register 4, also the 4-bit register 59, 4 shown in FIG.
The bit registers 64 are each given an independent address in the case of the memory processor I10, and the bit registers 64 are each given an independent address in the case of the memory processor I10.
Similarly, in the case of 0, an independent port number is assigned to each port.

Since the 4-bit registers 59 and 64 can be set independently, the CPU specifies parameters that define the operation of the main PWM by addressing each register and setting predetermined values.

Further, the RAM 8 that stores D/A conversion values, that is, the setting values of each sub PWM and A/D conversion data, is composed of, for example, a shift register, and the setting value of the main PWM is stored in a latch 9, as shown below. It communicates with the CPU in various ways. First, FIG. 13 shows the bit configuration of register 4 (see FIG. 5).

Bits 0 to 3 are the designation No. of RAM 8 or latch 9 in FIG. 5, or designation No. 1 of multiplexer 11, and bit 4 is the designation of Read or WRITE. When Read, it is the 8 channel of multiplexer 11 to be A/D converted. One of the inputs is indicated by the value of RAM No. (bits 0 to 3) and stored in a latch in the timing generator 6. Also, when WRITE, the address or latch 9 in RAMB to be D/A converted is set to RAMNo, (bits 0 to
3). Bit 5 is main PWM, sub PWM
Bit 7 specifies whether to output each output of the CPU.
For example, when bit 7 is changed from 0 to 1, bit 0
~5 data and register 2 data become valid. In addition, in the bit configuration, RAM No. is bit O~
3, 4 bits are allocated, but in this circuit, RAM
8 has 5 types and 8 external input channels, so 3 bits is actually sufficient.

The output value of each PWM is set in the RAM 8 or latch 9 by the following procedure. The CPU first addresses register 2 and writes the PWM control data to be set. Next, address register 4 and bits 0 to
The RAM number of the output you want to set to 3, for example 09SUB for main PWM, 1 for PWMO, and set bit 4 to WRITE state and bit 7 to 0.
Set it to 1 and write it. If main PWM is specified,
In other words, when the setting is 0, the timing generator 6 sets the input of the selector 7 to the register 2 side, sets the output to the latch 9 side, and also outputs a latch pulse to the latch 9 to capture the value of the register 2 into the latch 9. . After that, set the selector 7 to the RAMa side. In this circuit, RAM8 is
Since the shift register configuration is adopted as described above, the timing generator 6 uses the RAM N of the register 4.
o, and the corresponding RAM No.

At the same time as the data is output to the D/A converter 12, the selector 7, which normally selects the arithmetic unit 5, is set to the register 2 side, and the data in the register 2 is written into the RAM 8 by the next shift clock. The selector 7 again selects the data on the arithmetic unit 5 side when the aforementioned shift clock goes down.

Here, the arithmetic unit 5 outputs the input, ie, the output of the RAM 8, as it is, and uses it as an input to the selector 7.

As described above, the set value of each PWM output can be set in RAMa. It should be noted that when setting the data of the main PWM described above, it is limited to the case where the shift clock of the RAM 8 is not valid. Also, to set the A/D conversion address, C
The PU addresses register 4 and sets the channel number (0 to 7) for A/D conversion to 0 to 3 (actually 0 to 7).
2), set bit 4 to read, set bit 7 to 0 or 61, and write, the values of bits 0 to 3 of register 4 are set in the latch in timing generator 6. The timing generator 6 supplies the latched channel number to the multiplexer 11 at the timing for A/D conversion. At this time, the arithmetic unit 5 changes the bit data determined by the comparator result from 0 to 1 and outputs it to the selector 7.

The arithmetic unit 5 sequentially sets 1 from the most significant bit, repeats the above-mentioned comparison operation, and rewrites the data in the RAM 8 until the least significant bit is determined. Then, when the least significant bit is determined, the timing generator 6 gives a latch pulse to the register 3, stores the data from the arithmetic unit 5 in the register 3 as A/D conversion data, and performs the comparison operation again starting from the most significant bit. The computing unit 5 is
Only the most significant bit is set to 1, the other bits are set to 0, and the data is written into the RAM 8 through the selector 7.

The CPU reads A/D by addressing and reading register 3.
You can know the conversion value.

(Problems to be Solved by the Invention) As explained above, in the conventional example, the control of a high-precision PWM circuit (main PWM) using an up-down counter is difficult as shown in FIGS. 14 and 15, for example. The number of comparisons per unit time required for controlling each of the other control circuits, that is, the number of comparisons three to four times as dense as the comparison frequency, was assigned to each of the other control circuits.

Furthermore, the timing of these comparison controls is uniquely determined and cannot be changed. As a result, the following problems occurred.

a. When controlling a controlled object that does not require high-precision control, the above-described high-precision control becomes wasteful.

b. In the conventional case, when it is desired to increase the number of controlled objects, the comparator timing required for control is insufficient.

c. Depending on the application, main PWM is not necessary, and sub-PWM is required.
In such cases, there is no flexibility in switching the PWM circuit.

The present invention has been made in view of these circumstances, and is
The object of the present invention is to provide an automatic control device that can change the number of control outputs and/or control accuracy.

[Means to solve the problem]

In order to achieve the above object, the automatic control device of the present invention is configured as shown in (1) to (4) below.

(1) An automatic control device equipped with the following components a''-c.

a. Comparison means for comparing an input signal and a reference signal corresponding to the input signal.

b. Timing means for causing the comparison operation of the comparison means to be executed in a time-sharing manner.

c. A switching means for switching whether or not to output a part of the comparison output from the comparison operation to the normal output port or the I10 port, depending on a flag.

(2) Automatic control device equipped with components a to c.

a. Comparison means for comparing an input signal and a reference signal corresponding to the input signal.

b. Timing means for causing the comparison operation of the record comparison means to be executed in a time-sharing manner.

c. Switching the type of signals compared by the comparison means to a combination of a first type with a high comparison frequency and a second type with a low comparison frequency, or a combination of the second types, depending on a flag. means.

(3) An automatic control device equipped with the components a''-'c.

a. Comparison means for comparing an input signal and a reference signal corresponding to the input signal.

b. Timing means for causing the comparison operation of the comparison means to be executed in a time-sharing manner.

C2 Changing means for arbitrarily changing the comparison frequency of the first type signal and the comparison frequency of the second type signal compared by the comparison means, depending on the flag.

(4) An automatic control device that integrates at least a CPU, a memory D/A converter, a comparator, a selector, and a latch on one chip, the memory being capable of changing the number of channels for A/D conversion and automatic control. An automatic control device in which a program for switching the time ratio of time division allocated to each channel is stored.

[Operation] According to the configurations (2) and (4) above, the number of control outputs can be controlled, and according to the configurations (1), (3), and (4) above, all constraints can be changed.

〔Example〕

The present invention will be explained in detail below with reference to Examples.

FIG. 1 is a block diagram of an "automatic control device" which is a first embodiment of the present invention. The same reference numerals are given to the parts corresponding to the conventional example in FIG. 5, and the explanation here will be omitted.

The parts added to FIG. 5 will be explained. , 24
is a control flag and is composed of a D flip-flop. Pass the signal line 24-1 to the D input terminal.
A flag set signal is manually inputted from the PU, and a flag strobe signal is inputted from the CPU to its clock input terminal through a signal line 24-2. Its Q output terminal is connected to the control signal input terminal of multiplexer 25 through signal line 24-3. One input terminal of this multiplexer 25 is connected to a signal line 25-- which is connected to the up/down decision terminal of the up/down counter of the main PWM circuit 15 at the output of the latch 14.
1 is connected, and the other input terminal stores data for outputting normal digital data to the output port.
The signal line 25-2 of one of the nozzle lines 26-2 connected to the output terminal of the output latch 26 is connected. The output line 25-3 of the multiplexer 25 is
The output port 25 along with the other three signal lines 26-3 on the line 26-2 does not pass through the multiplexer 25.
-4.

Next, the operation will be explained. When the Q output terminal of the flip-flop 24, which is a flag, is 0, the multiplexer 2
5 operates to output the signals on the signal lines 25-2 onto the signal line 25-3, and output the signals on the signal line 26-3 to the output port 25-4. Next, the CPU connects signal line 2
When a flag signal of 1 is applied to signal line 24-1 and a strobe signal is applied to signal line 24-2, the Q output of D flip-flop 24 is inverted from 0 to 1, and multiplexer 25 outputs the signal on signal line 25-1. operates to output on the signal line 25-3, and outputs the output port 25 along with the signal on the signal @26-3.
-4 is output. Other operations are the same as the conventional example shown in FIG.

As explained above, according to this embodiment, the main PWM
Since it is possible to directly output the up/down data to 15 via the port, the following advantages arise.

a. The control status during main PWM control can be checked from the port, and abnormal conditions etc. can be determined. Also, the status can be easily determined during testing.

b. When PWM control with constant off time or on time is not required and on/off control is effective control, uptown data can be used as control data for the on/off control.

FIG. 2 is a block diagram of an "automatic control device" which is a second embodiment of the present invention. In the figure, 28-1 are four input terminals of a digital signal/analog signal port. The analog signal input to the input terminal 28-1 is 27
It is supplied to the input terminal of the analog switch of 28 and the waveform shaping circuit of 28. The control signal input terminal of the analog switch 27 is connected to the Q signal of the flag 24 via the signal line 24-3.
connected to the output terminal. The explanation of the flag 24 is as follows.
Since this is the same as the embodiment, the description will be omitted. The output terminal group of the analog switch 27 is connected to the lot line 1 via the pass line 27-2.
1-1 to the signal input terminal of the multiplexer 11. The output terminal of the waveform shaping circuit 28 is connected to the input terminal of the latch 29. The output terminal of the latch 29 is connected to the CPU bus 1. The latch 29 is
A control signal is input to the control signal input terminal through the signal line 29-1. When the signal is low, the output becomes high impedance, and when it is high, the input signal is latched and the digital signal at the input terminal 28-1 is output onto the CPU bus 1. Now, the Q output terminal of the flag 24 is further connected to the control signal input terminal of the multiplexer 11 and the latch 14 in the first embodiment via the signal line 24-3, and is also connected to the control signal input terminal of the multiplexer 25 and the timing generator 6. It is also connected to the input terminal. The number of latches 14 is increased from five in the conventional example to nine, and the output terminals of the four additional latches are connected to one input terminal group of the multiplexer 25 via a pass line 14-5). .

When the Q output of the flag 24 is 1, the latch output terminals 14-1 to 14-4 of the latch 14 are connected to the output port 25-4 via the multiplexer 25. Flag 24 Q
When the output is 0, the output port 25-4 is connected to the signal line 26-2.
It is connected to the output terminal of the output latch 26 via. C.P.
The U bus 1 is connected to the input terminal of the output latch 26 through the bus 26-1, and the output latch 26 serves as a buffer for the output port 25-4.

The input terminals of all the latches 14, including the added latches, are connected to signal lines to which conventional input terminals were connected. Further, the RAM 8 is a 7-bit×8 RAM. RAM
The control timing is assumed to be performed by the timing generator 6 by extending the conventional method.

Next, the operation will be explained. When the Q output of the flag 24 is O, the operation is the same as that of the conventional example shown in FIG. 5, except for the operation of the added port. In that case, 5 person Kaport 28-1
acts as a digital router, and its input signal is shaped by a waveform shaping circuit 28 and inputted to a latch 29 as a digital signal. and port control signal line 29
When a signal of 1 is added to -1, the digital data latched by the latch 29 is transferred onto the CPU bus 1. The multiplexer 25 operates to output the signal on the signal bus 26-2 to the output port 25-4 (even if the I/O port is set as an output port) through the signal bus 25-3. The normal port output function of outputting the data set in the latch 26 onto the output port 25-4 operates.

Next, the operation when the Q output terminal of the flag 24 is 1 will be explained. First, the analog signal applied to the input terminal 28-1 is sent to the analog bus 2 through the analog switch 27.
7-2, 12 channels of analog bus 1
1-1 to the input terminal of the multiplexer 11, while the outputs of the four additional latches of the latch 14 are supplied to the input terminals of the multiplexer 11 via the pass lines 14-5. A circuit is configured that can output digital data to the output port 25-4 through the multiplexer 25.

In the conventional example shown in FIG. 9, sub-PWM control is performed using two circuits, but in this embodiment, sub-PWM control is extended to three circuits as in the conventional example shown in FIG. , the configuration is such that it can be expanded by flag control for four more circuits.

In order to input the additional comparison data, the RAM 8, which had a conventional 7-bit x 4 configuration, was changed to a 7-bit x 8 configuration. Data setting may be performed in the same manner as in the conventional example.

That is, by using the 4 bits θ to 3 of register 4, 16 RAM addresses are possible. So, allocate 8 addresses, for example from 0 to 7. Then, control data corresponding to each input is written to the corresponding address of the RAM 8. The feedback signal applied to the input terminal 28-1 is applied to the signal line 28-1-1.
-4 signals are sequentially compared with the corresponding comparison data on the RAM 5. In other words, the selector 10 also uses the RAM at the select timing of the latch 9 in the conventional example.
It remains connected to the output terminal of 8, and in synchronization with the timing, the signal line 28-1-1.28-1-2.28-
The timing generator 6 is connected to the selector 10 . Controls RAM8.

At the same time, the multiplexer 11 also connects its respective input terminal of the feedback signal to be controlled or the SW of the comparator 13.
It is controlled to connect to the I side terminal. The output data of the latch 14 is sequentially changed based on the comparison result. That is, the comparison result of the feedback signal of the signal @2B-1-1 is output to the output terminal 14-1 of the latch 14,
Signal line 14-5. It passes through the multiplexer 25 and is output to the first bit of the output port 25-4. Similarly, the comparison result of the feedback signals on the signal line 28-1-2 is output to the output terminal 14-2 of the latch 14, and the result is output to the output terminal 14-2 of the latch 14, and
．． 2 of output port 25-4 through multiplexer 25.
The bit is output. Similarly, the comparison result of the feedback signals on the signal line 2B-1-3 is output to the third bit of the output port 25-4. Similarly, the comparison result of the feedback signal of the signal line 28-1-4 is the output port 25-4.
The 4th bit is output.

In this way, the data set in the RAM 8, the human port, and the output port.

It can be expanded by using the port 28-1, which was used as an I/O port, and setting a flag for the PWM control circuit (corresponding to SUBPWM).

The comparator 130 control timing is the same as in the conventional example. FIG. 15 shows a comparator time chart in a conventional example using three sub-PWM circuits. A similar time chart of this embodiment is shown in FIG. In FIG. 16, 5UBOA.

5UBIA, 5UB2A, and 5UB3A indicate control timings of the comparators 13 corresponding to the added sub-PWM circuits, which use the output data of the output terminals 14-1 to 14-4 of the latch 14 as comparison control data, respectively.

As explained above, according to this embodiment, instead of outputting to the main PWM circuit 15, a PWM circuit that can perform the same control as the output to the existing sub-PWM circuits 16, 17 and 18 is provided according to the flag 24. Since the output can be expanded by four circuits, it can be applied to power supply control with many control circuits. In addition, the device of this embodiment can be operated by a CPU like the controller shown in FIG.
An IC integrated on a single chip with other components increases the number of uses and reduces costs due to mass production effects.

FIG. 3 is a block diagram of an "automatic control device" which is a third embodiment of the present invention. This embodiment has a timing change flag 3 of the timing generator 6 in addition to the second embodiment.
0 is added.

Hereinafter, only the parts different from the second embodiment will be explained, and the explanation of other parts will be omitted. A flag control signal line 30-1 is connected to the D input terminal of the flag 30, and a flag strobe signal line 30-2 containing the address of the flag is connected to the clock input terminal. Further, the Q output terminal is connected to a timing change control signal input terminal of the timing generator 6 via a signal line 30-3.

Next, the operation will be explained. The flag 3o is set by placing set data on the CPU or signal line 30-1 (g segment line 30-1).
21: is controlled by adding a strobe signal to.

When the cPU sets flag 3o to 0, the automatic control device operates as in the second embodiment. CPU or flag 3o
When set to 1, the timing generator 6 can change the timing shown in FIG. 16 to the timing shown in FIG. 17. That is, sub PWM circuit 5UBIA
, the timing generated by the timing generator 6 is changed so that the timing to control 5UB3A can be the timing to control the main PWM circuit 15, and the output of the latch 9 or D/A conversion is changed at the timing when the selector 10 controls 5LIBIA and 5UB3A. The feedback data of the main PWM circuit 15 can be selected by the multiplexer 11 at that timing. In addition, the latch 14 also transmits the comparator result of the converter 13 at that timing to the main PWM circuit 1.
5. It is assumed that a signal that can be latched into the control latch is input from the timing generator 6. It is assumed that the basic sequence of individual blocks is shown in FIG. 7 as in the conventional example.

As explained above, this embodiment is effective when it is desired to increase the number of sub-PWM circuits even if the control frequency of the main PWM circuit 15 is lowered.

FIG. 4 shows an "automatic control device" which is a fourth embodiment of the present invention.
FIG. This embodiment is obtained by adding a variable clock signal generation circuit 32 and an anchor 31 to the third embodiment.

An output terminal of the AND gate 31 is connected to a timing change control signal input terminal of the timing generator 6 via a signal line 31-1. One input terminal of the AND gate 31 is connected to the Q output terminal of the D flip-flop which is the flag 30 via the signal line 30-3, and the other input terminal is connected to the variable clock signal generation circuit via the signal line 32-2. 32 output terminals. It is assumed that the variable clock signal generation circuit 32 can be programmed by the CPU to change the waveform necessary for control and output it to the signal line 32-2. The variable clock signal generation circuit 32 also has c.
It has a pu bus signal input terminal 32-1 and is connected to the CPU bus.

Next, the operation will be explained. When the Q output of the flag 30 is 0, the same operation as in the second embodiment is performed.

When the flag 30 outputs an output of 1 and the variable clock signal generation circuit 32 outputs an output signal of 1 to the AND gate 31, the same operation as in the third embodiment is performed. Next, CP
Assume that U outputs a clock signal having a period T and a duty of 50% as shown in FIG. 18 onto the signal line 32-2. In this case, the output signal of the timing generator 6 changes the control state from the state shown in the time chart shown in FIG. 16 to the state shown in the time chart shown in FIG. 17 in the middle of the period T. This reduces the control accuracy of the main PWM,
It becomes possible to increase the number of circuits that control sub-PWM. This is control at the timing shown in FIG. By changing the phase of the clock as shown in Figure 20,
It also becomes possible to control the timing shown in the figure. Further, the control timing of the flag 30 and the variable clock generation circuit 32 can be freely changed according to the human power conditions from the CPU. Therefore, the output of flag 30 is 0.
16, the output of the flag 30 is 1.
When the output of the variable clock generation circuit 32 is 1, the timing shown in FIG. 17 is obtained, and when the flag 30 is 1, the timing shown in FIG. 19 or 21 is obtained depending on the output phase of the variable clock generation circuit 32.

In this way, according to this embodiment, the control precision of the main PWM and sub-PWM can be controlled arbitrarily, and the control accuracy of the sub-PWM
The number of circuits can also be increased similarly to the second or third embodiment.

〔Effect of the invention〕

As explained above, according to the present invention, the number of control outputs and/or control accuracy can be changed, making it possible to apply it to various purposes.
Since an LSI integrated with a CPU and the like on one chip can be used on the same chip without changing the circuit, cost reduction can be expected due to mass production effects.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a first embodiment of the present invention, FIG. 2 is a block diagram of a second embodiment of the present invention, and FIG. 3 is a block diagram of a third embodiment of the present invention.
4 is a block diagram of the fourth embodiment of the present invention, FIG. 5 is a block diagram of the entire conventional automatic control device, FIG. 6 is a circuit diagram of the chopper type comparator of FIG. 5, Figure 7 is a timing chart of each part in Figure 5, Figure 8 is a block diagram of the main PWM, Figure 9 is a diagram showing an example of a circuit in which the device in Figure 5 is applied to power supply control, Figures 10 and 11.
The figure is an explanatory diagram of the operation of the circuit in Figure 9, Figure 12 is an overall configuration diagram of the controller, Figure 13 is a diagram showing the bit configuration of register 4, and Figure 14 is a diagram showing the timing of the comparator in the circuit shown in Figure 9. Figure 15 is a diagram showing the timing of the comparator in the conventional example shown in Figure 5.
6 is a diagram showing an example of the timing of the comparator in the second embodiment, FIG. 17 is a diagram showing an example of the timing of the comparator in the third embodiment, and FIG. 18 is a diagram showing an example of the timing of the comparator in the fourth embodiment. 19 is a diagram showing an example of the output of the circuit 32, FIG. 19 is a diagram showing the timing of the comparator according to the example of FIG. 18, FIG. 20 is a diagram showing another example of the output of the variable clock signal generation circuit, and FIG. 20 is a diagram showing the timing of the comparator according to the example of FIG. 20. FIG. 6・・・・Timing generator 13=−−−・
Comparator 24... Flag 25... Multiplexer

Claims (4)

[Claims] (1) An automatic control device characterized by comprising the following components a to c. a. Comparison means for comparing an input signal and a reference signal corresponding to the input signal. b. Timing means for causing the comparison operation of the comparison means to be executed in a time-sharing manner. c. A switching means for switching whether or not to output a part of the comparison output from the comparison operation to a normal output port or an I/O port, depending on a flag. (2) An automatic control device characterized by comprising the following components a to c. a. Comparison means for comparing an input signal and a reference signal corresponding to the input signal. b. Timing means for causing the comparison operation of the comparison means to be executed in a time-sharing manner. c. Switching the type of signals compared by the comparison means to a combination of a first type with a high comparison frequency and a second type with a low comparison frequency, or a combination of the second types, depending on a flag. means. (3) An automatic control device characterized by comprising the following components a to c. a. Comparison means for comparing an input signal and a reference signal corresponding to the input signal. b. Timing means for causing the comparison operation of the comparison means to be executed in a time-sharing manner. c. Changing means for arbitrarily changing the comparison frequency of the first type signal and the comparison frequency of the second type signal compared by the comparison means, depending on the flag. (4) At least a CPU, memory, and D/A on one chip
An automatic control device that integrates a converter, a comparator, a selector, and a latch, wherein the memory stores a program for changing the number of channels for A/D conversion and automatic control, and a program for switching the time ratio of time division allocated to each channel. An automatic control device characterized by being memorized.