JPH04186927A - A/d converter - Google Patents

Abstract

PURPOSE:To preserve the past A/D conversion result so that it can be referred to easily by writing the A/D conversion result in the storing means of an address corresponding to an A/D conversion channel with a writing means. CONSTITUTION:The contents of a latch 34 are sent out to a data bus by a fact that an A/D register selecting signal obtained by decoding an address sent out of a CPU side becomes active, and read in the CPU. In this regard, when a channel switching signal is inputted to the clock input terminal of a 1-clock D-dlip-flop 1-1 in order to change the selection of the latch, the signal of a Q output terminal of the D-flip-flop 1-1 is varied from '0' to '1', initial input is inputted to an initial circuit 32 through the OR gate of an initial signal generating circuit 1--30, and the restart of A/D conversion is applied. Subsequently, by the next timing, the A/D conversion is started, the R terminal of the D-flip-flop 1-1 goes to '1', and the D-flip-flop 1-1 is reset.

Description

[Detailed description of the invention] [Industrial application field] The present invention relates to an AD conversion device.

[Conventional technology] FIG. 5 shows a conventional AD conversion device.

In the figure, 21 to 24 are latches, for example, the main P
The digital reference voltages of the outputs to be subjected to WM control, sub (1) PWM control, sub (2) PWM control, and sub (3) PWM control are each latched. latch 21
-24 output stages have a 3-state configuration. 4 is D
/A converter ([1/A), which converts the digital reference voltage from latches 21 to 24 into an analog reference voltage. 8 is a multiplexer (MPX), which switches channels on a time-sharing basis. be. The MPX 8 is input with signals to be A/D converted from the fixing thermistor, density adjustment volume, etc., and feedback signals from outputs of the low voltage, high voltage power source, etc. to be PWM controlled. A comparator 5 compares the signal from the MPX8 with the analog reference voltage from the D/A4. Reference numeral 7 denotes a register for storing the comparison result of the controller 5.

56 is an A/D conversion control section, the configuration of which is shown in FIG.

25 is a timing controller, and latches 21 to 24.
Register 7゜MPX8. It controls the timing of the A/D conversion control section 56.

Next, the operation will be explained.

This is a comparison of main PWM control data by comparator 5 - sub (11) by comparator 5 - comparison of PWM control data → comparison of main PWM control data by comparator 5 → sub (2) by comparator 5 I'1
Comparison of 11M control data - Comparison of main PWM control data by comparator 5 - Sub (
3) Comparison of PWM control data - In this example, one cycle is defined as 1-bit A/D conversion by the controller 5, and this cycle is repeated. The timing around the comparator is shown in FIG. 7, and the timing of the controller 5 is shown in FIG.

Here, comparison of main PWM control data by comparator 5, comparison of sub (1) PWM control data by comparator 5, comparison of sub (2) PWM control data by comparator 5,
Comparison of control data, sub (3) P by comparator 5
Since comparison of WM control data is essentially the same operation, the comparison operation of main PWM control data by comparator 5 will be explained.

The latch 21 is selected by the timing controller 25, and the digital reference voltage for main PWM is converted into an analog reference voltage by the D/A converter 4. At the same time, the feedback signal input terminal of the main PWM output is selected by MPX8. Then, the analog reference voltage and the output of MPX8 are compared by a comparator 5, and as a result of the comparison, if the output of MPX8 is larger, a high level signal is output, and if it is smaller, a low level signal is output, and the register 7 is input. Next, after waiting until the output of the comparator 5 becomes sufficiently stable, the timing controller 25 selects 1 bit of the latch 7 corresponding to the main PWM and latches the comparison result.

Next, the 7-bit precision A/D conversion operation by the comparator 5 will be explained.

FIG. 6 shows the configuration of the A/D conversion control section 56 shown in the fifth figure.

When the initial signal generation circuit 35 operates.

The initial circuit 32 operates, and the value '1oooooo'B is output to the latch 33. At this point, the latch enable signal becomes high level, and the latch 33 receives '100'.
The value of 0000°B is loaded, the latch enable signal goes low, and the loaded value becomes latched. In this state, when an A/D cycle comes, the A/D selection signal is set to high level by the timing controller 25, the 3-state buffer of the latch 33 is turned on, and the contents of the latch 33, that is, '1000000°B D
/A data bus, and at the same time, latch 30 is enabled and '1000000'B is loaded into latch 30. This value is also sent to D/A converter 4, D/^ converted, and D/A. The A-converted analog voltage is input to one terminal of the comparator 5. At this time, the MPX
8 selects one of the analog inputs to be A/D converted and inputs it to the other terminal of the comparator 5.

The comparison result of the comparator 5 outputs "1" when the analog input is higher than the D/A conversion value, and outputs "0" when it is lower, and is input to the arithmetic unit 31 of the A/D conversion control unit 6 through the register 7. be done. The arithmetic unit 31 reflects the comparison result on the least significant bit of the bits set to "l" among the inputs, that is, the output of the latch 30, and outputs it as new data. At the same time, the next lowest bit of the bits set to "l", that is, bit 5, is forced to "l" and output as new data, and the remaining bits are inputted. Output as new data as is (LSB is bitO).

That is, in this case, the output of latch 3o is °10000
00°B, the computing unit 31 converts the comparator result into M
It is reflected in the SB, and when the comparator result is high, it generates "1" and when it is low, it generates "0" as the MSB. Furthermore, since the input of the arithmetic unit 31 is °1000000 °B, M
In order to forcibly set the next bit of SB to ``L'', new data is generated as new data, TE'X, 100000°B (X is ``1'' or ``0'' determined by the comparison result). At this time, the initial signal generation circuit 35 does not operate, so the initial circuit 32 also does not operate, and the output of the arithmetic unit 31 is sent to the latch 33 as it is.
The latch enable signal generated when the output of the comparator 5 becomes sufficiently stable becomes high and is loaded into the latch 33, and further, when the latch enable signal becomes low, it is latched.

Thereafter, essentially the same operation as described above is repeated until bito occurs every A/D cycle, and bito
When the bits up to
4 is loaded. All bits are determined by latch 30 bi.
Since the output of to is "l", the A of the latch enable pulse generated when the comparison result of bito is stable is
It can be determined by ND. Also, bit O of latch 30 is “
1'', that is, when the all-bit comparison operation completion flag for A/D conversion is set, the initial signal generation circuit 35 restarts the A/D conversion operation starting from the highest bit in the next A/D cycle. The initial circuit 32 is activated.

The initial circuit 32 outputs °1000000'B,
The latch enable signal loads the latch 33.

[Problems to be Solved by the Invention] However, in the above conventional example, the comparison time of the comparator is 8 μSec for one channel, so
If channels are allocated fairly in a time-divided manner and comparison judgment is controlled, the comparison time for that period will be 64 μsec, and 7
The conversion time for each bit AD conversion is 448 μsec. Therefore, there were the following problems (1) to (3).

(1) Even when the channel for AD conversion is switched, the AD conversion of the previous channel is still being executed, and the waiting time of the CPU (not shown) before actually obtaining the necessary AD conversion result is long.

(2) When switching channels, past AD conversion results may disappear or accurate values may not be obtained.

(3) When a CPU (not shown) accesses the A/D conversion results, it is unclear whether the A/D conversion results are being determined.

An object of the present invention is to provide an AD conversion device that solves the above problems.

[Means for Solving the Problems] In order to achieve such an object, the present invention provides a chopper type comparator, a digital reference voltage for time-division comparison with a multi-channel input by the chopper type comparator, In an AD converter having a digital reference voltage for successively AD converting analog data of an AD conversion channel among inputs, and a DA converter for DA converting the analog data, the number of storage means is the same as that of the AD conversion channels; The present invention is characterized by comprising a write means for writing an AD conversion result into a storage means for an address corresponding to the AD conversion channel.

[Function] In the present invention, the AD conversion result is written by the writing means into the storage means of the address corresponding to the AD conversion channel among the storage means of the same number as the AD conversion channels.

[Example] Hereinafter, an example of the present invention will be described in detail with reference to the drawings.

FIG. 1 shows an embodiment of the invention. This is an example applied to a copying machine.

The same parts as in Fig. 5 are given the same reference numerals and explanations are omitted.
In the figure, l is a CPU core section, which includes data memory, program memory, and the like. 2 is a reset circuit. 3
is a watchdog timer that monitors runaway programs. Reference numeral 9 denotes a power supply abnormality detection unit that detects an abnormality in a low-voltage power supply (not shown). 10 is main PWM
Based on the main PWM data latched in the register 7, the low voltage power supply (not shown) is PWM controlled.

The main PWMIO has a PWM output instantaneous shutdown function in the event of a power failure.The input consists of a comparator, and when a certain specified value is exceeded, the PWM output is immediately turned off to protect the circuit and increase the safety of the copier. )ru, 11
is a sub(1) PIIIM, which performs PWM control of a DC power supply (not shown) based on sub(1) PIIIM data. 12 is sub(2) PWM, sub(2) PII
It performs PWM control of high voltage based on IM data.

13 is sub(3)P! The IM performs PWM control on a fluorescent lamp (not shown) based on sub-(3) PWM data to dim it. 15 is a 4-bit frequency divider that divides the frequency of the CPU internal clock. Reference numeral 14 denotes a 1/2 frequency divider, which divides the signal from the 4-bit frequency divider 15 by 1/2 to make the developing AC bias drive pulse have a duty of 50%. 18 is a serial I10% 19 is an LED driver. The drive pulse generator for development AC bias is 4b.
It frequency divider 15 and 1/2 frequency divider 14 are used. 6 is an A/D conversion control section, the configuration of which is shown in FIG.

D/A converter4. Comparator 5. A/D conversion control section 6
．． The register 7, MPX 8, and timing controller 25 constitute a successive approximation type AD converter. This A/D converter is used to read various voltages of a fixing thermistor, copy density adjusting volume, etc. of a copying machine.

As a port for the control controller, there is an input boat for inputting various sensor inputs and operation key switch information such as copy start, copy number setting, etc., an output boat for controlling motors, heaters, solenoids, etc. 9 output boats for displaying LED drives It has a serial communication board for a checker that is connected to the main body to check the operation of the copying machine at factories, markets, etc.

In FIG. 3, 30 to 33 indicate the same parts as in FIG. 6. 1-41 is an OR gate that performs an OR operation on the signal from the C3 terminal of the latch 33 and the channel switching signal. The output signal of OR gate 1-41 is input to the G terminal of latch 30. 1-1 is a D flip-flop,
A channel switching signal is input to the clock input terminal through the signal line 12, and its output is input to the D terminal. The D flip-flop 1-1 is configured such that the levels of the Q and Q terminals change in synchronization with the falling edge of the clock signal. 1-30 is an initial signal generation circuit, A
Consists of ND gate and OR gate, negative logic input A
The ND gate performs an AND operation on the negative logic output of the latch 30, and the OR gate performs an AND operation on the output signal of the AND gate,
LSB signal of latch 30 and D flip-flop 1-1
This is to perform an OR operation with the signal from the Q terminal of . The output of the initial signal generation circuit 1-30 is the initial circuit 3
2 is entered. 1-44 is an AND gate that ANDs the LSB signal of latch 30 and the latch enable signal.
It is a calculation.

1-5 to 1-12 are latches, and each latch has an arithmetic unit 31.
The output of A is input to the C3 terminal of each latch.
The outputs of ND gates 1-13 to 1-20 are input, and the outputs of gates 1-33 to 1-40 are input to the G terminal of each latch. 1-13 to 1-20 are AND gates which perform AND operations on the channel O select signal to channel 7 select signal and the A/D register select signal, respectively. Every time the A/D register selection signal is output, a signal is output from the selected latch onto the data bus 1-21. 1-33 to 1-40 are AND gates,
The channel 0 select signal to channel 7 select signal are input to one side of the two, and the A signal is input to the other side.
The output of ND gate 1-44 is input.

FIG. 2 shows the configuration of the channel select signal generation circuit.

In the figure, 1-31 is a ripple carry counter, and the channel switching signal from the CPU is applied to its clock terminal.
The output value is changed every time the pulse is set. 1
-32 is a decoder, ripple carry counter 1-31
A signal [l] is set on the select signal line in response to a signal from the select signal line, and decoding corresponding to all the states is performed.

The latches are selected as shown in Table 1 according to the channel 0 select signal to channel 7 select signal output lines on which [1] is set.

Table 1 Next, the operation will be explained.

This is a comparison of main PWM control data by comparator 5 → sub (1) comparison of PWM control data by comparator 5 → comparison of main PWM control data by comparator 5 → sub (2) comparison of PWM control data by comparator 5 → comparator Comparison of main PWM control data using 5 → Sub (3) PW using comparator 5
In this example, comparison of M control data→1-bit A/D conversion by comparator 5 is defined as one cycle, and this cycle is repeated.

(1) Assume that rlJ is set on the channel 3 select signal output line and latches 1-8 are selected (see Table 1).

02037 unit 1 latches each PWM output control value from 21 to
24, and various data necessary for main PWM operation are written to the register in the main PWMIO.

Further, analog input channel data to be A/D converted is written to a latch within the timing controller 25.

(2) The timing controller 25 first selects the latch 21 and outputs data, that is, the control value of the main PIIM, to the D/A converter 4, and the D/A converter 4 generates an analog voltage based on the data. . At the same time, the main PWM output feedback signal and input terminal of MPX8 are selected. The output of the D/A converter 4 is input to one input terminal of the comparator 5, and the output of the MPX 8 is input to the other input terminal of the comparator 5. The comparator 5 compares the power of both people, and as a result of the comparison, if the input level on the MPXg side is higher than the input level on the D/A converter 4 side, a high level is output, and if it is lower, a low level is output, and 1 bit
It is input to a register (latch) 7 with an X5 configuration. After the timing controller 25 delays the output of the comparator 5 for a sufficient period of time, 1 bit of the latch 7 corresponding to the main PWMIO is selected and the comparison result is latched.

(3) Next, the latch 22 is selected by the timing controller 25, and data is output to the D/A converter 4. At the same time, the feedback signal input terminal of the sub (1) PWM II output of the MPX8 is selected, and the D/A converter 4 output and MPX8 output are input to comparator 5. Then, the timing controller 25 delays the output of the comparator 5 for a sufficient period of time as described above, and then selects 1 bit of the register 7 corresponding to the sub (1) PWM 11 output, and latches the comparison result.

(4) Next, perform the same operation as described above for the main PWMIO.

(5) Next, perform the same operation for the sub (2) PWM 12 output.

(6) Thereafter, the same operations as the main and sub (3) PWM 13 are repeated. This is the main PWM! !
This is because the comparison operation corresponding to the force requires high speed compared to other sub-PWM outputs.

(7) Next, a main PWM comparison operation is performed.

(8) Next, perform operation for 1-bit A/D conversion.

(9) After that, repeat the above one-cycle operation.

Next, the A/D operation will be explained in detail.

(a) When the initial signal generation circuit 1-30 operates,
The initial circuit 32 operates and outputs a value of 1000000°B to the latch 33. Now, the latch enable goes high, the latch 33 is loaded with the value of °1000000'B, the latch enable signal goes low,
Suppose that the loaded value becomes latched.

(b) Next, when the A/D cycle comes, the A/D selection signal is set to high level by the timing controller 25, the 3-state buffer of the latch 33 is turned on, and the contents of the latch 33 are set to '1000000°. B is D/A
sent to the data bus. At the same time, latch 30 is enabled and the above value is loaded into latch 30. Further, this value is sent to the D/A converter 4 and subjected to D/A conversion, and the D/A converted analog voltage is input to one terminal of the comparator 5. At this time, the other terminal of the comparator 5 is connected to the timing controller 25.
The MPX8 is driven and inputted to select one of the analog inputs (in this case, 8 channels) to be A/D converted by the signal.

The comparison result of the comparator 5 outputs "1" when the analog input is higher than the D/A conversion value, and outputs "0" when it is lower. Ru. The arithmetic unit 31 has an input, that is, a latch 3
The comparison result is reflected on the least significant bit of the bits set to "1" among the outputs of 0, and the result is output as new data. At the same time, the lowest bit next to the lowest bit of the bits set to "l", that is, bit 5, is forcibly set to "1" and output as new data, and the remaining bits are input as they are. Output as new data.

That is, in this case, the output of the latch 30 is °10000
Since it is 00゛B, the arithmetic unit 31 reflects the comparison result in MSH, and sets it as "1" when the comparison result is high, and when it is low.
0" as the MSB. Furthermore, since the input to the arithmetic unit 31 is °1000000°B, the next bit of the MSB is forcibly set to "1", so the new data is 'xs1oooooo°B (Xs is "l" or "0") determined by the comparison result is generated as new data.The initial signal generation circuit 35 does not operate at this time, so the initial circuit 32 also does not operate, and the arithmetic unit 31 The output of the comparator 5 is inputted as is to the latch 33, and when the output of the comparator 5 becomes sufficiently stable, the latch enable signal generated becomes high and is loaded into the latch 33. Furthermore, when the latch enable signal becomes low, it is latched. .At this time, the enable signal does not operate.

(c) Next, when the A/D cycle comes, similarly to (b), the A/D selection signal is set to high level by the timing controller 25, and the contents of the latch 33 are changed to '
X10000°B is sent to the D/A data bus and loaded into latch 30 at the same time. And its value is D
/A converted and the D/A converted value is input to the comparator 5, and the analog input to be A/D converted is input to the other terminal of the comparator. Arithmetic unit 31 receives input 'X
, 100000°B, the comparison result is reflected in the least significant bit of the bits set to "l", that is, bit5, and 0" or l" is output as the data of bit5. Further, the lowest bit next to the least significant bit marked with "l", in this case bit 4, is forcibly output as "1", and the remaining bits are output as they are. That is, output XJs1000°B (xs is 1" or "0" determined by the previous A/D cycle, Xs is "1" or "0" determined by this A/D cycle) as new data. Initial The signal generation circuit 1-30 does not operate in this cycle, so the initial circuit 32 also does not operate.The output of the arithmetic unit 31 is directly sent to the latch 3.
3, and the latch 3 is input by the latch enable pulse.
3 and latched. Also, the enable signal does not operate this time as well.

(4) Thereafter, essentially the same operation as above is performed up to bitl every time an A/D cycle occurs.

(5) Then, after determining up to bitl, drive the A/D selection signal and set the contents of the latch 33, that is, °x, x,
x, x.

X, 1'B is sent to the D/A data bus and loaded into latch 30 at the same time. Then, convert the value to D/A,
Input it to comparator 5 as an analog voltage value, and input it to A/D
Comparator 5 selects the analog input to be converted
and the comparison result is input to the other terminal of the arithmetic unit 31.
Enter. The arithmetic unit 31 reflects the comparison result in the least significant bit set to "l", that is, LSB (bite), and sets it as "0" or "bit" data.
1” is the same as the previous A/D cycle operation for determining other bits.
Similarly, the other bits are output as is. That is, the definite data and L te'xsxsx, x, x, x
, x, °B.

Since all bits have been determined in this cycle, the latch enable signal enables the latches 1-8, and the determined data is loaded into the latches 1-8. Since the bitO output of the latch 30 is "1", confirmation of all bits can be determined by ANDing with the latch enable pulse generated when the comparison result of bitO is stable using the AND gate 1-44.

In addition, when bito of the latch 30 is °1'', it is a flag indicating that all bits of A/D conversion have been compared, so the A/D conversion operation will restart from the most significant bit in the next A/D cycle. The initial signal generation circuit 1-30 operates, causing the initial circuit 32 to operate.The initial circuit 32 outputs °1000000 °B and outputs "1ooo
o00'B is loaded into latch 33 by the latch enable signal. With the above, a series of 7-bit A/D conversion operations is completed.

Note that each latch data is undefined at reset, so
When all bits are O, the initial signal generation circuit 35 is forced to operate and outputs '1000000°B to the latch 33.

Also, if any bit is set among the 7 bits at reset, the LSB
The A/D operation is performed until the initial signal generation circuit 1-3
Operate 0. In other words, the A/D conversion result may become unstable the first time after a series of A/D conversion operations are reset, but there is no harm as the contents of latches 1-5 to 1-12 are constantly refreshed. .

To avoid this, the latch 30 may be forcibly set to "0" or "000001" using a reset signal.

The contents of the latch 34 are sent to the data bus and read into the CPU when the A/D register selection signal decoded from the address sent from the CPU becomes active.

Note that to change the latch selection, when a channel switching signal is input to the clock input terminal of the 1-clock D flip-flop 1-1, the signal at the Q output terminal of the D flip-flop 1-1 changes from "0" to "1'', an initial input is input to the initial circuit 32 through the OR gate of the initial signal generating circuit 1-30, and AD conversion starts. Then, at the next timing, AD conversion starts, and at the moment when the MSB of the latch 30 is set to "1", the R terminal of the D flip-flop l-1 becomes "1", and the D flip-flop 1-1 is reset. In addition, the MSH of the latch 30 is set to “1” in advance.
” is set, input the channel switching signal to the latch 30 from one input terminal of the OR gate 1-41,
Latch 30 with channel switching signal when switching channels
This can be handled by resetting , and then setting the Q output of the D flip-flop 1-1 from "0" to rlJ. It is assumed that the circuit does not include an all-clear circuit at the start of circuit operation, and the Q output terminal of the D flip-flop 1-1 is naturally at "0" at the time of all clear.

1 vertical fork 11 In comparison with one embodiment, this embodiment has latches 1-5 to 11.
In this embodiment, when the channel switching signal is input to the signal line 1-2, the D flip-flop 1-42 is reset and its Q output becomes "0". So, AND gate 1-4
The 8 force of 5 becomes low level, and as a result, latch 1-5
Writing of result data from the AD converters 1-12 is prohibited. Then, at the next timing, the A/D register selection signal is applied to the signal line 1-46, and at the rising edge of the signal, the data stored in the register of the channel selected at that time is transferred to the data bus 1-46 by the CPU. -21 can be read out. And A/
At the falling edge of the D register selection signal, the Q output of the D flip-flop 1-42 becomes "1", and the latches 1-5 to 1-
It becomes possible to write the AD conversion result to 12.

r Effects of the Invention] As explained above, according to the present invention, since it is configured as described above, the following effects (1) to (3) are obtained.

(1) Since it has a dedicated output register for signals undergoing AD conversion, past AD conversion results can be saved and easily referenced.

(2) Since the AD conversion result can be accessed at the same address as the AD conversion channel selection address, software creation is facilitated.

(3) The AD conversion operation restarts at the timing of switching the register that reads the AD conversion result, so the
The time required to obtain a conversion result can be reduced compared to the conventional method.

Furthermore, scheduling for reading the software AD conversion results becomes easy.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of the present invention, FIG. 2 is a block diagram showing the configuration of a channel select signal generation circuit, and FIG. 3 is a block diagram showing the configuration of the A/D conversion control section 6 shown in the first diagram. 4 is a block diagram showing the configuration of an A/D conversion control section in another embodiment. FIG. 5 is a block diagram showing the configuration of a conventional A/D conversion device. FIG. 7 is a block diagram showing the configuration of the D conversion control section 56. FIG. 7 is a timing chart showing an example of the timing around the conventional comparator. FIG. 8 is a diagram showing the timing of the conventional comparator. DESCRIPTION OF SYMBOLS 1... CPU core part, 4... D/A converter, 5... Comparator, 6... A/D conversion control part, 7... Register, 8... Multiplexer, 10... Main PWM. 11...Sub (1) PWM. 12...Sub (2) PWM. 13...Sub (3) PWM. 25...Timing controller, 1-1.1-42...D flip-flop, 1-5~
1-12...Latch, 1-41...OR gate, 1-45...AND gate, 1-30...Initial signal generation circuit, 1-31...
- Ripple carry counter, 1-32... Decoder, 30... Latch, 31... Arithmetic unit, 32... Initial circuit, 33... Latch.

Claims (1)

[Claims] 1) A chopper type comparator, and a digital reference voltage for time-division comparison with multi-channel inputs by the chopper type comparator, and AD of the multi-channel inputs.
In an AD conversion device having a digital reference voltage for successively AD converting analog data of a conversion channel and a DA converter for DA converting the analog data, the AD conversion device has the same number of storage means as the AD conversion channels; and writing means for writing the AD conversion result into the storage means of the address corresponding to the AD.
conversion device. 2) The AD conversion device according to claim 1, wherein the writing means writes a new AD conversion result obtained each time the AD conversion channel is switched to the storage means of an address corresponding to the AD conversion channel. 3) In claim 1, the writing means writes a new AD conversion result into the storage means after data is read from the storage means at least once.
D conversion device. 4) In any one of claims 1 to 3,
An AD conversion device characterized in that each means is integrated on one common semiconductor substrate.