JPH0447333A - Microprogram loading system - Google Patents

Abstract

PURPOSE:To shorten time required for loading a microprogram by executing program loading from main storage at a time for all processors by sending the load timing of the microprogram to the processors other than the processor to be a host at the time of starting a system. CONSTITUTION:By a microprogram load start command issued from a diagnostic processor 2, the program loading to all plural processors from the main storage 1 is executed at a time. Namely, timing at which the microprogram on a system bus 5 is stored into a microprogram storage memory #0 7 is generated by a microprogram loader 9. Then, it is sent as a microprogram fetch signal to an address counter 10 for designating the microprogram storage memory #0 7 in the processor #0 3, the microprogram storage memory #1 8 in the processor #1 4, and the address of the microprogram storage memory #1 8 through a microprogram fetch signal line 12. Thus, the time required for loading the microprogram can be shortened.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a microprogram loading method, and particularly to a microprogram loading method during multiprocessing operation.

[Conventional technology]

Conventionally, the method of loading a microprogram into an information processing system having 9n processors is to first issue a microprogram load instruction to processor #0 based on instructions from a diagnostic processor, start the microprogram loader inside processor #O, and load the microprogram. Load the program.

When loading to processor #0 is completed, loading to processor #1 is performed by the diagnostic processor.

Thereafter, the microprogram loading up to processor #1 was repeated in the same way.

[Problem to be solved by the invention]

In the conventional microprogram loading method described above, the diagnostic processor cannot instruct multiple processors to load microprograms at the same time, and in order to load microprograms into each processor in turn, it is necessary to install a microprogram loader inside every processor. Moreover, the disadvantage is that the time required to load the microprogram increases in proportion to the number of processors.

[Means to solve the problem]

The microprogram loading method of the present invention involves a microprogram loader in processor #0, which is the system startup owner, a load register in one or more processors other than processor #0, and a load register in one or more processors other than processor #0, and A microprogram capture signal line that outputs the microprogram capture timing on the system bus to a single or multiple processors, multiple microprogram storage memories for storing microprograms in multiple processors, and processors other than #0. It has an address counter to specify the address of the microprogram storage memory in a single or multiple processors, and executes program loading from the main memory to all multiple processors simultaneously by the microprogram load start command issued by the diagnostic processor. and means to do so.

〔Example〕

Next, the present invention will be explained in detail with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

A case where multiprocessing operation is implemented using two processors will be described.

A diagnostic processor 2 that is a processor for diagnosing the main memory 1 and the system, processors #0 and 3 that are internal to the plurality of processors, and slave processors #1 and 4 are connected to a system bus 5. Furthermore, the diagnostic processor 2, processors #0, 3, and processors #1, 4 are connected to a diagnostic bus 6.

Microprogram loading at system startup is performed as follows. When diagnostic processor 2 finishes diagnosing processors #0, 3 and processors #1, 4, a microprogram load start command is issued and the load in processor #1 is completed. Register 11 is set to "1".

When load register 11 is set, processor #1
, 4 become ready for loading the microprogram on the system bus.

In addition, the microprogram load start command starts the microprogram loader 9 in the processor #03, takes out the microprogram stored in the main memory 1, and loads it into the microprogram storage memory #07 in the processor #03. Start storing operation.

The microprogram loader 9 generates and sends a write address #013 to the microprogram storage memory #07 in order to control reading of the microprogram in the main memory 1 and controlling writing to the microprogram storage memory #07.

Here, the timing at which the microprogram on the system bus 5 is stored in the microprogram storage memory 7 is generated by the microprogram loader 9, and the timing at which the microprogram on the system bus 5 is stored in the microprogram storage memory #07 in the processor #03 and the microprogram storage in the processor #14 is generated. Memory #1
8 and an address counter 10 for specifying the address of the microprogram storage memory #18 as a microprogram capture signal line 12.

The address counter 10 is connected to this program capture signal line 12.
The write address # is counted up and output from the microprogram loader 9 in the processor #0.3.
An address similar to 0.13 is sent to microprogram storage memory #1.8 using write address #1.14.

When the microprogram is repeatedly retrieved and stored as described above and the retrieval is completed, the diagnostic processor 2
The load register 11 is reset to "0" and the microprogram loading is completed.

〔Effect of the invention〕

As explained above, the present invention utilizes a microprogram in processor #0, which is the system startup owner, and a load register and microprogram import signal line in one or more processors other than processor #0. By sending the microprogram load timing to processors other than #0, the program can be loaded from main memory to all processors at the same time, which has the effect of shortening the time required to load the microprogram. This has the effect that a microprogram loader is not required and the amount of hardware can be reduced compared to the conventional method.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing an embodiment of the present invention. DESCRIPTION OF SYMBOLS 1... Main memory, 2... Diagnostic processor, 3... Processor #0.4... Processor #L5... System bus, 6... Diagnostic bus, 7... Microprogram storage memory #0.8... Micro program storage memory #engineering, 9... Micro program loader, 10.
...Address counter, 11...Load register, 1
2...Microprogram import signal line, 13...Write address #0, 4...Write address #1゜

Claims (1)

[Claims] Multiple processors (processors #0, #1,..., #n
; n is a positive integer), a diagnostic processor for diagnosing the plurality of processors, a main memory, a diagnostic bus connecting the plurality of processors and the diagnostic processor, and a diagnostic bus connecting the plurality of processors, the diagnostic processor, and the main memory. In the microprogram loading method of an information processing system capable of multiprocessing operations configured by a system bus, when the system is started up, the microprogram loader in the main processor #0 and the microprogram loader in the main processor #0 are a load register in the single or multiple processors; a microprogram loading signal line for outputting the loading timing of the microprogram on the system bus from the microprogram loader to the single or multiple processors other than the #0; Multiple microprogram storage memories (#0, #1, . . . #n; processor #0, #1, . . . #n) for storing microprograms in multiple processors (processors #0, #1, . . . #n)
0, #1, ... #n) and the processor #0
has an address counter for specifying the address of the microprogram storage memory in one or more processors other than the above, and the microprogram load start command issued by the diagnostic processor causes the main memory to be loaded into all of the plurality of processors. A microprogram loading method characterized by comprising means for simultaneously executing program loading.