JPH0445856B2 - - Google Patents
Info
- Publication number
- JPH0445856B2 JPH0445856B2 JP62045881A JP4588187A JPH0445856B2 JP H0445856 B2 JPH0445856 B2 JP H0445856B2 JP 62045881 A JP62045881 A JP 62045881A JP 4588187 A JP4588187 A JP 4588187A JP H0445856 B2 JPH0445856 B2 JP H0445856B2
- Authority
- JP
- Japan
- Prior art keywords
- output
- bit
- circuit
- adder
- adder circuit
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62045881A JPS63211431A (ja) | 1987-02-27 | 1987-02-27 | 加算回路 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP62045881A JPS63211431A (ja) | 1987-02-27 | 1987-02-27 | 加算回路 |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS63211431A JPS63211431A (ja) | 1988-09-02 |
| JPH0445856B2 true JPH0445856B2 (enrdf_load_stackoverflow) | 1992-07-28 |
Family
ID=12731572
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP62045881A Granted JPS63211431A (ja) | 1987-02-27 | 1987-02-27 | 加算回路 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS63211431A (enrdf_load_stackoverflow) |
Families Citing this family (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5038314A (en) * | 1989-11-17 | 1991-08-06 | Digital Equipment Corporation | Method and apparatus for correction of underflow and overflow |
Family Cites Families (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH067375B2 (ja) * | 1985-05-17 | 1994-01-26 | 日本電気株式会社 | 演算回路 |
-
1987
- 1987-02-27 JP JP62045881A patent/JPS63211431A/ja active Granted
Also Published As
| Publication number | Publication date |
|---|---|
| JPS63211431A (ja) | 1988-09-02 |
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US4667337A (en) | Integrated circuit having outputs configured for reduced state changes | |
| US4761760A (en) | Digital adder-subtracter with tentative result correction circuit | |
| EP0209308B1 (en) | Circuitry for complementing binary numbers | |
| JPH0650462B2 (ja) | シフト数制御回路 | |
| JPH0215088B2 (enrdf_load_stackoverflow) | ||
| US3932734A (en) | Binary parallel adder employing high speed gating circuitry | |
| JPH0421889B2 (enrdf_load_stackoverflow) | ||
| JP3248743B2 (ja) | 符号付き加算器のためのオーバーフロー/アンダーフロー高速制限回路 | |
| US5319347A (en) | Parallelized magnitude comparator for comparing a binary number to a fixed value | |
| US4899305A (en) | Manchester carry adder circuit | |
| US6434588B1 (en) | Binary counter with low power consumption | |
| US4092522A (en) | 5-Bit counter/shift register utilizing current mode logic | |
| JPH0445856B2 (enrdf_load_stackoverflow) | ||
| JPH09222991A (ja) | 加算方法および加算器 | |
| GB2184579A (en) | A multi-stage parallel binary adder | |
| US5357235A (en) | Parallelized magnitude comparator | |
| JP2766133B2 (ja) | パラレル・シリアル・データ変換回路 | |
| JP4354648B2 (ja) | バイアスを招かないで固定少数点フォーマットに信号を圧縮するための方法と装置 | |
| JP2552028B2 (ja) | 加算器 | |
| US5224133A (en) | Modular high speed counter employing edge-triggered code | |
| JP2629737B2 (ja) | アキュムレータ | |
| JP3106525B2 (ja) | 加算方式及びその回路 | |
| JP2804421B2 (ja) | 係数切替プリスケーラ | |
| JP2570562Y2 (ja) | 同期式カウンタ | |
| JPH0779247B2 (ja) | デコ−ド回路 |