JPH044450A - Computer system - Google Patents

Abstract

PURPOSE:To secure compatibility during both writing time and reading-out time and, at the same time, to read out written data by utilizing another address when the same address as that of an original computer system is accessed by providing a specific register. CONSTITUTION:A register, in or from which the same data as those written in a control register can be written or read out based on the writing address or reading-out address designated by an address generating means, is provided. For a compatible computer system, the data written in the control register, from which the same data as those written by an original computer system cannot be read out, can be read out while the compatibility is secured.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a computer system, and particularly to a computer system that has new functions added to it while maintaining compatibility with other computer systems.

[Prior Art] In computer systems, the importance of software as well as hardware has been recognized.

In order to create a highly functional computer system, it is necessary to create not only hardware but also high-quality software.

However, in today's era of rapid progress, it is becoming difficult for manufacturers to independently improve both hardware and software.

Therefore, many computer systems have been realized that have a so-called compatibility function that allows the use of software created for other computer systems.

Although such computer systems have the advantage of saving software development costs and development time, it is difficult to add new functions due to the need to maintain compatibility.

Adding new functions while maintaining compatibility is a major challenge in developing computer systems with compatible functions.

One of these is the need to be able to read the same value as the written data while maintaining compatibility with the control register, which has a structure that makes it impossible to read the written data in the original computer system. There is.

For example, a register with a screen display control controller is
When writing, it functions as a screen mode setting register, and when reading, it functions as a status register that indicates the operating status of the controller. Because the function of the register is different when writing and when reading, write to this control register. The entered data cannot be read out as is.

In conventional computer systems with compatibility functions, this problem was handled by software.

For example, if you store the data in a specific location in memory when writing, and you need to read the same value,
For example, the data is read from its memory rather than from the controller.

[Problem to be solved by the invention] However, since this method does not directly read the value of the controller, there are cases where multiple programs are running in parallel, such as during multitasking. If a program rewrites the contents of the controller without permission, a difference will occur between the data written to the controller stored in memory by other programs and the data actually written to the controller, and the computer system There were problems such as the possibility that the system would not work properly.

This invention was made to solve the above problem. When writing, the target control register is accessed at the same address, and when reading, it is accessed at a different address that is unused in the original computer system. By providing a register that is configured so that the same address as the original computer system is accessed, compatibility is ensured both when writing and when reading, and when writing using a different address. It is an object of the present invention to obtain a computer system that can also read data as it is.

[Means for Solving the Problems] A computer system according to the present invention includes a control register that has different functions during read or write access, a write address that is the same as an address for the control register,
Address generation means for specifying an arbitrary address different from the read address, and the same data as the data written to the control register based on the write address or read address specified by the address generation means can be written or read. A register is provided.

[Operation] In this invention, when a write access to the control register is started, the address generation means generates a write address for the register, and according to this address, the same data as the data written to the control register is written to the register. written.

Then, when a read access to the control register is started, data based on an original function different from the write data is read out, and compatibility is maintained.

On the other hand, when the address generating means generates an arbitrary read address different from the write address for the register, the data written in the register, that is, the same data as the data written in the control register can be read.

[Embodiment] FIG. 1 is a block diagram illustrating the configuration of a computer system showing an embodiment of the present invention, in which 1 is a CPU;
Data processing with each device connected to the system bus 10 is performed via the main memory 2, and processing for outputting the processing results to the display device 8 or the like is generally controlled. A magnetic disk interface 3 interfaces data processing between the magnetic disk device 4 and the system bus 10.

Reference numeral 5 denotes a keyboard interface, which interfaces key data from the keyboard 6 with data processing with the system bus 1o. A screen control controller 7 includes various control registers for screen control, and controls data output to the display device 8.

Reference numeral 9 denotes a write data read circuit, which includes a register and address generation means in this embodiment.

FIG. 2 is a circuit block diagram illustrating the configuration of the write data read circuit 9 shown in FIG. 1, and the same components as in FIG. 1 are given the same reference numerals.

In the figure, reference numeral 11 denotes an address decoder, which generates different addresses as a write address and a read address for the write data latch circuit 12 (for example, composed of a D-type flip-flop) as will be described later. That is, when an address on the address bus constituting the system bus 10 is analyzed and a write address to a control register is generated, a write address (
In this embodiment, 300H) is specified, and the write data latch circuit 12 is made to hold the same data as the data written to the control register. On the other hand, the address on the address bus constituting the system bus 10 is analyzed to generate an arbitrarily specifiable read address (400H in this embodiment) different from the write address.

14 is a logic circuit group composed of, for example, an AND gate, which performs a logical operation on the contents of the access control line (read signal, write signal) on the system bus 10 and the write address, read address, and outputs the write data latch circuit 12.
output a latch signal or an output enable signal for (for example, a D-type flip-flop).

13 is a data output buffer circuit, and logic circuit group 14
Based on the output enable signal output from the write data latch circuit 12, the same data as the data written to the control register of the screen control controller 7 is output to the system bus 10.

In a computer system configured in this way,
When a write access to the control register is started, the address generation means (comprising the address decoder 11 in this embodiment) generates a write address for the register (comprising the write data latch circuit 12 in this embodiment). The same data that is written to the control register is written to the register according to this address.

Then, when a read access to the control register is initiated, it is based on the original function (
Data is read and compatibility is maintained.

On the other hand, when the address decoder 11 generates an arbitrary read address different from the write address for the control register, the data written to the write data latch circuit 12, that is, the same data as the data written to the control register, is read. It becomes possible to take out.

The data processing operation of the write data read circuit 9 shown in FIG. 2 will be described below with reference to FIGS. 3 and 4.

FIG. 3 is a correlation diagram illustrating the correspondence between the addresses and functions of each control register in the screen control controller 7 shown in FIG. , address 300H is
Since the function is different when reading/writing, the address 3 above is
The contents of the control register corresponding to QOH cannot be read.

FIG. 4 is a correlation diagram showing the relative relationship between address designation by the write data reading circuit 9 shown in FIG. 2 and its functional processing. When the CPU 1 is instructed to write access to address 300H, 7 sets the mode in the control register (address 300H), and in parallel with this, the same write data is written into the write data latch circuit 12. On the other hand, CPU 1 is at address 3
When a read access to 00H is instructed, the address decoder 11 generates address 300H;
The status of H is readable to ensure compatibility.

On the other hand, when the CPU 1 specifies address 400H, the data written to the write data latch circuit 12 (data written to the control register by the screen control controller 7) is outputted from the data output buffer circuit 13 to the system bus 10.

It is now assumed that the registers and functions of the screen control controller 7 are as shown in FIG. It is also assumed that the address and function of the write data read circuit 9 are as described in FIG.

Among the registers in the screen control controller 7, the registers at addresses 301H to 303H have the same function during writing and reading, and written data can be read as is.

On the other hand, since the register at address 300H has different functions during writing and reading, the written data cannot be read as is.

Therefore, the address decoder 11 generates an address such that the address of the write data read circuit 9 becomes address 300H during writing and 400H during reading.

As a result, when the CPU 1 writes to the address 300H, the address 300 in the screen control controller 7
The same data is written to both the 0H control register and the write data read circuit 9. Further, when the CPU 1 reads out the address 300H, the status in the screen control controller 7 can be read out as in the original computer system.

On the other hand, when the CPU 1 reads the address 400H, the contents of the write data reading circuit 9, that is, the data written in the control register at the address 300H in the screen control controller 7 can be read as is.

In other words, as long as the address 300H is accessed, the operation is exactly the same as when the write data read circuit 9 does not exist, so compatibility with the individual original computer systems is maintained.

Furthermore, by reading the contents of address 400H, it becomes possible to read data written to address 300H, which could not be read in the original computer system, and data useful for other functional processes can be monitored.

FIG. 5 is a flowchart illustrating an example of a data processing procedure of the write data reading circuit 9 shown in FIG. Note that (1) to (7) indicate each step.

First, it is necessary to determine whether access to a specific control register with different functions for reading/writing is specified.1)
, if YES, it is determined whether the access type is write access 2), if YES, the same data as the data to be written to the control register is sent to the write data latch circuit 1 based on the write address specified from the address decoder 11.
2 (3) and move on to other processing.

On the other hand, if the determination in step (2) is No, it is determined whether the read address is the same as the write address for the control register.41. If YES, read the status 5) and proceed to other processing; if No, determine whether the latch address for the write data latch circuit 12 is specified 6); if NO, proceed to other processing, If YES, the same data as the data written to the control register is output onto the system bus 1o (7), and the process moves on to other processing.

In the above embodiment, the case where the read address and the write address to the write data latch circuit 12 are instructed by the address decoder 11 constituting the address generation means has been explained, but as shown in FIG. Separate dip switches 15 (for reading) and dip switches 17 (for writing) are provided, and addresses on the system bus 10 and each dip switch 15. By providing address comparison circuits 16 and 18 as shown in the figure for comparing addresses designated by the dip switch 17, it is possible to increase the degree of freedom in address designation.

FIG. 6 is a circuit block diagram illustrating another configuration of the address decoder 11 shown in FIG. 2, and the same components as in FIG. 1 are given the same reference numerals.

21 is a logic circuit group composed of, for example, an AND gate, which performs a logical operation on the contents of the access control line (read signal, write signal) on the system bus 1o and the above-mentioned write address, read address, and outputs the write data latch circuit 19.
output a latch signal or an output enable signal for (for example, a D-type flip-flop).

20 is a data output buffer circuit, and logic circuit group 21
Based on the output enable signal output from the write data latch circuit 19, the same data as the data written in the control register of the screen control controller 7, which is latched by the write data latch circuit 19, is output to the system bus 1o. Note that the data processing differs from the above embodiment only in address designation of write addresses and read addresses, so a description thereof will be omitted.

[Effects of the Invention] As explained above, the present invention specifies control registers with different functions during read or write access, a drop-in address that is the same as the address for the control register, and an arbitrary address where the read address is different from the address. Since an address generating means and a register capable of writing or reading the same data as the data written to the control register based on the write address or read address specified by the address generating means are provided, a computer with compatible functions can be used. In the system, a compatibility function has been added that allows the system to read the data written to the control register while ensuring compatibility for the control register, which cannot read the same data as the data written in the original computer system. This has the effect of making it easier to realize a computer system that has a computer system.

[Brief explanation of the drawing]

FIG. 1 is a block diagram illustrating the configuration of a computer system showing an embodiment of the present invention, FIG. 2 is a circuit block diagram illustrating the configuration of the write data read circuit shown in FIG. 1, and FIG. , a correlation diagram explaining the correspondence between the addresses and functions of each control register in the screen control controller shown in Fig. 1, and Fig. 4 shows address designation and its functional processing by the write data reading circuit shown in Fig. 2. FIG. 5 is a flowchart illustrating an example of the data processing procedure of the write data read circuit shown in FIG. 1, and FIG. 6 is a correlation diagram showing the relative relationship between FIG. 2 is a circuit block diagram illustrating the configuration. In the figure, 1 is a CPU, 2 is a main memory, 3 is a magnetic interface, 4 is a magnetic disk device, 5 is a keyboard interface, 6 is a keypad, 7 is a screen control controller, 8 is a display device, and 9 is write data This is a readout circuit.

Claims (1)

[Claims] In a computer system having a compatibility function with other systems, a control register with a different function during read or write access, a write address that is the same as the address for the control register, and an arbitrary address whose read address is different from the above address. It is characterized by comprising a designated address generating means and a register capable of writing or reading the same data as the data written to the control register based on the write address or read address designated by the address generating means. computer system.