JPH0444261A - Bicmos semiconductor integrated circuit device and manufacture thereof - Google Patents

Abstract

PURPOSE:To reduce a collector region, to inject a thin epitaxial layer, to highly integrate, and to improve its latchup resistance by forming isolation between bipolar transistors, between an NMOS or the transistor and a PMOS by means of a deep groove reaching a substrate, and isolation between the NMOS and the PMOS by means of a shallow groove. CONSTITUTION:An N<+> type buried layer 52 is formed on a P-type substrate 51 in which boron is added, and an N-type epitaxial layer 67 is deposited. Then, after an element region is formed, a shallow groove 68 and a deep groove 69 for isolation are formed, boron is ion implanted in the bottom of the groove 69 perpendicularly to a substrate, and a P<+> type channel cut region 66 is then formed. Thereafter, oxide film 65, 651 are deposited until the grooves 68, 69 are completely buried, and a P-well region 53 is formed. Subsequently, an NMOSFET 72 is formed on the region 53, a PMOSFET 71 is formed on an N-well region 54, and an NPN bipolar transistor 73 is formed on the region 541.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to bipolar transistors and complementary MO5
) transistor (hereinafter referred to as CMO3)
This article relates to the structure and manufacturing method of the OS type integrated circuit type integrated circuit CMO8 (referred to as CMO8), and in particular, the internal dual power supply type EC.
The present invention relates to a semiconductor device structure that can be applied to an L-110 type BiCMOS circuit, and that simultaneously achieves a reduction in collector capacitance (M), improvement in rough-tube resistance, and high integration of a CMOS device, and a method for manufacturing the same.

[Conventional technology]

The demand for lower power supply voltage in micro CMO5 elements is due to Bi
In CMOS circuits, severe limitations are imposed on the performance of bipolar elements. One solution to this problem is to lower the operating voltage of CMO3 by having a power supply voltage conversion circuit in the chip.
In the case of a type B i CMOS circuit, it is necessary to separate the P-well from the P-substrate in order to avoid problems with the breakdown voltage of NMO3 and the substrate bias effect. Conventionally, P-well was
The following two types of typical structures of a BiCMOS integrated circuit separated from a substrate can be considered. Examples of respective structural cross-sectional views are shown in FIGS. 3 and 4.

In these figures, 1 is a P-type semiconductor substrate, 2, 2a and 2b are N buried layers, 3 is a P-type semiconductor region, 4 is a P-well, 5 is an N-well, 51 is an N-type semiconductor region, and 6 is a N-type semiconductor region. N゛Collector compensation region, 7 is base 9M region, 8 is emitter region, 9 is source/drain of NMO8, 10 is PMO3
11 is a field oxide film, 12 is a gate oxide film, 13 is a gate electrode, and 14 is an insulator.

That is, in the conventional example I shown in FIG. 3, a buried layer 2a for reducing the collector resistance is provided in the bipolar transistor, and an N-type buried layer 2a is provided under the P well and the N well to connect the P well 4 and the P well. The substrate 1 is separated, and the bipolar transistors are separated from each other and between the bipolar transistors and the PMO.
5 or between the noibora transistor and NMO3,
They are separated by a P-type semiconductor region 3.

In addition, the conventional example ■ in Fig. 4 is Unino\Ji2 embedded in the entire surface.
b, and the bipolar transistors and the bipolar transistors and the NMO5 or the bipolar transistor and the PMO3 are separated by a deep trench that reaches as far as the P-type substrate 1 in which the insulator 14 is buried, along with the buried layer 2b. .

[Problem to be solved by the invention]

By the way, the above-mentioned conventional BiCMOS integrated circuits each have the following drawbacks.

(i) In the case of conventional example I in Fig. 3a) Since a PN junction is used for isolation between bipolar transistors and between PMO8 and bipolar transistor or between NMO8 and bipolar transistor, the capacitance of the isolation part is large and bipolar There are limitations to increasing speed, such as the difficulty of reducing the collector capacitance of the transistor. Furthermore, the area of the separated portion is large, making it unsuitable for high integration.

b) In order to realize high-performance bipolar transistors,
The shrimp layer needs to be thinner. However, for this structure,
Since the depth of the P-well is determined by the thickness of the shrimp layer, thinning the shrimp layer increases the resistance of the P-well and increases the current amplification factor of the parasitic vertical bipolar transistor.

Furthermore, the current amplification factor of the lateral parasitic bipolar increases with miniaturization, resulting in a decrease in the CMOS circuit's resistance to cavities, chirps, and bursts.

(ii) In the case of conventional example (■) in Fig. 4, between bipolar transistors, between bipolar transistors and NMO5 or PM
Since O3 and PMO3 are separated by an insulating material such as a groove, it is possible to reduce the isolation capacitance and reduce the area of the isolation part, and at the same time, it is possible to ensure sufficient resistance to rough rises and bubbles.

However, in this structure, in order to fix the potential of the N-type buried layer under the P-well to separate the P-well and the P-substrate, a new A contact region with the N-type buried layer must be formed.

Therefore, not only the chip area increases, but also the pattern design becomes complicated. Furthermore, if the potential of the buried layer under the P-well is not fixed but left in a floating state, the potential of the buried layer will easily change due to charges injected into the buried layer, causing temporary parasitic bipolar behavior. Therefore, the reliability of circuit operation decreases.

In this way, the ECL/I10 type Bi
Conventional P designed for use with 0M05 circuits
The device structure of the B i CMO8 integrated circuit, in which the well is separated from the P substrate, meets the requirements for realizing high-performance bipolar transistors, such as reducing the collector capacitance and introducing a thin shrimp layer, as well as achieving high integration.

It was not possible to simultaneously satisfy the challenges of ensuring latch amplifier durability for CMOS devices.

The present invention has been made in view of the above points, and provides a BiCMO5 integrated circuit and a method for manufacturing the same, which are suitable for achieving high integration and ensuring latch-up resistance by reducing the collector capacitance and introducing a thin shrimp layer. The purpose is to realize the following.

Means for Solving Problem C] In order to achieve the above object, BiCMOS according to the present invention
The integrated circuit includes a semiconductor substrate, a first semiconductor layer formed on the substrate and having a conductivity type opposite to that of the substrate, and a depth that reaches the substrate, and a plurality of the first semiconductor layers. a second insulating region that is on the first semiconductor layer and has a depth that reaches the first semiconductor layer and does not reach the substrate; 1st. Second
a plurality of second semiconductor regions separated by an insulating region, a bipolar transistor is formed in the second semiconductor region separated by the first insulating region, and a bipolar transistor is formed in the second semiconductor region separated by the first insulating region; 2 insulation areas and the first
A field effect transistor is formed in a second semiconductor region separated by an insulating region.

Further, in the method for manufacturing a BiCMOS integrated circuit according to the present invention, a first conductive layer of a conductivity type opposite to that of the semiconductor substrate is formed on the entire surface of the semiconductor substrate of one conductivity type.
a step of forming a second semiconductor layer on the first semiconductor layer; forming a first insulating region having a depth that reaches the semiconductor substrate; and a step of forming a first insulating region that penetrates the second semiconductor layer and has a depth that reaches the first semiconductor layer and does not reach the substrate. forming a bipolar transistor in a second semiconductor layer separated by the first insulating region; and forming a bipolar transistor in a second semiconductor layer separated by the first insulating region; forming a field effect transistor in a second semiconductor layer separated by one insulating region.

[Function] In the present invention, there are grooves of two types of depth: a deep groove that reaches the substrate and a shallow groove that stops in the buried layer and does not reach the substrate, and the grooves are formed between the bipolar transistors and between the bipolar transistors and the NMO3. Alternatively, the bipolar transistor and PMOS are separated by a deep trench, and the NMO3
and PMOS are separated by a shallow trench. Such a configuration has the following effects.

a) An N buried layer under the P well for separating the P well and the P substrate is electrically connected to the N well. As a result, all N wells surrounded by P wells are electrically connected to each other by the low resistance N buried layer.

b) Due to the trench isolation effect, the current amplification factor of the parasitic lateral bipolar transistor, which uses the PMOS source as the emitter, the N-well as the base, and the P-well as the collector, is significantly reduced.

C) The resistance of the N well is reduced due to the effect of the N buried layer.

d) The parasitic capacitance generated between bipolar transistors, between bipolar transistors and NMO3, or between bipolar transistors and PMOS is smaller than in the case of PN junction isolation.

〔Example〕

Next, embodiments of the present invention will be described using the drawings.

It should be noted that this embodiment is merely an example, and it goes without saying that various changes and improvements may be made without departing from the spirit of the present invention.

FIG. 1 shows an example of a BiCMOS structure implemented in the present invention, in which 51 is a P-type semiconductor substrate, 52 is an N buried layer, 53 is a P well, 54 is an N well, 54. ! ,
tN type semiconductor region, 55 is N collector compensation region, 56
is the base region, 57 is the emitter region, 58 is the base compensation region, 59 is the source/drain of NMO8, 60 is PM
Source and drain of O3, 61 is a field oxide film, 6
2 is a gate oxide film, 63 is a gate electrode, 64 and 641 are thermal oxide films, 65 and 651 are CVD oxide films, and 66 is a P channel cuft region.

In other words, the embodiment shown in FIG. 1 has a specific resistance of 30 to 40 Ω・cm.
A N buried layer 52 with a thickness of about 2 μm doped with arsenic at a concentration of 1 to 5×10 I910 l9 is formed on a P substrate 51 of N-type epitaxial layer 54 with a thickness of 1 μm doped with N
Well 54. and the concentration of boron in the N-type epilayer is lX
10'' to IX10''cm-', a thickness of 2
0 nm thermal oxide film 64 and CV in the thermal oxide film 64.
They are insulated and isolated by a trench 68 with a depth of 1 μm in which a D oxide film 65 is buried. This separated N-type semiconductor layer 54
P-type source/drain region 60 and gate oxide film 62 inside
．． and a gate electrode 63 are formed, and furthermore, in the P-type semiconductor layer 53, an N-type source/drain region 59, a gate oxide film 62 . And an NMOSFET 72 having a gate electrode 63 is formed.

In addition, the N-type region 54 or the P-required region 53 and the N-type region 54
．． is a thermal oxide film 64. and C in the thermal oxide film 64I.
VD oxide film 65. They are separated by a groove 69 with a depth of 3.5 μm that reaches the P-type substrate 51 in which the P-type substrate 51 is embedded. At the bottom of this 3.5 μm deep groove, 5 x 10” to I
X 10"cm-' P with 1 degree of boron added
A channel Kate eTJ region 66 is formed. In the N-type region 541, there are
Collector compensation region 554 doped with phosphorus at a concentration of 19 cm-'(7) Base region doped with boron of 7 cm bow 56. Emitter region 57 doped with arsenic at a concentration of about I x 10" cm-3. About I x I
An NPN vertical bipolar transistor 73 including a base compensation region 58 doped with boron at a concentration of O'°c m-co is formed to have a BiCMOS structure.

In this way, according to the BiCMOS structure of this example, P
Thermal oxide film 64 reaches the mold substrate 51. .

A deep groove 69 containing the CVD oxide film 651 and a deep oxide M64 that stops in the N3 buried layer 52 and does not reach the substrate 5 layer.
．． cvI) It has grooves of two different depths, a shallow groove 68 containing an oxide film 65, and the bipolar transistors 73 are separated from each other, the bipolar transistors and the NMOSFET 72, and the bipolar transistor 73 and the PMO3FET 71 are separated by the deeper groove 69, NMOSFET72 and PMOSF
The ETs 71 can be separated by shallow grooves 68.

As a result, the N-embedded bTfi 52 under the P well 53 for separating the P well 53 and the P type group Fi 51 is
Connected to N well 54. Therefore, the N-wells 54 surrounded by the P-wells 53 are all electrically connected by the low-resistance N buried layer 52, resulting in an advantage that the resistance of the N-wells 54 is reduced.

In addition, due to the effect of the groove separation mentioned above, PMO3FET71
The current amplification factor of the parasitic lateral bipolar transistor with the source as the emitter, the N well 54 as the base, and the P well 53 as the collector becomes significantly smaller. This has the advantage that the parasitic capacitance generated in the isolation portion between the PMO3FET 73 and the PMO3FET 71 is smaller than that in the case of PN junction isolation.

Next, an embodiment of the method for manufacturing the structure of the present invention is shown in FIG. 2, and will be explained below in order of steps. In Figure 2, the same symbols as in Figure 1 indicate the same or corresponding parts, and 67 is N.
°P well 53 on the buried layer 52. This is an N-type epitaxial layer for forming an N-well 54 and an N-type semiconductor head 54°.

FIG. 2(a): First, a N buried layer with an impurity concentration of 1 to 5 x 10" cm is formed on the entire surface of the P-type substrate 51 doped with boron with a specific resistance of 30 to 4 ohm-cm by arsenic diffusion and heat treatment. 52 is formed. The thickness of this buried layer 52 is approximately 2 μm.
Diffusion conditions and heat treatment conditions are controlled to achieve the desired results. Then, by epitaxial method, phosphorus is added to I x 10"
An N-type epitaxial layer 67 doped with a concentration of cm-' is deposited to a thickness of about 1 μm.

FIG. 2(b). Next, after forming an element region by the well-known LOCO3 method, an etching mask for forming a shallow groove 68 for isolation is formed by a well-known lithography method, and then a reaction layer is formed. Reactive ion etching (RI)
A groove 68 having a depth of approximately 1 μm is formed using the etching mask described above by method E). Subsequently, an etching mask for forming a deep groove 69 for isolation is formed, and using the above etching mask by RIE method,
A groove 69 with a depth of about 3.5 μm is formed. Next, using the above etching mask as a mask, a dose of 5 x boron is applied to the bottom of the groove 69 with a depth of 3.5 μm from a direction perpendicular to the substrate.
After ion implantation at 900°C, 3 cm
Perform 0 minute annealing to open P+ channel) 9M area 6
form 6.

FIG. 2(C); Next, after oxidizing the groove surface by about 20 nm,
Oxide film 65.65. is deposited until the grooves 68 and 69 are completely filled. After that, the wafer surface (,V
The D oxide film is removed by a known method such as RIE. Next, an ion implantation mask for forming the P well is formed by a known lithography method, and boron is implanted at 200 to 300 keV using the ion implantation mask. Acceleration energy I x 10" - I x 1014cm
-” After ion implantation at a dose of 1000℃, 30℃
P-well region 53 is formed by performing annealing for about 1 minute.

FIG. 2(d); After that, NMO3FET?
2, a PMO3FET 71 in the N-well region 54, and an N-type semiconductor region 54. NPN bipolar transistor 73
By forming the iCMO as shown in FIG.
3 structures can be created.

〔Effect of the invention〕

As described above, the present invention has the following effects.

(a) Since the N-type buried layer under the P-well for separating the P-well and the P-substrate is electrically connected to the N-well, there is a problem with the prior art (Fig. 4) mentioned above. Not only is there no need to make a new contact in the P-well with the N-type buried layer under the P-well, but all N-wells are connected by a low-resistance buried layer, so each N-well has its own well. There is no need to make contact, allowing for higher density.

(b) The current amplification factor of the lateral parasitic bipolar transistor can be reduced due to the effects of I isolation and the highly doped buried layer.
Launch amplifier resistance in the CM OS SL region can be improved.

(c) Since isolation is performed using an insulator, the isolation area is small, enabling high-speed operation, and the isolation area is small (high density can be achieved).

As described above, according to the present invention, it is possible to reduce the collector area, introduce a thin shrimp layer, and achieve high integration, which was not possible with the conventional device structure of a B i CMO3 integrated circuit in which the P well is separated from the P substrate. It is possible to simultaneously achieve improvements in oxidation and rough lump resistance.

[Brief explanation of the drawing]

FIG. 1 is a structural cross-sectional view showing an example of a BiCMOS structure implemented according to the present invention, FIG. 2 is a process cross-sectional view showing an example of a method for manufacturing the structure of the present invention, and FIGS. FIG. 3 is a cross-sectional view showing two typical examples of BiCMO5 structures in which a well is separated from a P substrate. 51...P-type semiconductor substrate, 52...N buried layer, 5
3...P well, 54...N well, 54.・
...N-type semiconductor region, 56...Base region, 57...
- Emitter region, 59... Source/drain of NMO3, 60... Source/drain of PMO8, 61...
・Field oxide film, 62...Gate oxide film, 63・
...Gate oxide film, 64, 64. ...thermal oxide film, 65
゜651...CVDM film, 67...N type epi layer,
68..., shallow groove, 69... deep groove, 71...P
MO3FET, 72...NMO5FET, 73...
bipolar transistor. *2 Ward (d) 1 procedural amendment)

Claims (2)

[Claims] (1) a semiconductor substrate; a first semiconductor layer formed on the substrate and having a conductivity type opposite to that of the substrate; and a plurality of first semiconductor layers having a depth reaching the substrate; a second insulating region that is on the first semiconductor layer and has a depth that reaches the first semiconductor layer and does not reach the substrate; a plurality of second semiconductor regions separated by first and second insulating regions, and a bipolar transistor is provided in at least one of the second semiconductor regions separated by the first insulating regions. a second insulating region formed and separated by the second insulating region or the second insulating region and the first insulating region;
A BiCMOS type semiconductor integrated circuit device, characterized in that a field effect transistor is formed in at least one of the semiconductor regions. (2) a step of forming a first semiconductor layer of a conductivity type opposite to that of the substrate over the entire surface of a semiconductor substrate of one conductivity type; a step of forming a second semiconductor layer on the first semiconductor layer; forming a first insulating region having a depth that extends through the semiconductor layer and the first semiconductor layer and reaches the semiconductor substrate; and a step that penetrates the second semiconductor layer and reaches the first semiconductor layer. forming a second insulating region having a depth of up to and not reaching the substrate; forming a bipolar transistor in a second semiconductor layer separated by the first insulating region; A BiCMOS type semiconductor integrated circuit device comprising a step of forming a field effect transistor in a second insulating region or a second semiconductor layer separated by the second insulating region and the first insulating region. Production method.