JPH0443732A - Pattern detection circuit - Google Patents

Abstract

PURPOSE:To reduce the circuit scale comparatively small even when a pattern length is long by providing a means operating a pattern comparator circuit with an output of a pattern detection circuit so as to detect a pattern in total N+M bits. CONSTITUTION:When a head N-bit of a specific pattern is found out in an input data 3, a pattern detection circuit 1 outputs a head pattern detection signal 5 and a pattern comparator circuit 2 applies remaining M-bit pattern comparison of the specific pattern succeedingly by using the signal and outputs a pattern detection signal 6 when data of M-bit are all coincident. Thus, the pattern detection circuit in L(=N+M) bits is formed in this way. That is, the initial N bits of the input signal are used to apply a pattern detection of N sets of storage devices and succeeding M bits are used to make pattern detection by a pattern comparator circuit comprising of M-bit pattern generating circuit and one-bit comparator. Thus, even when the pattern length is long, the pattern is detected with a pattern detection circuit with a comparatively small circuit.

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to a pattern detection circuit that is used for frame synchronization detection in data communication equipment, etc., and outputs a signal when a specific pattern exists in input data.

BACKGROUND OF THE INVENTION In recent years, data transmission has become faster and more accurate due to the increase in information data and the development of high-speed transmission lines. In particular, in order to ensure accurate data transmission,
Generally, transmissions are sent and received while checking a specific pattern of signals.

FIG. 4 shows a conventional example of the pattern detection circuit.

Input data 3 is input to a shift register 7 consisting of a number of memory devices equal to the pattern length, and is sequentially shifted to a subsequent stage by an input clock 4.

The outputs of all the stores are input to the comparator 8, and the outputs of all stores are given a certain pattern (in this example, 101011001101100o11o10111
pattern), a pattern detection signal 6 is output.

In this way, a pattern detection circuit that outputs a pattern detection signal when a certain specific pattern exists in input data is configured using a shift register.

Problems to be Solved by the Invention However, in the conventional pattern detection circuit described above,
When trying to detect a pattern with a pattern length of L, an L-stage shift register and an L-bit comparator are required, and there is a problem that the circuit scale increases in proportion to the pattern length. was.

The present invention has been made with the above-mentioned problems in mind, and an object of the present invention is to provide a pattern detection circuit with a relatively small circuit scale even when the pattern length is long.

Means for Solving the Problems In order to achieve the above object, the present invention uses a pattern detection circuit of the same type as the conventional example only for detecting the first N pinos of a pattern, and then uses a pattern generation circuit for N bits. A pattern detection circuit with a pattern length n (2N+M) is constructed by cascading a pattern comparison circuit consisting of a 1-bit comparator and a 1-bit comparator.

Operation The pattern detection circuit of the present invention having the above configuration can be used in conventional N memory devices having a sufficient number of bits to prevent the first part of an input specific pattern signal from being mistaken for an initial setting signal such as bit synchronization. In the second half, a pattern comparison circuit consisting of an N-bit pattern generation circuit and a 1-bit comparator performs serial pattern detection. In particular, when detecting a pattern with a large pattern length, the conventional pattern detection circuit, which has a large circuit scale, can be minimized, and the remaining part can be replaced with a pattern comparison circuit, which has a relatively small circuit scale. The circuit scale is smaller than that of the conventional example.

EXAMPLE Hereinafter, an example of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of one embodiment of the present invention.

As shown in Fig. 1, the four ear components 1 are an N-bit pattern detection circuit of the same type as the conventional example, and 2 is an N-bit pattern comparison circuit consisting of a pattern generation circuit and a 1-bit comparator, which are connected in cascade. is connected to L(=N
+M) bit pattern detection circuit.

In this block diagram, when the first N bits of a specific pattern are found in the input data 3, the pattern detection circuit 1 outputs the first pattern detection signal 5. Compare N-bit patterns.

When all N bits of data match, a pattern detection signal 6 is output.

In this way, an L (=N+M) bit pattern detection circuit is configured.

The pattern detection circuit configured as described above will be explained in more detail with reference to FIG. 2.

FIG. 2 is a detailed block diagram of one embodiment of the invention of FIG. This circuit follows the preamble 101o 1o1o110011o110oo1101011
This circuit detects a specific pattern having a length of 24, ie, 1, and operates substantially in the same manner as the circuit of the conventional example. In other words, the number of bits is shared by L
:24°N26. M: 18.

As for the components, 1 has the same format as the conventional example, and is a detection circuit with a pattern (101011') with a length of 6 bino.
The N bits in FIG. 1 are implemented as 6 bits. 2 is a pattern comparison circuit with remaining p18 bits, and this is a specific configuration in which N bits in FIG. 1 are 18 bits. 14 is a pattern generation circuit, 13 is a memory indicating whether or not the pattern comparison circuit is in operation, and 9 is a 6-pisoto counter, which is set to an initial value of 14. 10 is a decoding circuit, and 111ri is a 1-bit comparator.

The relative operations of the constituent elements will be explained below using the flowcharts of FIGS. 2 and 3. Initially, the counter 9 is prohibited from operating due to the ON output of the memory 13.

The input data signal 4 shown in FIGS. 3a and 3b is input to the shiba turn detection circuit 1 by the input clock 3. This circuit has the same format as the conventional example described above except that the detection pattern length is 6 bits.If the data contains the first 6 bits 101011 of a specific pattern, the beginning of the pattern shown in Figure 3C is detected. Signal 6 is output.

When the leading pattern detection signal 6 becomes 0 level, the memory 1
The stored data of 3 changes, changing the QN output of FIG. Therefore, from the falling edge of the next input clock 3, the counter 9 becomes 14, 15.
, 16, 17°..., 31 and start counting as shown in Figure 3e. The count value is input to the decoding circuit 10, decoded and corresponding to FIG.
As shown in the figure, a pattern signal 12 (pattern 001101100011010111) which is the output of the decoding circuit 10 is output. The 1-bit comparator 11, which serves as a detection means for checking the suitability of the pattern as a final output, compares the output pattern signal 12 with the input data 4 as shown in FIG. 1
3 is changed, and the operation of the counter 9 is prohibited again to return to the initial state. When all the data match and the count value reaches 32, the pattern detection signal 6 shown in the third diagram is output.

As described above, 6-bit pattern detection circuits 1 and 1
A 24-bit pattern detection circuit is constructed using an 8-bit pattern comparison circuit 2.

In this way, the detection of 24-bit patterns is now easier than before.
This can be achieved with a simple configuration. Note that the leading pattern detection circuit 1
It would seem that it would be better to reduce the circuit size by allocating the length of the leading pattern to be handled and detected to be shorter than 6 bits, but in the case of this embodiment, it cannot be made any shorter to avoid the risk of malfunction. In other words, if the leading pattern is assigned to 6 bits of 10101, 1o1o1, which includes the preamble period located before the initial setting signal such as bit synchronization of data transmission, will be detected as the leading pattern. There is a risk of failing to detect a specific pattern.The number of bits to be used as the length of the leading pattern is determined depending on the pattern to be detected.

Effects of the Invention As is clear from the above explanation, the present invention detects a pattern with N memories for the first N bits of an input signal, and then detects a pattern with an M bit pattern generation circuit for the M bits.
By detecting a pattern using a pattern comparison circuit using a bit comparator, conventional circuits can detect two memory devices, for example.
The circuit of the present invention requires only 13 memories, 6 for the leading pattern detection circuit 1 and 7 for the pattern comparison circuit 2, reducing the circuit scale.

This effect becomes more pronounced as the length of the detected pattern becomes longer. In the conventional circuit, the circuit scale increases in proportion to the length of the pattern, whereas in the circuit of the present invention, the circuit scale does not increase so much.

As described above, the present invention has the effect of realizing a pattern detection circuit with a relatively small circuit scale even when the pattern length is long, and is effective in practice.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of the present invention, FIG. 2 is a detailed block diagram of the embodiment, FIG. 3 is a timing chart of the embodiment, and FIG. 4 is a block diagram of a conventional example. 1... pattern detection circuit, 2... pattern comparison circuit, 7... shift lens star, 8...
Comparator, 11... 1-bit comparator, 14...
...Pattern generation circuit. Name of agent If Shigetaka Awano and 1 other person Q
)

Claims (1)

[Claims] An N-stage shift register consisting of N memories;
an N-bit pattern detection circuit consisting of an N-bit comparator that generates an output when the outputs of two memory devices match a certain pattern; and an M-bit pattern detection circuit consisting of an M-bit pattern generation circuit and a 1-bit comparator. A pattern comparison circuit comprising: a detection means for detecting a pattern of N+M bits in total by operating the pattern comparison circuit based on the output of the pattern detection circuit.