JPH0443672A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE:To obtain a Bi-CMOS semiconductor device provided with a CMOS element of a high breakdown strength in a small number of processes by a method wherein a MOS transistor for the CMOS element is constituted of the following: a first region whose drain and source are at the same depth; and a second region which is deeper than the first region. CONSTITUTION:The drain of an N-channel MOSFET 400a (a P-channel MOS FET 400b) of a CMOS transistor 400 is constituted of the following: a first region 155a (165a) of an N<+> type (a P-type) drain whose depth from the surface of a well is at the same depth as that of a source region 156 (166); and a second region 155b (165b) of an N<+> (a P-type) drain whose depth from the surface of the well is deeper than that of the first region 155a (165a) of the N<+> type (the P<+> type) drain. The source region 156 and the first drain region 155a for the N-channel MOS transistor 400a of the CMOS element 400 as well as the P<+> type source region 166 and the first region 165a of the P<+> type drain for the P-channel MOS transistor are formed simultaneously by the respectively same process.

Description

DETAILED DESCRIPTION OF THE INVENTION (41J Essential) The first invention (claim 1) is based on the same semiconductor substrate.
In a semiconductor device in which a bipolar element and a CMOS element are formed in a semiconductor device, a MOS transistor of an The second area is deeper than the area.
Due to the presence of the second region, the drain breakdown voltage is improved compared to the conventional one, and both the p-channel MOS transistor and the n-channel OS transistor of the CMOS device have a high breakdown voltage. This made it possible to transform the system into

A second invention (claim 2) provides a method for manufacturing a semiconductor device in which a bipolar element and an O3 element are formed on the same semiconductor substrate, in which a base of the first conductivity type of the hypo element and a CMOS a second region of the drain of the MOS transistor of the channel of the first conductivity type of the device is simultaneously formed, and an emitter of the second conductivity type of the bipolar device and a region of the drain of the MOS transistor of the channel of the second conductivity type of the CMOS device are simultaneously formed. By forming the second region at the same time, the drain of the CMOS element can be formed at the same depth as the source on the channel side (depth from the well surface) and from the first region. and a second region formed deeply adjacent to each other, the CMO has a high drain breakdown voltage.
A Bi-CMOS type semiconductor device having an S element can be manufactured using fewer photolithography steps and fewer ion implantation steps than conventional ones.

The third invention (claims 3.4 and 5) provides a semiconductor device in which a bipolar element and a CMOS element are formed on the same semiconductor substrate, in which the CMOS element is placed in the first CMOS element.
element and its second element, which has a higher drain breakdown voltage than the CMOS element.
This has the advantage of increasing the degree of freedom in circuit design. Further, the second CMOS element is the CMOS of the first invention described above.
It has the same configuration as the element.

Furthermore, in a fourth invention (claim 6), a bipolar element, a first CMOS element, and a second CMOS element having a drain breakdown voltage higher than that of the first CMOS element are formed on the same semiconductor substrate. In a method of manufacturing a semiconductor device, a base of a first conductivity type and a base of a second conductivity type of a bipolar element are connected to each other.
The second region of the drain of the MOS transistor of the first conductivity type channel of the CMOS device is simultaneously formed, and the emitter of the second conductivity type of the bipolar device and the second CM
By simultaneously forming the second region of the drain of the MOS transistor of the second conductivity type channel of the OS element, the drain having a higher drain breakdown voltage than the first CMOS element and the first CMOS element can be formed. A Bi CMOS device in which two types of CMOS devices are mixed: a first region having the same depth as the source from the well surface and a second region having a second region deeper than the first region. -CMOS
A type semiconductor device can be manufactured using fewer photolithography steps and ion implantation steps than conventional Bi-CMOS type semiconductor devices.

[Industrial Field of Application] The present invention relates to a method of manufacturing a semiconductor device, and particularly to a method of manufacturing a semiconductor device, in particular a semiconductor device in which a bipolar element and a CMOS element are formed on the same substrate.
The present invention relates to an i-CMOS type semiconductor device and its manufacturing method.

[Conventional technology]

As MOS FETs become smaller (shorter channels), high energy carriers (electrons and holes) generated by the electric field strength in the channel are injected into the gate oxide film (Si02) or the 5SiO2 interface. The hot carrier effect caused by this becomes a problem.

That is, pot carriers with high energy are injected into and captured in the gate oxide film, and cause changes in device characteristics (dark voltage V, mutual conductance C, etc.) over time.

In order to prevent such characteristic fluctuations due to hot carriers, attempts have been made to reduce the peak electric field strength of the lnylain depletion layer that occurs in the pinned-off state.

Figure 5 shows an example of such a MOS FET.
It is.

In the figure, l is a P-type silicon substrate or ■) well;
2 is an N° type drain region 3 is an N° source region, 4 is a data 1 to oxide film consisting of S, 0□, 5 is a Pony-5i
It is a gate. Then, on the channel side of the N-type drain region, there is an N-type drain jlJA with a low impurity concentration.
6 is formed shallower than the N1 type drain region 2. Furthermore, the N" type drain region 2 and the N" source region 3 are formed at the same depth.

In this way, by providing the shallow N-type drain region 6 with a low impurity concentration formed on the channel side, the depletion layer is extended toward the drain side, and the voltage received by the substrate side is reduced, and the voltage near the drain is reduced. By relaxing the electric field at the source, the withstand voltage between the source and drain is increased.

Next, a method for manufacturing an M(IS + transistor) Bi CMOS lcO'J having the structure shown in FIG. 5 will be explained with reference to FIGS. 6(a) and 6(f). do.

First, as shown in FIG. 3 (3), a predetermined dose of Δ and ions are implanted into a p-type silicon substrate through a Hanwha oxide film to form two N implanted layers separated by a predetermined distance. do. Subsequently, these N-type implantation layers are driven into the P-type silicon substrate 1, and the N-type buried layer i11.1 is formed.
form 2. Then, the N buried layers 11 and 12 are formed by epitaxial growth.
On a P-type silicon substrate 1, an N-type epitaxial layer 13 with a low impurity concentration is formed. In this step, one mask is used to selectively form the N-buried layers 11 and 12.

Next, as shown in FIG. 1 (1)), the N-type epitaxial layer 1 is
A P-type well 14 and an N
A type well 15 is formed, and an N type sink collector layer 17 is further formed on the left corner of the N type buried layer 11. Further, between the N'' buried layer 11 and the N'' buried layer 12, a P layer is provided for electrically separating the bipolar 1 to transistor section 100 and the CMOS transistor section 200, which will be formed later by ion implantation, drive-in, etc. A type isolation layer 16 is formed so as to be connected to the P- type silicon substrate 1.

In this step, one mask is used for forming the above-mentioned)- type isolation layer 16, one for forming P-type well 14, and one mask for forming N-type isolation layer 16.
A total of four sheets are used, one for forming the type well 15 and one for forming the N'' type sink collector layer 17. Further, the N-type epitaxial layer 13 is formed by a P-type isolation layer 16, so that the bipolar 1-transistor section 1
N-type epitaxial layer 20.00 is formed. CMO
It is separated into an N-type epitaxial layer 30 in which an S transistor section 200 is formed.

Furthermore, as shown in FIG. 2C, a P-type base 2I is formed in the N-type epitaxial layer 20, and P-type channel cut layers 31 and 3 are formed at both ends of the surface of the P-type well 14.
1 are formed simultaneously. In addition, the above P゛ type base Jm2
An N-type emitter 22 is formed in the N-type well 15, and N-channel cut layers 32 and 32 are formed at both ends of the surface of the N-type well 15 at the same time.

Then, using the silicon nitride film C3r3Na) as a mask, thermal oxidation is performed to obtain LOC ("l5 (Local
A field oxide film 41 is selectively formed using the oxidation of silicon method. In this step, one mask is used for forming the P'' base layer 21 and the P'' channel cut 1-ji31, and one mask is used for forming the N'' type emitter 22 and the N'' type channel power/ant layers 32, 32. 1 piece, 1 piece silicon nitride (1 piece for butter j-ing)
In total, 1-t-3 masks are used.

Next, as shown in the same figure (d), the r1 channel MO
5FET 200δ gate (oxide film 54, p channel
and the above-mentioned data 1 to oxide film 54°64 on the N-type well 15.
10, each n-channel MO5FET 20 Oa
Poffy-5i game (・51, p channel MO
A Pofy-5i gate 61 for 5FET is formed in four dimensions. Furthermore, the Pony-5i gate 51 and Pony
Using the -5i gate 61 as a mask, the self-alignment technology is applied.
ogy), an n-nayan metal MO is formed in the P-type well 14.
N-type region 5 which becomes N-type source and drain of 5FET
2.53, N J, P channel MO3F in Le 15
Y serves as the P-type source, drain and input of ET 200 b.
>-forming mold regions 62,63; During this time (
Well, for forming the Pofy-3i gate 5161, the above N
One mask is used for forming the type region 52.53 and the P type region 62.63, so a total of three masks are used. Also, -1, Poj2y-5
The i-gate 5161 is doped (added) with phosphorus (P).

Furthermore, as shown in the same figure ((2)), the high impurity concentration N5-Yannel M [JS FET 200a]
゛゛Arsenic (As) or phosphorus (P) is added to the parts forming the source 5G and drain 55b to prevent p channel] 5F
After ion-implanting boron (B) at 15HF into the portions of the ET200a where the high impurity concentration l)-type source G6 and paralayer 65b are to be formed, drive-in is performed to form the p-type well I4. n-channel MO5FET 20
0a N-type source 56, N-type tray: 155a,
At the same time as forming an N-type drain 55F, a P-channel MOS F is formed in the N-type drain 55.
)-type source 66, (2)-type 1 Ruin 65a, and P'-type drain 65b are formed. In this stage I, the high impurity concentration N-type drain 5b, the high impurity +J? A
A total of two masks are used for ion implantation to form each of the P' type drains 65b.

Then, as shown in the same figure (f), PS is applied to the entire surface.
After forming an interlayer insulating film 71 such as G, contact holes for wiring electrodes are formed in the interlayer insulating film 71. Then, after depositing A1 alloy or the like to a predetermined thickness over the entire surface by sputtering or the like, the collector electrode 23, base electrode 24, and emitter electrode 25 of the bipolar NPN transistor 100 are formed by photolithography. At the same time, n-channel MOS-FE
T 200 a source electrode 59, drain electrode 57,
Then, the source electrode 58 and drain structure 60 of the P-channel MO5FET 200b are selectively formed.

[Problem to be solved by the invention]

As described above, in order to increase the withstand voltage between the source and drain, the n-channel M of the CMOS transistor 200 is
The drain of the OS FET 20 Da and the drain of the n-channel MOS FET 200 b are connected to a low impurity N-type drain 55a and the N-type drain 5, respectively.
A high impurity concentration N-type drain 1/in 55b which is deeper than the well surface than the well surface 5a; In the case of a structure consisting of a deep high impurity concentration P-type drain 65b, the low impurity concentration N
In order to form the - type drain 55a and the P- type drain 65a, two steps, a photolithography step and an ion implantation step, are required. That is, n-channel MOS FET 200a, , P-channel MO5
Since the above two steps are required on each FET 20Ob, CMOS with a normal drain structure
A total of four additional steps are required compared to transistors. Therefore, this causes a decrease in yield and an increase in manufacturing costs.

The present invention provides B
i-(: A first object of the present invention is to provide a first semiconductor device and a method for manufacturing the first semiconductor device that can manufacture an MOS type semiconductor device with a smaller number of steps than conventional ones, and further , a first CMOS device and its first CMOS
A second semiconductor device capable of manufacturing a Bi-CMOS type semiconductor device having a second CMOS element having a drain breakdown voltage higher than that of a semiconductor with a smaller number of IT elements than before, and a second semiconductor device thereof. A second object is to provide a method for manufacturing a semiconductor device.

(One Step for Solving the Problems) The first invention provides bipolar elements and CMOS devices on the same semiconductor substrate in order to achieve the first object (semiconductor device) of
In a semiconductor device in which a MOS element is formed, the C
The drains of the MOS transistors of the first conductivity type channel and the second conductivity type channel of the MOS transistor include a first region on the channel side whose depth from the well surface is the same as that of the source, and the first region. a second region adjacent to the well surface and deeper than the first region and adjacent to the first region; The region No. 2 has the same depth from the well surface as the base of the first conductivity type of the bipolar element, and has the same depth as the base of the second conductivity type channel. - the second region of the ruin of the transistor is
The depth from the well surface is the second depth of the bipolar element.
It is characterized by having the same depth as the conductive type emitter.

Furthermore, in order to achieve the first object (method for manufacturing a conductor device), a second invention provides a method for manufacturing a semiconductor device in which a bipolar element and a CMOS element are formed on the same semiconductor substrate. In the method, simultaneously forming a base of the first conductivity type of the bipolar element and a second region of the ruin (of the MO'il transistor of the MO'il transistor of the first conductivity type channel); The second conductivity type of the bipolar element and the second conductivity type of the CMOS element are the MOS 1 transistor's 1-rain second transistor.
One culm that forms the head area at the same time, and IjiI ('MO
The sorter of the S-type first conductivity-type -y-type MOS transistor and the first region of the ruin on the channel side are connected to each other by a distance 77 from the well surface of the AI first conductivity-type transistor. , 7. than the second region of the L line of the MIIS+ transistor. (a step of simultaneously forming the CMOS so that and simultaneously forming the second conductivity type channel so that the depth of the second conductivity type channel is shallower than the second region of the drain of the transistor.

Furthermore, a third invention provides a semiconductor device in which a bipolar element and an 0MO5 element are formed on the same semiconductor substrate in order to achieve the second object (semiconductor device), in which the 0MO5 element comprises: A first 0MO5 element and a second 0MO5 element having a higher drain breakdown voltage than the first CMOS element.
The device is configured to include an element.

In the second 0MO5 element, for example, as described in claim 4, the drains of the MOS l transistors of the first conductivity type channel and the second conductivity type channel of the second 0MO5 element have a depth from the well surface. A first region of the channel example has the same depth as the source, and a second region is deeper than the first region from the well surface and is adjacent to the first region. . For example, the second region of the drain of the MOS transistor of the first conductivity type channel has the same depth from the well surface as the base of the first conductivity type of the bipolar element, and The second drain of conductive type Janel MOS transistor
The region has the same depth from the well surface as the second conductivity type emitter of the bipolar element.

A fourth invention provides a method for manufacturing a bipolar element, a first 0MO5 element, and a first CM element on the same semiconductor substrate in order to achieve the second object (method for manufacturing a semiconductor device).
In a method of manufacturing a semiconductor device in which a second 0MO5 element having a higher drain breakdown voltage than an OS element is formed, a MOS transistor of a first conductivity type base of the bipolar element and a first conductivity type channel of the second 0MO5 element. a step of simultaneously forming a second region of the drain of the bipolar element, an emitter of the second conductivity type of the bipolar element and the second region of the drain of the bipolar element;
a step of simultaneously forming a second region of the drain of the channel MOS transistor of the second conductivity type of the IO5 element; The depth from the well surface is the drain of the MOS transistor of the first conductivity type channel of the second CMOS element. the source and drain of the second conductivity type channel MOS transistor of the first CMOS element, and the source and drain of the second conductivity type channel MOS transistor of the first CMOS element;
: The first region of the drain of the MOS transistor of the second conductivity type channel of the MOS element is defined as its well surface, j, and the depth of the MOS transistor of the second conductivity type channel of the second MOS element. The second region of the drain is formed at the same time so as to be shallower than the second region of the drain.

[For A1] In the first invention, the drain of the MOS transistor of the 0MO5 element is connected to the first region of the channel example whose depth from the well surface is the same as the source, and from the well surface to the drain of the MOS transistor of the 0MO5 element. Since the second region is deeper than the first region, a high drain breakdown voltage can be obtained due to the presence of the second region.

Further, in the second invention, in the method of manufacturing a semiconductor device in which a bipolar element and an 0MO5 element are formed on the same semiconductor substrate, the base of the first conductivity type of the bipolar element and the first conductivity type of the 0MO5 element are formed. The second region of the drain of the MOS transistor of one conductivity type channel is simultaneously formed in the same process, and the second region of the drain of the bipolar element is formed simultaneously.
A 1-conductivity type emitter and Mf]S) of the second conductivity-type channel of the 0MO5 element to the second region of the transistor are also formed simultaneously in the same process. Therefore, the number of photolithography steps can be reduced by two compared to the conventional method, and the number of ion implantation steps can also be reduced by two.

Furthermore, in the third invention, since the first 0MO5 element and the second 0MO5 element having a higher drain breakdown voltage than the first 0MO5 element are mixed on the same semiconductor substrate, the circuit The degree of freedom in editing can be increased compared to before.

In the fourth invention, a bipolar element, a first 0MO5 element, and a second CM having a drain breakdown voltage higher than that of the first 0MO5 element are arranged on the same semiconductor substrate.
In the method of manufacturing a semiconductor device in which an OS element is formed, a base of a first conductivity type of the bipolar element and a base of the second conductivity type are formed.
A second region of the drain of the first conductivity type channel of the CMOS device is simultaneously formed in the same process, and an emitter of the second conductivity type of the bipolar device and the second conductivity type of the second CMOS device are simultaneously formed. The channel of the MOS transistor and the second region of the drain of the transistor are formed in the same process. For this reason, the first side O5 element and its drain, which has a higher drain breakdown voltage than the first CMOS element, are connected to the first region where the drain has the same depth as the source (depth from the well surface), and two types of CMOS of the second CMOS element consisting of a second region deeper than the region and adjacent to the second region;
A Bi-CMOS type semiconductor device with a mixture of elements and other elements is replaced by a Bi-CMOS type semiconductor device that has only conventional high drain breakdown voltage CMOS elements.
It can be manufactured using the same number of steps as the first invention, which is fewer than the i-CMOS type semiconductor device.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 shows Bi-CMO, JI, which is the first embodiment of the present invention.
FIG. 3 is a cross-sectional view schematically showing the configuration of C.

In the figure, 1 is a P-type silicon substrate, 20.3
0 is an N-type epitaxial layer epitaxially grown on the substrate 1 via an N-type buried collector layer 14 and an N-type buried layer 15, and the N-type epitaxial layer Ji20.30 is an isolation layer. The bipolar NPN transistor 300 and C
MOS) Forms an island area for Range Meta 400.

Reference numerals 14 and 15 designate a P well and an N well for each MO5FET, an N-channel MO5FET 400a and a P-channel MO5FET 400b, which are each diffused in the N-type epitaxial layer 30 of the CMOS transistor 400 example.

Further, 21 is the bipolar NPN transistor 3
A P′ type heavy layer 22 is selectively formed within the N − type epitaxial layer 200 of the N′ type buried collector layer IL on the 00 side, and a P′ type heavy layer 22 is selectively formed within the P′ type base layer 21 described above. The surface area of these base-collector junctions and the surface area of the base-emitter junction are covered with a field oxidation layer of sufficient thickness (e.g., 5000 Å or more). covered with a membrane 41, 15
is an N'' sink collector layer connected to the N'' type buried collector layer 11. In addition, 156 is each of the above C
N-channel MO5FET 400a formed in the N゛゛ epitaxial layer 30 on the MOSl-range metal 400 side
The source layers 155a and 155b are the first and second N-type drain regions, respectively, which become the drain of the N-channel MO5FET 400a. Another 54.5
1 is the gate oxide film and gate electrode of the N-channel MO5FET 400a.

Further, 166 is the source of the P-channel MO5FET 400b formed in the N-type epitaxial layer 30 on the side of the CMOS l-range metal 400, and 155
a 155b is P channel MO5FET 400b
The first region of P's drain, which becomes the drain of P.

This is the second area. Furthermore, 61.64 is the gate oxide film and gate electrode of the 1) channel MO5FET 400b. Further, reference numeral 71 denotes an interlayer insulating film such as a PSG film that covers each of these parts, and 59, 57.51'3.60 connects the source layers 56, 166 and the 1 Ruin area 155a
, 155b, 165a, and 165b are wiring electrodes made of aluminum or the like.

In addition, P well 1 of the above CMOS+-randisk 400
At both ends of the surface side of the N-well 15, there are P'-type channel cut layers 31, 31 for channels 1 to brim (gart ring), and at both ends of the surface side of the N well 15, channels (and brim (gart ring)) are formed. ) for N゛゛channel cut layer 32.3
2 is formed.

In this way, the Bi-CMOSIC of this embodiment has an N-channel M()S FET 400 a (
The drain of the P channel MO5FET 400 b) is located in the source region 156 (166
) with the same depth as the first H of the N-type (P-type) drain.
region 155a (165a), and a first region 155a of the N1 type (1)-type) drain that is deeper than the well surface.
(165a) and a second region 155b (165b) of a deep N" type (P" type) drain.
5b (165b), the electric field concentration in the vicinity of the drain is alleviated, resulting in a structure in which the withstand voltage between the source and the drain is increased. Furthermore, since the drain first region 154a (165a) has the same depth from the surface as the source region 156 (166), self-line technology using the gate electrode 51 (61) as a mask can be used. The source region 156 (16
6) and the drain first region 154a (165a) at the same time, the channel length can be easily controlled.

Further, as shown in FIG. 1, the N+ type drain second region 155b and the N' emitter layer 22 of the bipolar NPN transistor 300, and the P' type drain second region 165b and the P' base layer 21 of the bipolar NPN transistor. , and have the same depth from the surface, the N-type drain second region 155b can be formed simultaneously with the N-type emitter 122 of the bipolar NPN transistor 300 shown in FIG. Similarly, the second TiI region 165b and the P-type drain region 165b can be formed simultaneously with the P-base layer 21 of the bipolar NPN transistor 300 in the same process. Further, the N' source region 156 and the N' type drain first region 155a of the N-channel MOS transistor 400a, and the P+ type source region 166 and the P+ type drain first region 165a of the P channel MOS transistor 400b are each located at a depth from the surface. The source region 156 and first drain region 155a of the N-channel MOS transistor 400a of the CMOS device 400 and the P source region 16 of the P-channel MOS transistor are the same.
6 and the P' type drain first region 165a can be formed simultaneously in the same process.

Therefore, the Bi-CM[lS type semiconductor device having this high breakdown voltage CMOS transistor has a structure that can be manufactured with a smaller number of steps than the conventional one.

For example, the depth d of the first region 155a of the N-type source 154 and N-type drain shown in FIG. 2 is, for example, 0.5.
The width W1 of the middle channel region between the N' type source 54 and the N' type drain first region 155a is, for example, 4 μm. ) tm onwards.

Next, FIGS. 3(a) to 3(f) are manufacturing process diagrams showing a method for manufacturing a Bi-CMOSIC, which is an embodiment of the present invention.

First, a third image similar to that shown in FIGS. 6(a) and (t)) is shown.
Figure (a).

The manufacturing process shown in (t)) is carried out, and the P-type silicon substrate I
G-N embeddings 111 and 12 are formed, and the above-mentioned N
An N-type resin collector 15 is formed on the N-type buried layer 11, and a P-well 14 and an N-well 15 are formed on the N-type buried layer 12.

Next, as shown in FIG. 3C, a bipolar NPN transistor 300 is formed by thermal diffusion or ion implantation.
P' type base layer 21 of CMOS transistor 400, P' channel cut layer 31, 31 of N channel MOS FET 400a of CMOS transistor 400, and P channel MOSFET
A second region 165b of the 1] type drain of 400b is formed at the same time. Further, by thermal diffusion or ion implantation, the N emitter 22 of the bipolar N1 transistor 300 and the N emitter 22 of the N channel MOS FET 400a of the CMOS transistor 400 are separated.
7)・Second region 15 of layers 32, 32 and N゛゛l rain
5b is formed simultaneously. Then, a nitride film (S□N
, ) is used as a mask to perform thermal oxidation, and 1. a field oxide film 41 is selectively formed by the OCO5 method.

In this way, the P'' type base layer 21 of the high-volume transistor NPN 300 and the CMOS+ transistor 400
The second region 165b of the deep P drain of the P channel MOS FET 400b and the bipolar NPN
N emitter layer 22 and CM of transistor 300
N-channel MOS FET of OS transistor 400
The N-type drain second region 155b of 400a is formed simultaneously in the same process.

Subsequently, as shown in the same figure (d), a P channel M is formed in the P well 14 and the N well 15'' by thermal oxidation.
Gate oxide film 54 of OS FET 400a and gate oxide film 6 of N-channel MOS FET 400b
4, a buffer oxide film 42 is formed on the surface -L of the other N-type epitaxial layer. And then further,
After forming Poff1y-5i on the entire surface by CVD method etc., N-channel M
[]Poly-5i gate 51 of S FET 400a, P of P channel MOS FET 400b
Buttering o1y-5i61.

Then, as shown in FIG. 5E, a photolithography process and an ion implantation process (self-line process) using the gate 51 as a mask are performed to form the N' source layer 156 and the N' type drain second region 155b. An N° type drain first region 155a having a shallow depth from the L surface is formed at the same time, for example, to a depth of about 0.5 μm. Then, a photolithography process and an ion implantation process (self-line process) using the gate 61 as a mask are performed again to form the p'' type source layer 1.
66 and a P' type drain 1/in first region 165a having a shallower depth from the well surface than the P' type drain second region 165b are simultaneously formed.

Also, at this time, N-channel MOS FET 400
The channel length W2 between the N source layer 156 of a and the first region 155a of the N9 type drain, and the P channel M
P source layer 166 and N of OS FET 400b
Channel length W between °-type drain first region 165a
3 are formed so that they are both about 4/1 m or more, for example.

The N-type source layer 156 and the N-type drain first
The region 155a is formed by using the gate 51 as a mask and connecting the P'' source 166 and the P'' type drain first region 16.
5a are formed in a self-aligned manner using the gate 61 as a mask, so that the N-channel MO5FET 40
0 a channel length d and the above P channel MO5FET
The channel length d2 of can be controlled with great precision.

Then, as shown in FIG. 6(f), an interlayer insulating film 71 such as PSG is laminated on the field oxide film 41F in the same manner as in the steps of FIG. A contact pole is formed in the phosphorus-doped silicon oxide 71 by a lithography process. and,
After forming an Af gold alloy on the entire surface by a sputtering method or the like, a photolithography process is performed to form the collector electrode 233, base electrode 24, and emitter electrode 25 of the bipolar NPN transistor 300 made of the above i-alloy, etc., and the P-channel MOS FET 400. a source electrode 59, drain electrode 57, N-channel MOS
The source electrode 58 and drain electrode 60 of the FET 400b are patterned.

As described above, in this embodiment, the P'' type heavy layer 21 of the bipolar NPN transistor 300, the P channel M
The second region 165b of the P" drain of the OS FET 400b and the P" type channel cut layer 31, 31 are simultaneously formed in the same process, and the bipolar NPN
The transistor 300ON'-type conductor layer 22, the N-type drain second region 165t of the N-channel MOS FET 400a, and the N-type channel cant layer 32.
32 and 32 are formed at the same time at the same time (
(See Figure 1(C)). In addition, N-channel MOS FE
T400a N-type source layer 154, N-type drain first region 155a, and P channel MOS FE
The P-type source layer 166 of T and the first fi of P-type drain
The I area 165a is formed at the same time in the same process (see FIG. 3(e)).

For this reason, as in the past, the base of the bipolar NPN) transistor and the P channel M of the CMOS transistor are
Source and drain of O5FET and bipolar NP
Compared to the case where the emitter of the N-transistor and the source and drain of the N-channel MO5FET of the CMOS+ transistor are formed in separate processes, the photophosphor layer process is reduced by 2 and the ion implantation process is reduced by 2 (see Figure 3). C), (d), (e) and Figure 6 (C), (d
), see (e)).

Next, FIG. 4 shows a normal CMn5 transistor 50 which does not require a very high breakdown voltage, which is a second embodiment of the present invention.
0 and the high-voltage CMn5 h range meta 4000 Bi-CMOS in which two types of CMn5 transistors coexist
1 is a schematic diagram showing the configuration of an IC.

This Bi-CMn3 IC consists of a normal CMn5 I-transistor 400 and a high voltage CMn5 transistor 50.
0 is mixed, which has the advantage of increasing the degree of freedom in circuit design.

As shown in the figure, the CMOS 500 includes an N-channel Mn5 FET 500a and a P-channel MO5F.
ET500b, and these N channel M
[lS FET 500a and P channel MO5FE
The source and drain of T 500b can be formed by thermal diffusion or ion implantation using self-line technology using the gate as a mask.

In this case, the N-channel M of the CMOS transistor 400
n5 FET 400 aN” type source layer 156 and N
When forming the first region 155a of the "type drain," the N-channel Mn5 of the CMOS transistor 500 is formed.
The N1 type source layer 201 and the N' type drain N2O2 of the FET 500a are formed simultaneously, and the CMn5
Transistor 400 P-channel MO5FET40
0b P' source layer 166 and P' type drain first
When forming the region 165a, the CMo5 transistor 5
00 P channel Mn5 FET500 bo) P
``type source layer 301 and P0 type drain layer 302 may also be formed at the same time.

Note that the first and second embodiments are Bi-C in which bipolar NPN transistors and CMn5 transistors are mixed.
Although an example of a Mn5 IC, the present invention is not limited thereto, but is applicable to a Bi
-CMn5 IC is of course applicable.

〔Effect of the invention〕

As explained above, according to the first aspect of the invention, a Bi
- Since it is possible to manufacture a CMOS type O5 body device with fewer photolithography processes and ion implantation processes than before, the Bi-CMOS type O5 body device with the high drain breakdown voltage mentioned above can be manufactured.
This improves the production efficiency of body devices, making it possible to reduce costs.

Further, according to the second aspect of the invention, the semiconductor device of the first aspect can be manufactured with a reduced number of steps.

Furthermore, according to the third invention described in claim 3.4 or 5, the first CMn5 element and the second CMn5 element having a higher drain breakdown voltage than the first CMn5 element are arranged on the same semiconductor substrate. Since it is formed in a mixture of C and C, it has a higher degree of freedom in circuit design than conventional L, and has a drain breakdown voltage of 1 C.
A Bi-CMOS type O5 structure having a Mn5 element can be obtained.

Further, according to the fourth invention described in claim 6, two types of CMn5 elements, a first 40S element and a second CMn5 element having a higher drain breakdown voltage than the first CMrlS element, are mixed. The Bi-CMOS type O5 body device has been replaced with a conventional Bi-CMOS device having only a CMn5 element with high drain breakdown voltage.
Since it can be manufactured with fewer steps (reduced photolithography steps and ion implantation steps) than an 8-type semiconductor device, it is possible to manufacture a Bi-CMOS type O5 mounting surface with high applicability in a concentrated manner.

[Brief explanation of drawings]

FIG. 1 is a sectional view showing the structure of a Bi-CMn5 IC according to the first embodiment of the present invention, and FIG. 2 is a Bi-CMOS IC of the first embodiment of the present invention.
3(a) to 3(f) are manufacturing process diagrams illustrating the manufacturing method of the B knee CMOS IC of the first embodiment; The figure shows the configuration of a Bi-[':MO5IC according to another embodiment of the present invention. Figure 5 shows a conventional Mn5FET with high drain breakdown voltage.
Cross-sectional views showing the structure of transistors, FIGS. 6(a) to 6(f) are conventional high drain breakdown voltage CMOS+ transistors.
-'/7',; Bi-CMOSIC with star
□) It is a manufacturing process diagram explaining the manufacturing method. 155a...N-type 1-rain first region, 155b
...N゛゛Drain second region, 165a...-P''
First i'IJT region of type drain, 165b... Second region of P' type drain, 300... Bipolar NP
N+- transistor, 00° CMOS transistor, 400a. 00a ・N channel MO5 ET 00b. 500b/P channel MO5 ET

Claims (1)

[Claims] 1) In a semiconductor device in which a bipolar element and a CMOS element are formed on the same semiconductor substrate, the drains of the MOS transistors of the first conductivity type channel and the second conductivity type channel of the CMOS element are: a first region on the channel side that is deeper than the well surface; and adjacent to the first region, the first region is deeper than the well surface and adjacent to the first region. The second region of the drain of the first conductivity type channel MOS transistor has the same depth from the well surface as the first conductivity type base of the bipolar element. The second region of the drain of the second conductivity type channel MOS transistor has the same depth from the well surface as the second conductivity type emitter of the bipolar element. Semiconductor equipment. 2) In a method of manufacturing a semiconductor device in which a bipolar element and a CMOS element are formed on the same semiconductor substrate, the base of the first conductivity type of the bipolar element and the CMOS
a step of simultaneously forming a second region of the drain of the MOS transistor of the channel of the first conductivity type of the S element; and an emitter of the second conductivity type of the bipolar element and the second region of the drain of the MOS transistor;
a step of simultaneously forming a second region of the drain of the MOS transistor of the second conductivity type channel of the OS element; and a step of simultaneously forming the second region of the drain of the MOS transistor of the first conductivity type channel of the CMOS element
a region whose depth from the well surface is the second region of the drain of the first conductivity type channel MOS transistor.
a step of simultaneously forming a source and a drain on the channel side of the second conductivity type channel of the CMOS element;
forming a region at the same time so that the depth from the well surface is shallower than the second region of the drain of the second conductivity type channel MOS transistor. manufacturing method. 3) In a semiconductor device in which a bipolar element and a CMOS element are formed on the same semiconductor substrate, the CMOS element includes a first CMOS element and a first CMOS element.
A semiconductor device comprising a second CMOS element having a higher drain breakdown voltage than the MOS element. 4) The drains of the MOS transistors of the first conductivity type channel and the second conductivity type channel of the second CMOS element include a first region on the channel side having the same depth as the source from the well surface; 4. The semiconductor device according to claim 3, further comprising a second region deeper than the first region from the well surface and adjacent to the first region. 5) The second region of the drain of the MOS transistor of the first conductivity type channel of the second CMOS element has the same depth from the well surface as the base of the first conductivity type of the bipolar element. The second region of the drain of the second conductivity type channel MOS transistor is characterized in that the depth from the well surface is the same as the second conductivity type emitter of the bipolar element. semiconductor devices. 6) On the same semiconductor substrate, a bipolar element, a first C
In a method for manufacturing a semiconductor device in which a MOS element and a second CMOS element having a higher drain breakdown voltage than the first CMOS element are formed, the base of the first conductivity type of the bipolar element and the second CM
a step of simultaneously forming a second region of the drain of the MOS transistor of the first conductivity type channel of the OS element;
a step of simultaneously forming a second region of the drain of the MOS transistor of the second conductivity type channel of the CMOS device;
The source and drain of the OS transistor and the first region of the source and drain of the MOS transistor of the first conductivity type channel of the second CMOS element are connected to each other at a depth from the well surface of the second CMOS element. simultaneously forming a channel of the first conductivity type of the MOS transistor so that the channel is shallower than a second region of the drain of the MOS transistor;
The source and drain of the OS transistor and the first region of the source and drain of the MOS transistor of the second conductivity type channel of the second CMOS element are connected to each other by a depth from the well surface of the second CMOS element. Second
1. A method of manufacturing a semiconductor device, comprising: simultaneously forming a conductivity type channel of a MOS transistor so that the second region of the drain is shallower than the second region.