JPH0443662A - Semiconductor device and its manufacture - Google Patents

Semiconductor device and its manufacture

Info

Publication number
JPH0443662A
JPH0443662A JP15204390A JP15204390A JPH0443662A JP H0443662 A JPH0443662 A JP H0443662A JP 15204390 A JP15204390 A JP 15204390A JP 15204390 A JP15204390 A JP 15204390A JP H0443662 A JPH0443662 A JP H0443662A
Authority
JP
Japan
Prior art keywords
oxide film
semiconductor substrate
photomask
film
selective oxide
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15204390A
Other languages
Japanese (ja)
Inventor
Shigeru Okamoto
茂 岡本
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electronics Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electronics Corp filed Critical Matsushita Electronics Corp
Priority to JP15204390A priority Critical patent/JPH0443662A/en
Publication of JPH0443662A publication Critical patent/JPH0443662A/en
Pending legal-status Critical Current

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  • Local Oxidation Of Silicon (AREA)
  • Element Separation (AREA)

Abstract

PURPOSE:To reduce an interelement isolation width by a method wherein an oxide-film layer extended in the depth direction is formed under a selective oxide film for interelement isolation use. CONSTITUTION:An oxide film 12 is formed on the surface of a semiconductor substrate 11; a silicon nitride film 13 is deposited on the oxide film 12; an opening part is formed selectively in the part of an interelement isolation region. Then, a selective oxide film 16 is formed; the silicon nitride film 13 is removed; after that, a photomask 1 is formed; an opening part is formed selectively, by an etching operation, in a part near the center of an interelement isolation region of the photomask 1. Boron ions are implanted into the opening part to form a P-type impurity diffusion layer 2. Then, oxygen ions are implanted into the opening part of the photomask 1; an oxide-film layer 3 which comes into contact with the selective oxide film 16 and which is extended in the depth direction of the semiconductor substrate 1 is formed by an annealing operation. Then, the photomask 1 is removed; after that, an N-type impurity diffusion layer 17 to be used as a source-drain region is formed selectively. Thereby, it is possible to form the interelement isolation region whose isolation width is narrow and which does not lower the breakdown strength of elements.

Description

【発明の詳細な説明】 産業上の利用分野 本発明は、L OG OS (Local 0xida
tion ofSilicon)酸化工程により素子分
離領域を形成する半導体装置およびその製造方法に関す
Z0従来の技術 近年、半導体装置の高集積化・高密度化に伴ない回路素
子間の分離がますます重要になってきている。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention is directed to LOG OS (Local Oxida
Z0 Conventional technology regarding semiconductor devices and their manufacturing methods in which element isolation regions are formed by oxidation process In recent years, isolation between circuit elements has become increasingly important as semiconductor devices become more highly integrated and densely packed. It's coming.

従来、MOSトラ/ジスタ素子間の分離領域をL OG
 OSにより形成する際、シリコン・ナイトライドおよ
びフォトl/シストをマスクとしてホロンを選択的に分
離領域全体にイオンt+入することにより素子間の分離
を高める方法が知られている。
Conventionally, the isolation region between MOS transistors and transistor elements was
When forming by OS, a method is known in which the isolation between elements is increased by selectively injecting holons (t+) into the entire isolation region using silicon nitride and photol/cyst as masks.

Yノ下、従来の半導体装置およびその製造ツノ法につい
て第2図を参照しながら説明する。
Below, a conventional semiconductor device and its manufacturing method will be explained with reference to FIG.

第2図は従来の半導体装置の主要工程段階での素子分離
領域の断面図であり、11はP型/リコンで構成された
半導体基板、12は半導体基板]−】の表面に形成され
た酸化膜、13は酸化膜12の表面に選択的に形成され
たシリコン・ナイ]・ライド膜、14はシリコン・ナイ
トライド膜13の表面に選択的に形成されたフォトレジ
スト膜、15はP型不純物拡散層、16はLOCO8酸
化膜、17は半導体基板11の表面に選択的に形成され
たN型不純物拡散層を示す。
FIG. 2 is a cross-sectional view of the element isolation region at the main process stage of a conventional semiconductor device, in which 11 is a semiconductor substrate made of P-type/recon, and 12 is an oxide formed on the surface of the semiconductor substrate. 13 is a silicon nitride film selectively formed on the surface of the oxide film 12, 14 is a photoresist film selectively formed on the surface of the silicon nitride film 13, and 15 is a P-type impurity. A diffusion layer 16 is a LOCO8 oxide film, and 17 is an N-type impurity diffusion layer selectively formed on the surface of the semiconductor substrate 11.

すなわち、従来の半導体装置では第2図(alに示すよ
うに、半導体基板11の表面に酸化膜12を形成し、そ
の上にシリコン・ナイトライド膜]3およびフォトレジ
スト膜14を形成する。つぎに、フォトリングラフィお
よびエツチングにより、フォトレジスト膜14およびシ
リコン・ナイトライド膜13に選択的に開孔部を形成し
た後、ボロンイオンを注入し、P型不純物拡散層15を
形成する。つぎに第2図fblに示すように、フォトレ
ジスト膜14を除去し酸化することによりLOCO8酸
化膜16を形成した後、ソース・ドレイン領域となるN
型不純物拡散層17を選択的に形成していた。
That is, in the conventional semiconductor device, as shown in FIG. After selectively forming openings in the photoresist film 14 and silicon nitride film 13 by photolithography and etching, boron ions are implanted to form a P-type impurity diffusion layer 15.Next, As shown in FIG.
The type impurity diffusion layer 17 was selectively formed.

発明が解決しようとする課題 このような従来の半導体装置およびその製造方法では、
LOGOSによる酸化膜で素子分離領域を形成するため
、半導体装置の高集積化・高密度化に伴う素子間の分離
幅の減少に際して、充分な素子分離を得るためLOGO
Sによる酸化膜の厚みと横置がりを最適化することは困
難であり、また従来より高い濃度のP型不純物拡散層を
形成すると素子の耐圧が下がるという課題があった。
Problems to be Solved by the Invention In such a conventional semiconductor device and its manufacturing method,
Since element isolation regions are formed using LOGOS oxide films, LOGOS is used to obtain sufficient element isolation when the isolation width between elements decreases due to higher integration and density of semiconductor devices.
It is difficult to optimize the thickness and horizontal alignment of the sulfur oxide film, and there is also the problem that forming a P-type impurity diffusion layer with a higher concentration than in the past lowers the breakdown voltage of the device.

本発明は上記課題を解決するもので、LOGOSによる
酸化膜の横置がりを増やさず、かつ素子の耐圧を下げな
い素子間分離を可能とする半導体装置およびその製造方
法を提供することを目的とする。
The present invention has been made to solve the above-mentioned problems, and an object of the present invention is to provide a semiconductor device and a method for manufacturing the same that enable isolation between elements without increasing the horizontal placement of oxide films due to LOGOS and without lowering the withstand voltage of the elements. do.

課題を解決するための手段 本発明は上記目的を達成するために半導体基板上に形成
された選択酸化膜と、その選択酸化膜の中央付近のみに
その選択酸化膜と接して前記半導体基板の深さ方向にの
びて形成された酸化膜層とを設けてなる素子間分離領域
を有する構成としたものである。
Means for Solving the Problems In order to achieve the above object, the present invention provides a selective oxide film formed on a semiconductor substrate, and a selective oxide film formed only near the center of the selective oxide film in contact with the selective oxide film deep in the semiconductor substrate. This structure has an element isolation region formed by providing an oxide film layer extending in the horizontal direction.

作用 本発明は」二記した構成により、LOGOSによる酸化
膜の横置がりを増やさず、半導体基板の深さ方向にのび
た酸化膜層により、素子間分離かより充分なものになる
。また高い濃度のP型不純物拡散層を必要としないため
、素子の耐圧を下げずに素子間分離領域か形成されるこ
とになる。
Effects of the present invention With the structure described in section 2, the oxide film layer extending in the depth direction of the semiconductor substrate can provide more sufficient isolation between elements without increasing the horizontal placement of the oxide film due to LOGOS. Further, since a high concentration P-type impurity diffusion layer is not required, an isolation region between elements can be formed without lowering the withstand voltage of the element.

実施例 以下、本発明の一実施例について第1図を参照しながら
説明する。
EXAMPLE Hereinafter, an example of the present invention will be described with reference to FIG.

第1図+al〜fd)は本発明の実施例の主要工程段階
での素子分離領域の断面図を示すものである。図におい
て従来例の第2図と同一部分には同一番号を付し、説明
を省略する。すなわち本発明の特徴は、第1図+b+に
おける、酸化膜12およびLOGOSによる酸化膜16
の表面に選択的に形成されたフォトマスク1、フォトマ
スク1をマスクとして選択的に形成されたr)型不純物
拡散層2、第1図fcl、 fdlにおけるフォトマス
ク1をマスクとして選択的に形成された酸化膜層3とに
ある。
FIGS. 1+al to fd) show cross-sectional views of the element isolation region at main process steps in an embodiment of the present invention. In the figure, the same parts as those in FIG. 2 of the conventional example are given the same numbers, and the explanation will be omitted. That is, the feature of the present invention is that the oxide film 12 and the oxide film 16 formed by LOGOS in FIG.
A photomask 1 selectively formed on the surface of the r) type impurity diffusion layer 2 selectively formed using the photomask 1 as a mask, selectively formed using the photomask 1 as a mask in FIG. There is an oxide film layer 3 formed on the surface.

つぎにその構成を製造方法とともに詳しく説明する。ま
ず、第1図ta+に示すように半導体基板11の表面に
酸化膜12を形成し、その酸化膜12の上に/リコン・
ナイトライド膜13を積み素子間分離領域の部分に選択
的に開孔部を形成する。つぎに第1図(l))に示すよ
うに選択酸化膜(LOGOSによる酸化膜)16を形成
し/リコ/・ナイ!・ライト膜13を除去した後、フォ
トマスク1を形成しエツチングによりフォトマスク1の
素子IUI :I) Ni領域の中央付近にあたる部分
に選択的に開孔部を形成4る。この開孔部にボロンイオ
/を注入することによりP型不純物拡散層2を形成する
。つぎに第1図(C)に示すように、フォトマスク1の
開孔部に酸素イオンを注入しアニールすることにより選
択酸化膜16に接し、半導体基板1]の深さ方向にのび
た酸化膜層3を形成する。つぎに第1図fdlにiI〈
すようにフォトマスク]を除去した後、従来例と同様に
ソース・ドレイン領域となるN型不純物拡散層17を選
択的に形成する。これにより、半導体表面の選択酸化膜
による素子間分離領域の中央付近のフォトマスク1の開
孔部の幅を適切に選び酸化膜層3の横方向の広がりを抑
え、選択酸化膜]6の中央付近のみに、その選択酸化膜
と接して、半導体基板11の深さ方向にのびた酸化膜層
3が形成されるため、P型不純物拡散層2の濃度を濃く
する必要がなくなり、分離幅が狭く素子の耐圧を下げな
い素子間分離領域を形成することができた。
Next, the structure will be explained in detail together with the manufacturing method. First, as shown in FIG.
A nitride film 13 is stacked and openings are selectively formed in the inter-element isolation regions. Next, as shown in FIG. 1(l)), a selective oxide film (LOGOS oxide film) 16 is formed. - After removing the light film 13, a photomask 1 is formed and an opening is selectively formed 4 in a portion near the center of the element IUI:I) Ni region of the photomask 1 by etching. A P-type impurity diffusion layer 2 is formed by implanting boron ions into this opening. Next, as shown in FIG. 1C, oxygen ions are implanted into the openings of the photomask 1 and annealed to form an oxide film layer that comes into contact with the selective oxide film 16 and extends in the depth direction of the semiconductor substrate 1. form 3. Next, in Figure 1 fdl, iI
After removing the photomask], as in the conventional example, N type impurity diffusion layers 17 which will become source/drain regions are selectively formed. As a result, the width of the opening of the photomask 1 near the center of the element isolation region formed by the selective oxide film on the semiconductor surface is appropriately selected to suppress the lateral spread of the oxide film layer 3, and the center of the selective oxide film 6 is Since an oxide film layer 3 extending in the depth direction of the semiconductor substrate 11 is formed only in the vicinity, in contact with the selective oxide film, there is no need to increase the concentration of the P-type impurity diffusion layer 2, and the isolation width is narrow. It was possible to form an isolation region between elements without lowering the withstand voltage of the element.

発明の効果 以上の実施例から明らかなように本発明によれば、通常
の素子間分離用の選択酸化膜の下に深さ方向にのびた酸
化膜層を設けているので、素子間分離幅の節減となり、
分離幅が狭くて耐圧の下がらない半導体装置およびその
製造方法を提供できる。
Effects of the Invention As is clear from the above embodiments, according to the present invention, an oxide film layer extending in the depth direction is provided under a selective oxide film for normal isolation between elements, so that the width of isolation between elements can be reduced. It saves money,
It is possible to provide a semiconductor device whose isolation width is narrow and whose breakdown voltage does not drop, and a method for manufacturing the same.

【図面の簡単な説明】[Brief explanation of drawings]

第1図ta+〜(dlは本発明の一実施例の半導体装置
の製造方法の主要工程段階の工程断面図、第2図fat
、 (blは従来の半導体装置の製造方法の主要工程段
階の工程断面図である。 3・・・・・・酸化膜層、11・・・・・・半導体基板
、16・・・・L OG OSによる酸化膜(選択酸化
膜)。 代理人の氏名 弁理士 粟野重孝 はか1名第2 j1!
Fig. 1 ta+~(dl is a process cross-sectional view of the main process steps of the method for manufacturing a semiconductor device according to an embodiment of the present invention, Fig. 2 fat
, (bl is a process cross-sectional view of the main process steps of a conventional semiconductor device manufacturing method. 3... Oxide film layer, 11... Semiconductor substrate, 16... L OG Oxide film (selective oxide film) by OS. Name of agent: Patent attorney Shigetaka Awano Haka1 person 2nd j1!

Claims (3)

【特許請求の範囲】[Claims] (1)半導体基板上に形成された選択酸化膜と、その選
択酸化膜の中央付近のみにその選択酸化膜と接して前記
半導体基板の深さ方向にのびて形成された酸化膜層とを
設けてなる素子間分離領域を有する半導体装置。
(1) A selective oxide film formed on a semiconductor substrate, and an oxide film layer formed only near the center of the selective oxide film and extending in the depth direction of the semiconductor substrate in contact with the selective oxide film. A semiconductor device having an isolation region between elements.
(2)半導体基板の深さ方向にのびて形成された酸化膜
層の下部に不純物拡散層を設けた請求項1記載の半導体
装置。
(2) The semiconductor device according to claim 1, wherein an impurity diffusion layer is provided below the oxide film layer formed extending in the depth direction of the semiconductor substrate.
(3)半導体基板上に素子間分離領域として選択酸化膜
を形成する工程と、その選択酸化膜の中央付近に選択的
に酸素イオンを注入して前記選択酸化膜と接し前記半導
体基板の深さ方向にのびた酸化膜層を形成する工程とを
有する半導体装置の製造方法。
(3) Forming a selective oxide film as an element isolation region on a semiconductor substrate, and selectively implanting oxygen ions near the center of the selective oxide film so that the selective oxide film contacts the depth of the semiconductor substrate. A method for manufacturing a semiconductor device, comprising: forming an oxide film layer extending in a direction.
JP15204390A 1990-06-11 1990-06-11 Semiconductor device and its manufacture Pending JPH0443662A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15204390A JPH0443662A (en) 1990-06-11 1990-06-11 Semiconductor device and its manufacture

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15204390A JPH0443662A (en) 1990-06-11 1990-06-11 Semiconductor device and its manufacture

Publications (1)

Publication Number Publication Date
JPH0443662A true JPH0443662A (en) 1992-02-13

Family

ID=15531812

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15204390A Pending JPH0443662A (en) 1990-06-11 1990-06-11 Semiconductor device and its manufacture

Country Status (1)

Country Link
JP (1) JPH0443662A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333243B1 (en) 1996-06-12 2001-12-25 Micron Technology, Inc. Method for growing field oxide to minimize birds' beak length

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6333243B1 (en) 1996-06-12 2001-12-25 Micron Technology, Inc. Method for growing field oxide to minimize birds' beak length

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