JPH0443394A - Multi-window double buffer system - Google Patents

Abstract

PURPOSE:To eliminate need to control the front/back state of a display bank in window units by providing a function for a copying process between a front and a back plane during the blanking period of a vertical synchronizing signal. CONSTITUTION:Functions are so fixed completely that data are plotted on the back plane 3 and display data are transferred from the front plane 2 to a CRT 9. When two graphic windows Af and Af are present and data are plotted in the window Af, front planes 0 - 3 are copied to the back plane and a window Ab is generated on the back plane 3. A processor 0 plots data in the window Ab through a data bus 1 for plotting. After the plotting, the blanking period TVBL of the vertical synchronizing signal is used to perform a copying process from the window Ab to the window Af again. Consequently, screens are replotted without any disorder.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a graphic display device using a graphic CRT display device, and more particularly to a double buffer method in multi-window display.

[Summary of the invention]

The present invention utilizes a high-speed transfer mode of a video memory to display a front plane during blanking of a vertical synchronization signal in a graphics display device that displays a frame buffer in a double-buffer format with two banks of front plane and hack plane per plane. By copying the data from the backplane to the backplane, modifying the data on the backplane, and then copying it to the frontplane again, the display is always fixed to the frontplane side, eliminating the need to manage whether the display bank of each window is front or back. It realizes multi-window double buffering without any screen disturbance during drawing.

[Conventional technology]

In a graphic CRT display device, a so-called double buffer system is adopted in order to eliminate disturbances on the display screen during data changes when enlarging, reducing, or moving figures.

FIG. 2 explains the double buffer system conventionally used in boat fishing. The frame buffer is composed of two planes, a front plane 12 and a back plane 13, and one plane is displayed by a bank switching signal 16, while the other plane is changed. When the change is completed, change the bank and display the changed plane.

By repeating this process, the movement of the figure can be made to appear smooth.

In reality, multi-color display and multi-windows are achieved by preparing multiple planes of double-buffered frame buffers, but when performing multi-window processing using this method, the following processing is required. .

In Figure 2, there are window A and window B on the screen, and each window has planes 0 to 3 as shown in Figure 3.
Assume that planes 4 and 5 are assigned to window A and planes 4 to 5 are assigned to window B. Banks can be switched independently for each plane, and when window A is moved, only planes 0 to 3 are displayed in a double buffer.

Therefore, it is necessary to confirm whether each window on the screen that is finally being displayed is a front plane or a back plane before writing new data.

[Problem to be solved by the invention]

In the case of the conventional method, it is necessary to manage for each window whether the screen that is finally displayed is the front plane or the back plane. Therefore, as the number of windows increases, the amount of information that must be checked when rewriting the screen increases, and the load on the software increases.

[Means to solve the problem]

In order to solve the above-mentioned problems, the present invention provides a function for copying between the front plane and the backplane during blanking of the vertical synchronization signal, and for example, the front plane is used only for display and the back plane is used only for drawing. Here, when redrawing the window Af in FIG. 1, the window Af is first copied onto the backplane and is designated as a window Ab. Next, drawing is done in window Ab on the back plane, and when it is finished, it is copied again to window Af on the front plane. Since the interplane copy here is performed during blanking of one vertical synchronization signal, no disturbance occurs on the screen when copying to the front plane being displayed.

〔Example〕

Embodiments of the present invention will be described below with reference to the drawings.

In FIG. 1, l is a bus for drawing data to a frame buffer, and is connected to the backplane 3 in this embodiment. Further, 8 is a bus for reading display data from the frame buffer, and is connected to the front plane 2 in this embodiment. Here, the front plane 2 and the back plane 3 are physically the same 25
It is a 6Kx4 video DRAM, and when the most significant bit of the address is O, it is the front plane, and when it is 1, it is the back plane.

Here, a method for performing inter-blink copying during blanking of the vertical synchronization signal will be described.

Figure 4 shows commonly used IM bit video RA
It is a figure showing the structure of M. The RAM portion has a 512×512 memory cell, and the SAM portion has a 512×1 register structure. 51 between the RAM section and the SAM section
Pig transfer is possible in units of 2 bits. Figure 5 shows this RA
This figure shows an example of the transfer timing between the M part and the SAM part, and represents the timing when copying from the front plane to the back plane. In cycle 1, the most significant bit A8 of the address applied to the video RAM is 0, and the IRoW of the front plane 2 is
512 bits of data are transferred to the SAM 17. In cycle 2, the most significant bit A8 of the address is 1, and 512 bits of data in the SAM 17 are transferred to the IRC)W of the backplane 3.

Therefore, by repeating the cycle shown in FIG. 5 256 times, the entire surface can be copied from the front plane 2 to the back plane 3. In the example shown in Fig. 5, we assume a basic clock tφ-32nSec and a video memory access time of 100nS.
The data copy time for IRoW is 512 nS. In other words, from the front plane 2 to the back plane 3
The time required to copy the entire area to is 131 μs.

In CRT, which is currently most commonly used in graphic CR7 display devices, the vertical synchronization signal blanking time T
Since VBL is approximately 800 μs, it is possible to perform full copy between planes during this time.

In this embodiment, as shown in FIG. 1, the functions are completely fixed: data drawing is transferred to the backplane 3, and display data transferred to the CRT 9 is transferred from the front plane 2. It is assumed that there are two graphic windows Af and Bf on the front plane 2, and the relationship between each window and the plane is as shown in FIG. When drawing on window Af, copies are made from the front plane of planes O to 3 to the back plane, and window Ab is generated on the back plane 3.

Here, the processor 0 draws on the window Ab via the drawing data bus 1.

After the drawing is completed, the blanking period TVBL of the vertical synchronization signal is used to re-copy from the window Ab to the window Af. Therefore, although the window Af remains displayed, the screen is redrawn without any disturbance.

In this embodiment, only the plane corresponding to the window to be drawn is copied to achieve a double buffer, but it goes without saying that the same result can be obtained by copying all the planes at the same time.

〔Effect of the invention〕

As explained above, in the present invention, by providing a function to execute copying between the front plane and the back plane during the blanking period of the vertical synchronization signal, the display plane and the drawing plane can be fixed, and multi-window double It has a great effect in that it realizes a buffer and eliminates the need to manage whether the display bank is front or back for each window as in the past.

[Brief explanation of drawings]

Fig. 1 is a block diagram for explaining the present invention in detail, Fig. 2 is a block diagram for explaining the conventional double buffer display, and Fig. 3 shows the correspondence between each window and plane in this embodiment. Figure 4 shows a general video RAM
FIG. 5 is a diagram showing an example of the timing of the inter-plane copy executed during the blanking period of the vertical synchronization signal in the present invention. 1st M 2...Front plane 3...Back plane 9... CRT Fig. 2 Fig.

Claims (1)

[Claims] CR in the multi-window double-buffer system of a graphics display device that has two banks of frame buffers per plane and displays the screen in a double-buffer system.
It has a function to complete inter-bank copying of each plane during the blanking period of the vertical synchronization signal T, and when performing double buffer display, it copies from the display bank to the drawing bank, and after the drawing is completed, the above Multi-window double buffer that makes it possible to fix the display bank and drawing bank by copying back to the display bank using bank-to-bank copying, and eliminates the need to manage display banks for each window during multi-window processing. method.