JPH0442470A - Clock extraction circuit - Google Patents

Abstract

PURPOSE:To surely detect a locked state by detecting whether or not a phase- locked loop is locked corresponding to data for lock detection generated based on a reference clock or reference data and input data or the reference clock. CONSTITUTION:The clock extraction circuit is equipped with a voltage controlled oscillation means 13 which generates a prescribed reference clock CK11 corresponding to a control voltage VERI, and a phase comparison means 21 which compares the phase of the reference clock CK11 with that of the input data DTIN and generates and feeds back the control voltage VERI in accordance with the phase difference of them to the voltage controlled oscillation means 13, and controls the frequency of the reference clock CK11. Thence, it is detected whether or not the phase locked loop is locked corresponding to the data CK12 for lock detection generated based on the reference clock CK11 by lock detecting means 31, 32, and 18, and the input data DTIN. Thereby, the locked state can be surely detected.

Description

[Detailed description of the invention] The present invention will be explained in the following order.

A. Industrial field of application B. Overview of the invention C. Prior art (Figs. 5 to 7) D. Problems to be solved by the invention (Figs. 8 and 9) 8. Means for solving the problems (Fig. 9) 1, 3) F action (Fig. 1, 3) G embodiment (G1) Clock extraction circuit of the first embodiment (Fig. 1, 2)
Figure) (G2) Clock extraction circuit of the second embodiment (Figures 3 and 4)
(G3) Other Embodiments H Effects of the Invention A Field of Industrial Application The present invention relates to a clock extraction circuit, and is suitable for application to, for example, a circuit used in a reproduction system of a data recorder.

B. Summary of the Invention The present invention provides a clock extraction circuit that extracts a clock from human input data using a self-chronograph method, and lock detection data generated based on a reference clock or input data, and phase lock according to the input data or reference clock. By detecting whether or not the droop is locked, the locked state can be reliably detected.

C. Prior Art Conventionally, data recorders that record and reproduce desired information data on a magnetic tape have adopted a data transmission system based on a so-called self-clock method, in which the information data is modulated including a clock and transferred to the magnetic tape. Extracts the clock from the digital signal recorded on the top and played back during playback,
The reproduced digital signal is demodulated according to the clock to obtain information data.

That is, as shown in FIG. 5, the data reproducing device W1 of the data recorder reads information data recorded on the magnetic tape 2 using the head 3, and then amplifies and equalizes it through the head amplifier circuit 4 and the equalizer circuit 5. The signal is input as a reproduced RF signal SIF to a binarization circuit 6 having a comparator circuit configuration.

A predetermined reference voltage V ltF is supplied to the binarization circuit 6, which binarizes the reproduced RF signal SmF according to the level of the reference voltage V IEF, and the resulting input data D
T I N is input to the input end of the D flip-flop 7 and is also input to a clock extraction circuit 8 having a phase-locked loop (PLL) configuration.

The clock extraction circuit 8 extracts the clock CK o synchronized with the input data DTIN, and sends it to the D flip-flop 7.
The signal is supplied to the clock end of the circuit, and is also sent to a subsequent digital signal processing circuit (not shown).

The D flip-flop 7 synchronizes the input data D T t N at a timing according to the clock CK, and sends the resulting input data D T I N l to the digital signal processing circuit.

In this manner, the digital signal processing circuit executes the demodulation process of the input data DTIN+ based on the timing of the clock CK0, and is thus able to reproduce the information data recorded on the magnetic tape 2.

Generally, in order to detect whether or not the clock extraction circuit 8 is operating normally, it is sufficient to detect whether or not the PLL is locked (conventionally, as shown in FIG.
In the PLL circuit 10 which generates the second reference clock CK1□ (FIG. 7 (B)) whose phase is synchronized with the second input clock CK+Nx (FIG. 7 (A)) based on the input clock CKINI of is the second input clock C
An exclusive OR operation is performed on the inverted signals of K+Ht and the second reference clock CK□, and when the integral value of the operation result is at the logic rH level, it is detected that the PLL circuit IO is talking It is made to be.

Actually, in this PLL circuit 10, the first input clock CK, □ is divided by 1/N through the 1/N frequency divider circuit 11 and the second input clock CKIN! The signal is then input to the phase comparator circuit 12.

In addition to this, the phase comparator circuit 12 receives a first reference clock signal CKmir+ sent from a voltage controlled oscillator (VCO) 13 through a 1/M frequency dividing circuit 14.
The frequency is divided and inputted as the second reference clock CK1o.

The phase comparator circuit 12 has a second input clock CK1! and a second reference clock CK1! F! An error voltage V, . Thus, the frequency of the first reference clock signal CK, . . A second reference clock CK□ whose phase is synchronized with that of the second reference clock CK□.

Send out.

Here, in the case of this PLL circuit 10, the second reference clock CK□□ is inverted through the inverter circuit 16, and the second reference clock CK
is input to the exclusive OR circuit 17 together with the input clock CK+Nz, and an exclusive OR operation is executed, and the result of this operation is passed through the integration circuit 18 to the lock detection signal S,
. (FIG. 7(C)).

The PLL circuit 10 locks this lock detection signal SL0, and the second reference clock CKIIEF! and when the phases of the second input clocks CK+ and 4z match, 16
Based on the logic level of the lock detection signal sL, it is possible to detect whether or not the PLL circuit 10 is locked.

D invention tries to solve! ! By the way, in the clock extraction circuit 8 mentioned above, the eighth
As shown in the figure, human data DTIN (FIG. 9(A)) is input to the data window generation circuit 20, and as a result, a data window that rises for a predetermined period in response to the rising and falling edges of the input data DT and H. D'
r'wD (FIG. 9(B)) is generated and input to the phase comparison circuit 21.

Further, a reference clock CK (FIG. 9(C)), which is approximately equal to the self-clock included in the input data DT, generated by the VCO 13, is input to the phase comparator circuit 21.

As a result, the phase comparator circuit 21 uses the data window DTw.
Generate error voltages ■ and □ such that the reference clock CK rises at the center timing of the rising period of n,
This is averaged through the LPF 15 and used as an average error voltage v tax to control the oscillation frequency of the VCOI 3.

In this way, this clock extraction circuit 8 receives the input data D.
The reference clock CK whose phase is synchronized with the self-clocker included in the T-piece is extracted and can be sent out.

However, since the input data DTIN of the clock extraction circuit 8 and the reference clock CKo have different actual frequencies, as described above for the PLL circuit 10, the input data DTIN and the reference clock CK are simply used as input data DTIN and the reference clock CK.

Even if the exclusive OR operation is performed, the clock extraction circuit 8
There was a problem in which it was not possible to detect whether or not the device was locked.

Therefore, the error voltage sent out from the phase comparator circuit 21
. It is conceivable to detect whether or not the clock extraction circuit 8 is locked by monitoring VE1, but even with this method, the reliability of the error voltage VEll itself may be low depending on the configuration and state of the PLL, making it difficult to extract the clock correctly. It was not possible to detect whether the circuit 8 was locked, and as a result, the solution was still insufficient.

The present invention has been made in consideration of the above points, and it is an object of the present invention to propose a clock extraction circuit that can reliably detect whether or not a lock state is established when extracting a clock from manual data using a self-clock method.

Means for Solving the EyA Problem In order to solve this problem, in the first invention, in the clock extraction circuit 30 that has a phase-locked loop configuration and extracts the clock included in the input data DT, H that is transmitted by a self-clotter method. , control voltage VEm+
(Vtmt), a predetermined reference clock CK,
, (CK,.);
Reference clock CKt+ and input data DTIN (DT
We compare the phases of we) and set the control voltage V according to the phase difference.
va+ (VIz), which is fed back to the voltage-controlled oscillation means 13 to control the frequency of the reference clock CK, , and the first lock detection data CKI based on the reference clock CK++. ! and a first lock detection signal 5LO corresponding to the first lock detection data CK and input data DT1.4.
First lock detection means 31, 32, and 18 for generating I are provided.

Further, in the second invention, the input data D has a phase-locked loop configuration and is transmitted by a self-cropping method.
In the clock extraction circuit 40 that extracts the clock included in T I N, the control voltage V Fall (Vtaz
) and a voltage-controlled oscillation means 13 that generates a predetermined reference clock CKxo according to the reference clock CK! . The phases of input data DTIN and input data DTIN are compared, and a control voltage Vrm+ (Vtaz) corresponding to the phase difference is generated and fed back to the voltage controlled oscillation means 13, and a reference clock CK. phase comparison means 12 for controlling the frequency of input data DTI;
The second lock detection data DTLo is generated based on the second lock detection data DTLo and the reference clock CKt. The second lock detection signal S LOI! A second lock detection means 41.
42.18.

Lock detection means 31.32.1 When extracting a clock from input data D T I N of the F action self-clock method
Reference clock CK by 8 (41, 42, 18),
, or the lock detection data (CKrt, DTto) generated based on the input data DTIN, and the input data DTl,l or the reference clock CK. By detecting whether or not the phase-locked loop is locked depending on the timing, the locked state can be reliably detected.

G example An embodiment of the present invention will be described in detail below with reference to the drawings.

(G1) Clock extraction circuit of the first embodiment In FIG. 1, parts corresponding to those in FIG. 8 are denoted by the same reference numerals. In FIG.
(FIG. 2(A)) is input to the input ends of the data window generation circuit 20 and the D flip-flop 7.

The data window generation circuit 20 has, for example, a delay circuit and an exclusive OR circuit configuration, and performs an exclusive OR operation between the input data DT and delayed data delayed by a predetermined amount in the delay circuit, so that the input data DT, . The data window DT@e (see Fig. 2) rises at the timing of the rising and falling edges of
B)) is generated and sent to the phase comparison circuit 21.

The phase comparison circuit 21 also receives the first reference clock CKIO (FIG. 2(E)) sent from the VCO 13 at 1/
The frequency is divided by 1/2 through the frequency divider circuit 33 and inputted as the second reference clock CK (FIG. 2(C)).

As a result, the phase comparator circuit 21 uses the second reference clock C
K, , and the rising edge of data window DT1.
The phase is compared with the center part of the rising pulse of ID, and an error voltage (2o1) is generated according to the phase difference.

This error voltage Veil is the average error voltage ■ through the LPF15. , so that the VCO 13 outputs the first reference clock CK, depending on the average error voltage V Eat. control the oscillation frequency.

Thus, as the output of the clock extraction circuit 30, the second reference clock CK whose phase is synchronized with the data window DThn based on the input data DT, H is sent out, and is input to the digital signal processing circuit and the D flip-flop 7. input to the clock end of the

The D flip-flop 7 synchronizes the input data DT, . . . with a timing corresponding to the second reference clock CK, and sends the resulting input data DT I N + to the digital signal processing circuit.

Thus, the digital signal processing circuit uses the clock CK,...
Based on the timing of , demodulation processing of the input data DTINI is executed, and thus the information data recorded on the magnetic tape 2 can be reproduced.

Here, in the case of this embodiment, the first reference clock CK,
and the second reference clock CK■ are respectively input to the clock end and the input end of the D flip-flop 31 for generating lock detection data, and as a result, the D flip-flop 31
A clock whose phase is delayed by 45 degrees with respect to the second reference clock CK r + is generated from the inverted output end page of the clock, and this is used as the lock detection data CK 1t to be used as the lock detection data D.
It is sent to the input end of the flip-flop 32.

The clock end of the D flip-flop 32 for lock detection has input data DT1. As a result, the lock detection D flip-flop 32 receives input data DT, .
At the timing when CK rises, lock detection data CK,
is latched, and the latch result is integrated through the integrating circuit 18 and sent as a lock detection signal 5LOI.

When the phase of the actually output second reference clock CK,l matches the input data DT, , and the PLL of the clock extraction circuit 30 is in a locked state, the rising edge of the input data DTIN coincides with the second reference clock CK, . , for 4
It exists during the rising period of the lock detection data CK, whose phase is delayed by 5 degrees.

As a result, the logic "H" level is latched in the lock detection D flip-flop 32, and the logic rH
A lock detection signal 5LOI having a level of , is sent out.

On the other hand, when the 'PLL of the clock extraction circuit 30 is not in the locked state, the rising edge of the input data D T I N deviates from the rising period of the lock detection data CK, and as a result, the logic "L" level or A lock detection signal S, which has an intermediate level. 1 is sent.

Therefore, in the case of this clock extraction circuit 30, the lock detection signal S,. By detecting whether or not 1 is at the logic rH level, it is possible to easily detect whether or not the PLL of the clock extraction circuit 30 is in a locked state.

According to the above configuration, when extracting a clock from the self-clocking input data DT, the reference clock CK
It generates lock detection data CK, whose phase is delayed by 45 degrees with respect to , and determines whether or not the rising edge of input data D T r N exists in the rising period of lock detection data CK, . By detecting whether or not the PLL is locked accordingly, it is possible to realize the clock extraction circuit 30 that can easily and reliably detect the locked state.

(G2) Clock extraction circuit of the second embodiment In FIG. 3, parts corresponding to those in FIG. (A)) is the reference clock CKt generated by the VCO 13.

(FIG. 4(B)) and is input to the phase comparison circuit 12.

In the case of this phase comparison circuit 12, the rising and falling edges of input data DT0 and the reference clock CK.

Compare the phases of and calculate the error voltage according to the phase difference■□1
This is inputted to the VCO 13 as the average error voltage v tax through the LPF 15, and thereby V
CO13 is the reference clock CK, depending on the average error voltage ■□□. control the oscillation frequency.

Thus, the clock extraction circuit 4o receives the input data DTIN
It is possible to send out a reference clock CK□ whose phase is synchronized with the reference clock CK□.

In this embodiment, the input data DT□ is input to the lock detection data generation circuit 41 in addition to the phase comparison circuit 12, and the reference clock CKm* is also input to the phase comparison circuit 12.
In addition, a buffer amplifier circuit 42 having an enable end
The signal is input to the integrating circuit 18 through.

The lock detection data generation circuit 41 has, for example, a delay circuit and an exclusive OR circuit configuration, and input data DT
, , and a delay circuit, for example, a reference clock CK. 1/2 of
An exclusive OR operation is performed with the delayed data D'r+me (FIG. 4(C)) delayed by a period, and the reference clock CK, . Lock detection data DTto (FIG. 4(D)) which rises with a pulse width of 1/2 cycle is generated and sent to the enable terminal of the buffer amplifier circuit 42.

The buffer amplifier circuit 42 receives a reference clock CK during a period in which the lock detection data DTLO input to the enable terminal has a logic "H" level. Amplify ′
The lock detection signal SLO! is sent to the integration circuit 18 and integrated through the integration circuit 18. (Fig. 4(E)).

Actually reference clock CK! . When the phase of the reference clock CK matches that of the input data DT and the PLL of the clock extraction circuit 40 is in a locked state, the reference clock CK. The rising period of the lock detecting data DTL is defeated by the rising period of the lock detecting data DTL, thereby causing the lock detecting signal S1 having a logic "H" level.
゜, is sent.

On the other hand, when the PLL of the clock extraction circuit 40 is not in a locked state, the reference clock CK. The rising period of the lock detection data DTLO is shifted from the rising period of the lock detection data DTLO, and as a result, the lock detection signal stag having a logic "L" level or an intermediate level is sent out.

Therefore, in the case of the clock extraction circuit 40, by detecting whether the lock detection signal 5Lot is at the logic "H" level, it is possible to easily detect whether the clock extraction circuit 400PLL is in the locked state.

According to the above configuration, when extracting the clock CK, from the self-clocking input data DT, , the reference clock CK rises at the timing of the rising and falling edges of the input data DTIN. 1
Lock detection data DT having a pulse width of /2 cycles
By generating L0 and detecting whether or not the PLL is locked depending on whether the rising period of the lock detection data DTLO coincides with the rising period of the clock CK, it is easy and reliable. A clock extraction circuit 40 that can detect a lock state can be realized.

(G3) Other embodiments (1) In the first embodiment described above, the input data D
Although the phases of the data window generated based on T I N and the reference clock are compared, the same effect as in the above embodiment can be obtained even if the phases of the input data DT, . . . and the reference clock are directly compared. can be realized.

C) In the first embodiment described above, the first reference clock generated by the VCO is divided by half, and the phase is compared with the second reference clock and data window obtained as a result. Alternatively, the phase may be compared with a third reference clock and a data window generated by the VCO.

In this case, instead of the lock detection data generated using the first reference clock and the second reference clock, the third
and a fourth reference clock obtained by doubling the reference clock of the cylinder 3, to generate lock detection data that is delayed in phase by 45 degrees with respect to the third reference clock. Alternatively, instead of using the fourth reference clock, a delay circuit or the like may be used to delay the phase of the third reference clock by a predetermined amount to generate lock detection data.

(3) In the first embodiment described above, the first reference clock generated by the VCO using a D flip-flop and the second reference clock obtained by dividing the first reference clock by 1/2 are used. Although the lock detection data delayed by 451 phases with respect to the second reference clock is generated, instead of this, the lock detection data may be generated using a logic circuit such as an exclusive OR operation. In short, if the lock detection data is generated in accordance with the output reference clock, the same effect as in the above-described embodiment can be achieved.

(4) In the first embodiment described above, the lock detection circuit is configured with D flip-flops, but the circuit configuration is not limited to this, and the point is that the lock detection data is input at the timing when the input data rises. By latching the level, the same effect as in the above embodiment can be achieved.

(5) In the second embodiment described above, the clock rises at the edge timing of the input data and is 1/2 of the reference clock.
Although we have described the case where lock detection data having a pulse width equal to a period is generated, the pulse width of the lock detection data may be limited to this and may be within 1/2 period. Detection accuracy can be improved.

(6) In the second embodiment described above, the case was described in which a buffer amplifier circuit with an enable terminal was used to send the clock to the integrating circuit during the rising period of the lock detection data, but the circuit configuration is as follows. However, the point is that the same effects as in the above-described embodiments can be achieved even if a logic gate circuit or the like is used as long as the clock can be sent during the rising period of the lock detection data based on the input data.

(7) In the above-mentioned embodiment, the case where the present invention is applied to the playback system of a data recorder has been described, but the present invention is not limited to this. It is widely applicable and suitable for extracting.

H Effects of the Invention As described above, according to the present invention, when extracting a clock from input data in a self-clocking system, the lock detection data generated based on the reference clock or input data and the input data or reference clock are By detecting whether or not the phase-locked loop is locked according to the above, it is possible to realize a clock extraction circuit that can easily and reliably detect whether or not the phase-locked loop is locked.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing one embodiment of a clock extraction circuit according to the present invention, FIG. 2 is a timing chart for explaining its operation, and FIG. 3 is a block diagram showing a clock extraction circuit according to another embodiment. 4 is a timing chart for explaining its operation, FIG. 5 is a block diagram showing a data reproducing device, FIG. 6 is a block diagram showing a conventional PLL circuit, and FIG. 7 is a timing chart for explaining its operation. FIG. 8 is a block diagram showing a conventional clock extraction circuit, and FIG. 9 is a timing chart for explaining its operation. 8.30.40...Tlock extraction circuit, 12.2
1...Phase comparator circuit, 13...■C0
115...LPF, 1B...Integrator circuit, 20...Data window generation circuit, 31...
... D flip-flop for lock detection data generation, 32 ... D flip-flop for lock detection, 41 ... Data generation circuit for lock detection, 42
...Buffer amplifier circuit. Figure 1

Claims (2)

[Claims] (1) In a clock extraction circuit that has a phase-locked loop configuration and extracts a clock included in input data transmitted using a self-clock method, voltage-controlled oscillation means that generates a predetermined reference clock according to a control voltage; Compare the phases of the reference clock and the above input data,
phase comparison means for generating a control voltage according to the phase difference and feeding it back to the voltage-controlled oscillation means to control the frequency of the reference clock; and generating first lock detection data based on the reference clock. and a first lock detection means that generates a first lock detection signal according to the first lock detection data and the input data, and detects the phase lock based on the first lock detection signal. A clock extraction circuit characterized by detecting whether or not a droop is locked. (2) A voltage-controlled oscillation means that generates a predetermined reference clock according to a control voltage in a clock extraction circuit that has a phase-locked loop configuration and extracts a clock included in input data transmitted in a self-clocking manner; Compare the phases of the reference clock and the above input data,
phase comparison means for generating a control voltage according to the phase difference and feeding it back to the voltage-controlled oscillation means to control the frequency of the reference clock; and generating second lock detection data based on the input data. and a second lock detection means for generating a second lock detection signal according to the second lock detection data and the reference clock, and detects the phase lock based on the second lock detection signal. A clock extraction circuit characterized by detecting whether or not a droop is locked.