JPS6053387B2 - data demodulator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a data demodulation device for data recorded on a magnetic medium using, for example, a two-frequency modulation method, and in particular, the present invention relates to a data demodulation device that performs phase adjustment based on a reading signal of a frequency divider output signal. This invention relates to a demodulator.

When reproducing information recorded on a magnetic medium using a multi-track phase modulation method, such as in a magnetic tape device,
As shown in FIG. 1, a data demodulation device comprising a phase synchronized oscillator 1, a frequency divider 2, and a data discrimination circuit 3 is used. The phase synchronized oscillator 1 generates an output signal with a frequency N times higher than the read signal transmitted from the input terminal TN. The first frequency divider 2 divides the frequency of the output signal transmitted from the phase synchronized oscillator 1 into 1/N to obtain a reference signal. The data discrimination circuit 3 determines the logic "1" of the read signal transmitted from the input terminal TN.
, "O" is determined based on the reference signal, and the read signal is interpreted as a data signal to a data processing device such as a central processing unit, and the data signal is sent from the data output terminal D.
Until now, as shown in FIG. 1, the circuit configuration is expensive and large and complicated.

Since a data demodulator having a phase synchronized oscillator 1 was provided for each multi-track of the magnetic tape, the circuit configuration of the conventional magnetic recording apparatus had to be complicated and expensive. However, in general, in a magnetic tape device, the frequency of data between each track is the same, but the phase of the data is different. A system has been proposed in which a common phase synchronized oscillator 1-1 is provided for every three tracks, and frequency dividers 2-1 to 2-3 and 3-logic 3-3 are provided for each track. .

According to this method, one phase-locked oscillator is used every few tracks.
Since it is only necessary to provide a single one, the above-mentioned problems can be solved.

However, in reality, the information recorded on each track of a magnetic tape is A difference occurs in the frequency components of

That is, for example, as shown in FIG.
and TN-3, there are three adjacent tracks No. of the magnetic tape. l, NO. 2 and NO. It is assumed that the read signals read from 3 are being transmitted respectively. Among the read signals transmitted to these input terminals, input terminal TN
-1 and TN-2 read signals A-1 and A
-2, as shown in Figure 3, the first pulse has a phase difference of Δt1, but as mentioned above, there is a difference in frequency components, so for example, in the fifth pulse, the phase difference becomes ΔT2. , the initial phase difference Δ becomes considerably different compared to later. However, as shown in FIG. 2, the phase-locked oscillator 1-1 generates an output signal of N times the frequency synchronized with the read signal A-1, and this output signal is commonly used to transmit the signal to the frequency divider 2, respectively. -1 to 2-3 to 1/N
The reference signal is obtained by dividing the frequency into In other words, since the data discrimination circuits 3-1 to 3-3 perform discrimination based on this reference signal, the inventors have found that the following problem will occur if the phase of the frequency divider is first adjusted. It's been found. Reference signal B- obtained from frequency dividers 2-1 and 2-2
1 and B-2 are obtained from the output signal obtained from the phase synchronized oscillator 1-1, so the phase difference between them is the same for both the first pulse and the subsequent pulses, as shown in Figure 3. It is.

Moreover, the output signal of the phase synchronized oscillator 1-1 can be read. Since it is obtained in synchronization with signal A-1, reference signal B-1
maintains synchronization with the read signal A-1. As a result, the data obtained from the data discrimination circuit 3-1 is accurate. However, as mentioned above, the data is transmitted to terminal TN-2. Since the read signal A-2 that is reached includes a frequency component different from that of the read signal A-1, the data discrimination circuit 3 uses the reference signal B-2 obtained in synchronization with the read signal A-1. When the data is discriminated at -2, the read signal A-2 and the reference signal B-2 are no longer synchronized, and as a result, the data obtained from the data discriminator circuit 3-2 contains an error.

Of course, this will also cause an error for the same reason when determining the read signal A-3 transmitted to the input terminal TN-3. Therefore, it is an object of the present invention to provide a data demodulation device that uses a phase synchronized oscillator as a common signal, which improves the above problems discovered by the present inventor, and for this purpose, The data demodulation device of the present invention includes a data discriminator circuit to which different read signals are transmitted, a plurality of frequency dividers that divide the frequency of an output signal generated from a common phase synchronized oscillator, and In a demodulator configured to discriminate information of the different read signals by transmitting the obtained reference signal to each data discriminator circuit, data discrimination is performed in which a read signal other than the read signal transmitted to the phase synchronized oscillator is discriminated. A phase correction circuit is provided in the frequency divider that transmits the reference signal to the circuit, and by transmitting the read signal to the phase correction circuit, the phase of the reference signal obtained from the frequency divider is corrected, and each read signal is discriminated. It is characterized by being configured to do so.

An embodiment of the present invention will be explained based on FIGS. 4 to 6.

FIG. 4 is a circuit configuration diagram showing a device according to an embodiment of the present invention, FIG. 5 is a circuit configuration diagram showing its essential parts in more detail, and FIG. 6 is an explanatory diagram of its operation.

In the figure, parts with the same symbols as in other figures indicate the same parts, 4 is a frequency divider with a phase correction circuit, 5 is a frequency divider, 6 is a differentiation circuit, 7 is a wind pulse generation circuit, and 8 is a frequency divider with a phase correction circuit. This is a phase extraction circuit.

Details of the frequency divider 4 with phase correction circuit are shown in FIG.

The differentiating circuit 6 has a logic RlJ or ROJ as shown in FIG. 6A.
The circuit is configured to detect a read signal of , and output a logic RlJ when there is a change in either the positive or negative direction.

The window pulse generating circuit 7 is configured to generate a window pulse as shown in FIG. 6C based on the output signal from the frequency divider 5 and the read signal. Phase extraction circuit 8
is configured to generate an output signal as shown in FIG. 6-2 when the window pulse transmitted from the window pulse generating circuit 7 and the pulse transmitted from the differentiating circuit 6 match. In Fig. 4, input terminal TN-1
A read signal A-1 is transmitted from the phase-locked oscillator 1-1, which causes the phase-locked oscillator 1-1 to generate an output signal of N times the frequency synchronized with the read signal A-1, and the frequency divider 2-1 divides this into 1/ N
The reference signal B-1 and the read signal A-1 are transmitted to the data discrimination circuit 3-1, and the data discrimination circuit 3-1 receives the read signal A-1. 1 and demodulates the data. At this time, in order to prevent undesired resetting due to signals with jitter, in the case of the face encoding method, it is necessary to perform phase correction using a phase with less jitter components. For this purpose, a wind pulse is used and an output signal corresponding to the above-mentioned phase is obtained as shown in FIG. 6-2.
On the other hand, the output signal of the phase synchronized oscillator 1-1 is also transmitted to the frequency divider 4 with a phase correction circuit. The frequency divider 4 with phase correction circuit includes a frequency divider 5, a differentiation circuit 6, a window pulse generation circuit 7, and a phase extraction circuit 8, as shown in FIG.

This frequency divider 5 receives the output signal generated from the phase synchronized oscillator 1-1, the read signal A-2 transmitted from the input terminal TN-2, and the frequency division start signal shown in FIG. is being applied.

Then, by transmitting the read signal A-2, the frequency-divided output signal obtained from the frequency divider 5, and the window pulse generation circuit 7, a window pulse as shown in FIG. 6C is generated. This wind pulse and the differential circuit 6 as described above
When the pulses shown in Figure 6, obtained from
The phase extraction circuit 8 outputs pulses as shown in FIG. 6-2. The pulse obtained from the phase extraction circuit 8 is transmitted to the frequency divider 5 and serves as a forced reset signal for the frequency divider 5.

That is, the phase of the read signal A-2 is detected by the wind pulse and the differential circuit output, and as shown by the dotted line in FIG. It will be corrected to correspond to the phase of . At this time, since the pulse obtained from the phase extraction circuit 8 is obtained from a phase with less jitter, correct correction can be performed. In this way, even if the frequency component of the read signal A-2 is different from the read signal A-1 and the phase difference changes accordingly, the frequency component of the read signal A-2 is different from that of the read signal A-1, and even if the phase difference changes accordingly, the output signal of the common phase synchronized oscillator can be divided. Since the signal can be used as a reference signal,
In the data discrimination circuit 3-2, the problem of errors caused by the causes mentioned above can be reliably solved.

Of course, the frequency divider with phase correction circuit described with reference to FIG. 4 and the like can be connected in place of the frequency dividers 2-2 and 2-3 in FIG.

As described above, according to the present invention, when reproducing information recorded on a magnetic medium using a phase modulation method in multi-track, data can be reliably demodulated even if some phase synchronized oscillators are omitted.

[Brief explanation of the drawing]

FIG. 1 shows a conventional data demodulation device, FIG. 2 shows a data demodulation device that partially shares a phase-locked oscillator, FIG. 3 shows an operation diagram, and FIG. 4 shows an embodiment of the data demodulation device of the present invention. FIG. 5 is an explanatory diagram of the main part, and FIG. 6 is an explanatory diagram of the operation. In the figure, 1, 1-1 are phase synchronized oscillators, 2, 2-12 to 2-3 are frequency dividers, 3, 3-1 to 3-3 are data discrimination circuits, and 4 is a frequency divider with a phase correction circuit. , 5 is a frequency divider, 6 is a differentiation circuit, 7 is a wind pulse generation circuit, and 8 is a phase extraction circuit.

Claims (1)

[Claims] 1 A data discrimination circuit to which different read signals are transmitted, a plurality of frequency dividers that divide the output signal generated from a common phase-locked oscillator, and a reference signal obtained from each of the above frequency dividers to each data discrimination circuit. In the demodulator, the reference signal is transmitted to a data discriminating circuit in which a read signal other than the read signal transmitted to the phase synchronized oscillator is discriminated. The device is provided with a phase correction circuit, and the phase of the reference signal obtained from the frequency divider is corrected by transmitting the read signal to the phase correction circuit, and each read signal is discriminated. data demodulator.