JPH0442018A - Up/down counter apparatus - Google Patents

Abstract

PURPOSE:To reflect the phase relationship of pulse input signals having the phase difference in detail on the value of a counter by generating double-edge pulses at the rise-ups and fall-downs of two pulse input signals. CONSTITUTION:Double-edge-pulse generating circuits 1a and 1b generate pulses for both edges of the rise-ups and the fall-downs of pulse input signals A and B. The circuit 1a outputs the pulse Pc, and the circuit 1n outputs the pulses Pa. A phase detecting circuit 4 outputs the pulses Pd for the pulse input signals A and B. A control circuit 5 receives the output pulses Pc, Pa and Pd of the circuits 1a, 1b and 4, forms an up-count/down-count controlling output Pe and a counted output Pf based on the pulses and sends the outputs into a counter 3. Thus, the counted value of the up/down counter is changed at every time the pulse input signals A and B are changed. The state of the change in pulse input signal is reflected on the counted value of the up/down counter in detail.

Description

[Detailed Description of the Invention] [Field of Industrial Application] The present invention relates to an up/down counter device for counting up or down two-phase pulses having a phase difference according to the phase relationship in a semiconductor device such as a microcomputer. .

[Conventional technology]

FIG. 4 is a block diagram showing the configuration of this type of conventional up/down counter device. In the figure, A and B are pulse input signals with a phase difference. 1 is pulse input signal B
As shown in the figure, this double-edge pulse generation circuit generates pulses for both rising and falling edges, and as shown in the figure, a pulse input signal B is input thereto, and a pulse Pa is output.

2 is an AND circuit to which the pulse input signal A and the output of both edge pulse generation circuits 1 are input, and outputs a pulse pb. 3 is a counter, which is equipped with a counting human power T and an up count/down counting control human power UD that controls whether to count up or down; Connected to control human power UD.

FIG. 5 is a timing chart showing the operation of the up/down counter device shown in FIG. 4. The operation will be explained below with reference to the same figure. Note that the pulse input signals A and B are out of phase, and the explanation will be made assuming that the pulse input signal B is delayed in phase than the pulse input signal A as shown in the figure.

When a rising edge B1 from "L' to "H" occurs in pulse input signal B while pulse input signal A is at "H" level, pulse Pa2 is generated from both edge pulse generation circuits 1.
occurs. This pulse Pa2 is input to the AND circuit 2, but since the pulse input signal A is at "H" level at this time, the same pulse P as the pulse Pa2 is also input from the AND circuit 2.
b2 is output, and this pulse Pb2 is input to the counting force T of the counter 3.

Here, it is assumed that the counter 3 counts up when the up-count/down-count control human power UD is "H" and counts down when it is "L2".

Further, the falling edge of the count force T is defined as the effective edge of the count. Now, when the pulse Pb2 is input to the counter 3, the level of the pulse input signal B connected to the up-count/down-count control human power UD is "H", so the counter 3 counts up at the fall of the pulse Pb2. .

Next, after the pulse input signal A falls to “L”,
When a falling edge B2 from "H" to "L" occurs in the pulse input signal B, a pulse Pa4 is generated from both edge pulse generation circuits 1. At this time, the pulse input signal A becomes "
Since it is at L° level, the output of AND circuit 2 has a pulse P.
A pulse similar to a4 is not generated, the output of the AND circuit 2 remains at the "L" level, and no valid count edge is generated in the counting force T of the counter 3.

Subsequently, after the pulse input signal A rises to "H" again, the pulse input signal B changes from "L" to "H".

When the rising edge B3 occurs, the count input T of the counter 3 is calculated based on the same idea as the rising edge B1.
The input pulse Pb6 is input to the counter 3, and the input pulse signal B is
Since it is at the "H" level, it becomes "H" and the counter 3 counts up in response to edge B3.

In Fig. 5, the explanation was made assuming that the pulse input signal B is delayed in phase than the pulse input signal A, but conversely, if the pulse input signal B is ahead in phase than the pulse input signal A, the pulse input signal Exactly the same idea as the above explanation holds true, except that during the "L2" period of the signal B, a valid count edge occurs in the counter force T and the counter 3 counts down.

[Problem to be solved by the invention]

Since the conventional up/down counter device is configured as described above, one of the two pulse input signals AB,
In this case, only the edges of the pulse input signal B could be counted. Furthermore, the other pulse input signal,
In this case, only the edges of the pulse input signal B that entered the period when the level of the pulse input signal A was either "H" or "L", in this case the "H" period, were counted. In other words, in the conventional up/down counter device, only the falling edge of the pulse input signal B during the period in which the level of the pulse input signal A is "H" is the effective counting edge of the counter 3. Therefore, since the value of counter 3 changes only every cycle of pulse input signal B, when looking at the value of counter 3, the phase of either pulse input signal A or B is delayed depending on whether it is up-counting or down-counting. The problem was that even if it was possible to determine whether the phase relationship was present, the detailed phase relationship could not be detected.

The present invention was made to solve the above-mentioned problems, and an object of the present invention is to provide an up-down counter device in which the phase relationship of pulse input signals having a phase difference is minutely reflected in the counter value.

[Means to solve the problem]

The up/down counter device according to the present invention detects each rising edge of the first and second pulse input signals.

means for generating count pulses on both falling edges; The device includes means for generating an up-count/down-count control signal according to the phase relationship of the second pulse input signal, and an up-down counter that counts up or down the count pulse according to the up-count/down-count control signal.

[Effect]

In this invention, a count pulse is generated at both the rising and falling edges of each of the first and second pulse input signals, and this count pulse is counted by an up/down counter. Every time there is a change in the second pulse input signal, the count value of the up/down counter also changes. The state of change in the second pulse input signal is reflected in detail on the count value of the up/down counter.

〔Example〕

An embodiment of this invention will be described below. FIG. 1 is a block diagram showing the configuration of an embodiment of an up/down counter device according to the present invention. In the figure, A and B are pulse input signals with a phase difference. 1a and lb are double-edge pulse generation circuits that generate pulses for both the rising and falling edges of pulse input signals A and B, respectively. A is input, and outputs a pulse Pc. Both edge pulse generation circuits 1b receive a pulse input signal B, and output a pulse Pa. 4 is a phase that outputs the "H" level when the levels of the two pulse input signals A and B are equal to "H" or "L2", and outputs the "L2 level" when one becomes "H" and the other becomes "L" Pulse input signal A in the detection circuit.

B is input, and pulse Pd is output. 5 is a double edge pulse generation circuit 1. a.1. The respective output pulses Pc and Pa of b, and the output pulse P of the phase detection circuit 4
d, and generates an up-count/down-count control output Pe and a count output Pf based on these. The counter 3 includes an up-count/down-count control human power UD and a count human power T, and the two outputs Pe and Pf of the counter control circuit 5 are input to the up-count/down count control human power UD and the count human power T of the counter 3, respectively.

FIG. 2 is a timing chart showing the operation of the up/down counter device shown in FIG. The operation will be explained below with reference to the same figure. The pulse input signals A and B are out of phase, and the explanation will be made assuming that the pulse input signal B is delayed in phase than the pulse input signal A, as shown in the figure.

The phase detection circuit 4 detects that the level of the pulse input signals A and B is “H”.
” or “L” when all are aligned.

Level: “H” when one is “H” and the other is “L”
Since the level is outputted, the output pulse Pd becomes as shown in FIG. Further, both edge pulse generation circuits 1a and lb receive pulse input signal A.

Since a pulse corresponding to each rise and fall of B is output, the output pulse Pc.

Pa becomes as shown in FIG. That is, from both edge pulse generating circuits 1a, pulses Pcl and Pc5 are generated for rising edges AI and A3 of pulse input signal A, and pulses Pcl and Pc5 are generated for falling edges A2 and A3 of pulse input signal A, respectively. A4
Pulses Pc3 and Pc7 are generated. Similarly, from both edge pulse generation circuits 1b, the rising edge, falling edge B1, B2 . B3.
B4 with pulse Pa2. Pa4. Pa6. Pa8 occurs.

The output pulses Pc, Pa, and Pd as described above are input to the counter control circuit 5, and the counter control circuit 5 generates an up-count-down count control output Pe and a count output Pf based on these pulses Pc, Pa, and Pd. Among these outputs, the count output JPf is a combination of the pulse Pc and the pulse Pa as shown in the figure. On the other hand, the up-count/down-count control output Pe changes to "H" level or "L° level" depending on the phase relationship between the pulse input signals A and B. In other words, if the phase relationship is such that pulse input signal B lags behind pulse input signal A as shown in the figure, the up-count-down count control output Pe will be at "H" level, and contrary to what is shown in the figure, pulse input signal B will lag behind pulse input signal A. If the phase relationship is such that the repulse input signal B is ahead, the up count down count control output Pe becomes "L rubel".

FIG. 3 is a circuit diagram showing one embodiment of the counter control circuit 5 shown in FIG. 1. As shown in the figure, the output pulse Pd of the phase detection circuit 4, the output pulse Pc of the both edge pulse generation circuit 1a, and the output pulse Pa of the both edge pulse generation circuit 1b are applied to the up/down switching signal generation circuit 6. , two output pulses Pg and Ph of the up-down switching signal generation circuit 6 are respectively applied to inputs S and R of an up-down switching circuit 7 consisting of an R-S flip-flop. Further, the output pulse Pc of the both edge pulse generating circuit 1a and the output pulse Pa of the both edge pulse circuit 1b are applied to the OR circuit 8. Further, the pulse of the output Q of the up/down switching circuit 7 is applied to the up/down count control output Pe of the counter 3 as an up/down count control output Pe, and the output pulse of the OR circuit 8 is applied as the count output Pf to the counting force T of the counter 3. It is being

Next, the operation of one embodiment of the counter control circuit 5 will be described. When the output pulse Pd of the phase detection circuit 4 is "H", the up/down switching signal generation circuit 6 outputs the output pulse Pc of the both edge pulse generation circuit 1a as the output pulse ph to the up/down switching circuit 7, and outputs the output pulse Pc of the both edge pulse generation circuit 1a to the up/down switching circuit 7. 1b output pulse Pa up/down switching circuit 7
The output pulses are output as output pulses Pg. Conversely, when the output pulse Pd of the phase detection circuit 4 is at "L" level, the output pulse Pc of the both edge pulse generation circuit 1a is set as the output pulse Pg to the up/down switching circuit 7, and the output pulse Pa of the both edge pulse generation circuit 1b is set as the output pulse Pg to the up/down switching circuit 7. Each of them is outputted as an output pulse ph to the up/down switching circuit 7.

The up/down switching circuit 7 consisting of an R-S flip-flop outputs "H# level" to the output Q when only the output pulse Pg of the up/down switching signal generation circuit 6 inputted to the set human power S is at the 1H level. Output pulse p of the up/down switching signal generation circuit 6 input to the reset human power R
When only h is at the "H" level, the output Q is outputted at the "L" level.

When both the output pulses Pg and Ph are at the "L" level, the state of the output Q does not change.

As in the embodiment shown in FIG. 2, if pulse input signal B is delayed in phase than pulse input signal A,
When the output pulse Pd of the phase detection circuit 4 is "H", the output pulse Pc of both edge pulse generation circuits 1a is always "L".
” level, the output pulse Pa of both edge pulse generation circuits 1b becomes “H” or “L” level. Conversely, when the output pulse Pd of the phase detection circuit 4 is “L” level, the output pulses of both edge pulse generation circuits 1a become “H” or “L” level. The pulse Pc is always at the "H" or "L" level, and the output pulse Pa of both edge pulse generating circuits 1b is always at the "L° level." Therefore, the input pulse Pg of the up/down switching circuit 7 is at "H" level.
“L” level repeats, input pulse ph is always “L”
The up/down count control output Pe, which is the output pulse of the up/down switching circuit 7, is always at the "H" level.

Contrary to the embodiment shown in FIG. 1, if pulse input signal B is delayed in phase than pulse input signal A,
From the same idea as the above explanation, up/down switching circuit 7
The up-count-down count control output Pe, which is the output pulse, is always “L”.

level.

Further, the OR circuit 8 inputs the output pulse Pc of both edge pulse generation circuits 1a and the output pulse Pa of both edge pulse generation circuits 1b, and outputs a pulse such as a combination of pulses Pc and pulse Pa as a count output Pf, and outputs the pulses of the counter 3. Output to human power T.

The up-count/down-count control output Pe and count output Pf generated by the counter control circuit 5 are given to the up-count/down count control human power UD and the count human power T of the counter 3. Here, the counter 3 has an up count down count control manual UD of “
When it is "H", it counts up, and when it is "Lo", it counts down. Further, the falling edge of the count force T is defined as the effective edge of the count. In the embodiment shown in FIG. 2, the pulse input signal B lags behind the pulse input signal A, is output from the counter control circuit 5, and is counted up at the fall of the count output Pf of the control circuit 5. In this way, the counter 3 counts up in response to all edges of the pulse input signals A and B. on the other hand,
Contrary to Fig. 2, the pulse input signal B is lower than the pulse input signal A.
If the phase relationship is such that
will count down in response to all edges of pulse input signals A and B.

Thus, in this embodiment, the pulse input signal A.

The counter 3 counts up or down in the same way as in the past, depending on the phase lead or lag relationship between pulse input signals A and B. I'm making sure the count is done.

Therefore, by knowing from the count value of the counter 3 whether up-counting or down-counting is being performed, it is possible to detect the relationship between phase advance and lag between pulse input signals A and B in the same manner as before. Of course,
The manner in which the pulse input signals A and B change is reflected in detail in the count value of the counter 3, and the detailed phase relationship between the pulse input signals A and H can also be detected from the manner in which the count value changes. becomes possible. In other words, according to the present invention, it is possible to accurately detect not only which of the pulse input signals A and B is delayed in phase, but also the extent of the phase shift. .

In the above embodiment, when the up-count/down-count control UD of the counter 3 is 'H', it is counted up, and when it is 'L', it is counted down, but the polarity may be reversed. Although the effective edge is set as a falling edge, the same effect can be obtained even if it is a rising edge.

〔Effect of the invention〕

As described above, according to the present invention, there is provided a means for generating a count pulse at both the rising and falling edges of each of the first and second pulse input signals, and a means for generating a count pulse at both the rising and falling edges of each of the first and second pulse input signals; Alternatively, an up-down counter that counts down is provided, and the count value of the up-down counter changes every time there is a change in the first and second pulse input signals. The state of change in the second pulse input signal is reflected in detail in the count value of the up/down counter, and there is an effect that the phase relationship between the two pulse input signals can be detected accurately and with high precision.

[BRIEF DESCRIPTION OF THE DRAWINGS] FIG. 1 is a block diagram showing an embodiment of the up-down counter device according to the present invention, FIG. 2 is a timing chart showing the operation of the up-down counter device of FIG. 1, and FIG.
1 is a block diagram showing an embodiment of the counter control circuit 5 shown in FIG. 1, FIG. 4 is a block diagram showing a conventional up-down counter device, and FIG. 5 is an operation of the up-down counter device shown in FIG. 4. FIG. In the figure 1. la and lb are both edge pulse generation ports,
2 is an AND circuit, 3 is a counter, 4 is a phase detection circuit, 5
is a counter control circuit. Note that the same reference numerals in each figure indicate the same or corresponding parts.

Claims (1)

[Claims] (1) An up-down counter device that receives a first pulse input signal and a second pulse input signal, the rise of each of the first and second pulse input signals,
means for generating a count pulse at both falling edges; means for generating an up-count-down count control signal according to the phase relationship of the first and second pulse input signals; and means for generating the count pulse according to the up-count-down count control signal. An up/down counter device comprising an up/down counter that counts up or counts down.