JPH0374325B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION Field of the Invention The present invention relates to an incremental digital converter for converting two position signals into a digital quantity representing position, comprising: a pulse generator; a set value generator; a reversible position counter; a regulator; and a signal generator; the pulse generator generates two out-of-phase position signals indicative of the position and direction of movement of two oppositely movable objects. the setpoint generator is for transmitting a predetermined digital target value, and the reversible position counter is for forming an actual position value of the object from a direction signal and a clock pulse. the regulator compares the setpoint value with the actual position value and adjusts the object according to the control deviation; the signal generator includes an edge detector and a direction discriminator; , the edge detector derives clock pulses counted by a position counter from each edge of one of the position signals, and the direction discriminator has one clock pulse of the edge detector. and on the other hand the two position signals, from which a direction signal determining the counting direction of the position counter is derived.

DESCRIPTION OF THE PRIOR ART Pulse generators in the normal case have a very high resolution, so that a large number of position pulses are generated even if the movable object moves only very slightly.
Due to such a large resolution, position pulses can be generated even if the movable object moves in a direction opposite to the desired direction of movement, for example due to vibrations or vibrations in the stationary state. According to known transducers of the type mentioned at the outset, such disturbance pulses (malfunction pulses) cause the occurrence of pulses to be counted by a position counter if a movement opposite to the predetermined direction is detected. The number of counting pulses that occur after the disturbance movement has shifted in a given direction is the sum of the counting pulses sent in the opposite direction. Only when it exceeds the number of pulses is the position counter used to count the counting pulses. In this case, the counting state of the position counter does not always correspond exactly to the position of the moving object. In any case, there is no correspondence while the moving object is moving in the wrong direction, and even if it corrects itself to the correct direction of movement, no correspondence can be obtained until the object returns to the position from which it was first reversed. If the movable object starts to move and the fault pulse counter has not yet counted pulses, the fault pulse counter is first set to the "proper travel distance pulse" before starting the actual position actual value counting process.
The count value should be set to zero by This has the disadvantage in many applications, for example in rotary table indexing controls and in many machine tool controls, that the first moving part is not detected. Furthermore, in the case of known transducers, the clock pulses are derived only from the edge of one position signal. Therefore, it is not possible to phase-discriminate the position signals reliably to determine the movement direction, because on the one hand the tolerance of the impulse count percentage of the position signals is relatively large, e.g. reaching ±10%, and on the other hand, the difference between the two position signals This is because the phase difference may deviate from the normal phase difference of 90° by as much as ±45°, that is, by as much as 50%. Errors due to such tolerances are directly introduced into the calculation of the actual position value.

Object of the invention The problem on which the invention is based is to provide a transducer of the type mentioned at the outset, which measures the position of a moving object with a fairly high degree of accuracy, even if it moves in the wrong direction of movement. .

Structure of the Invention According to the present invention, this problem is solved by a direction discriminator having a first flip-flop circuit, a second flip-flop circuit, and an addition element, and the first flip-flop circuit is directly connected to a first position signal. The second flip-flop circuit is configured as a D-type flip-flop circuit to which the second position signal is supplied via a delay element, and the addition element is configured as a D-type flip-flop circuit to which the second position signal is supplied via a delay element. both D-type flip-flop circuits are connected downstream to supply a direction signal to a position counter, said edge detectors detecting one position signal at the respective edge of the other position signal as well. Similarly, the clock pulses of the edge detector are canceled by being arranged to be applied to the clock inputs of both D-type flip-flop circuits.

Effects of the Invention According to such a configuration, the count value of the position counter always corresponds to the position of the movable object. Counters for fault pulses are omitted. Since all edges of both position signals are detected, it has the advantage of measuring changes in the moving direction of a moving object as early as possible with high resolution. Discrimination of the direction of movement is performed at low cost using both D-type flip-flop circuits and summing elements. The use of a delay element ensures that the value of the first position signal before one edge of this position signal is equal to the value of the second position signal before the subsequent edge of the second position signal. The value of the position signal can be directly compared with the adding element for direction discrimination. It also becomes possible to compare the amplitude value preceding one edge of the first position signal with the amplitude value immediately following one edge of the second position signal.

Further, a delay element having a delay time smaller than the delay time of the delay element pre-connected to the D-input side is connected between the output side of the edge detector and the clock input side of the first D-type flip-flop circuit. Then it is advantageous. As a result, the amplitude values of other position signals are
Immediately after the edge of this position signal, it becomes stabilized before being sampled.

The delay element can be constructed as an integrated RC-element. This has a very simple structure as it consists only of a resistor and a capacitor.

It is advantageous to connect a frequency divider which divides the pulse frequency by 1/4 between the output of the edge detector and the clock pulse input of the position counter. This frequency divider eliminates the frequency fluctuations that occur in the clock pulses derived from all edges of the position signal due to tolerances in the percent duty coefficients of the two position signals. That is, in that case the frequency divider transfers only the fourth clock pulse in each case to the position counter for counting, and the time intervals of all the fourth clock pulses are such that the two position signals have different impulse coefficient percentages. This is because if the moving speed of the moving object is constant, then it will be constant.

Furthermore, the frequency divider can be provided with a reversible pulse counter, and the counting direction input side of the reversible pulse counter can be connected to the output side of the direction discriminator. The counting direction of this pulse counter is therefore reversed at the same time as the direction of movement of the moving object is reversed, so that erroneous counting when the direction of movement is reversed is prevented.

DESCRIPTION OF EMBODIMENTS The present invention will now be described in detail with reference to illustrated embodiments.

The position adjustment circuit shown in FIG. 1 includes a regulator 1, a servo motor 2, a pulse generator 3, a signal generator 4, a frequency divider 5, a position counter 6, and a set value generator 7.

The digital setpoint value supplied by the setpoint generator 7 is compared with the digital actual position value supplied by the position counter 6 in the regulator 1 . The difference or adjustment deviation obtained during the comparison is converted into an analogue adjustment signal and fed to the servo motor 2 via a connection line 8. Depending on the aforementioned control signals, the servomotor 2, possibly via a transmission with a bevel gear 9 and a spindle 10, moves a movable object 11, for example the table of a machine tool, by means of a bidirectional arrow 12. Adjust in one or the other direction of movement as shown.

The rotational angular position, rotational speed and rotational direction of the shaft 13 of the servo motor 2, and thus the position and movement direction of the movable object 11, are determined by a pulse generator having two output lines 14 and 15 and coupled to the shaft 13. 3 into two square wave position signals A and B having a phase difference of approximately 90° with respect to each other and a duty factor percentage (ratio of pulse duration to period) of approximately 50%. Depending on whether one position signal A leads or lags the other position signal B in phase, it indicates in which direction the servo motor 2 and the movable object 11 are driven. On the other hand, the number of pulses of both position signals A and B from the movement start time is
It is a measure of the distance traveled or the position of the movement based on the initial position of the movement.

For this purpose, the pulse generator 3 has a reference pattern 16 driven by the servo motor 2, which patterns are spatially offset from each other in accordance with the 90° phase difference of the desired position signals. It is scanned by the sensor and converted into square wave position signals A and B via pulse forming devices 17, 18.

Position signals A and B are fed to a signal generator 4.
The signal generator 4 sends a direction signal R to an output line 19 from the sign of the relative phase difference between the position signals A and B.
and one clock pulse T from every edge of both position signals A and B respectively to the second output line 20.
Send to.

For this purpose, the signal generator 4 has a direction discriminator 21 and a pulse edge detector 22.

The direction discriminator 21 includes two D-type flip-flop circuits 23 and 24 and a flip-flop circuit 2.
Delay element 25 pre-connected to the D-input side of 4
, a second delay element 26 connected upstream to the clock input C of both flip-flop circuits 23 and 24;
and a summing element 27 in the form of an exclusive-OR element connected to the Q-output ("true" output) of . The delay time t ₁ of the delay element 25 is one of the position signals A and B.
is significantly shorter than half of the smallest period, and the delay time t ₂ is shorter than t ₁ . Delay elements 25 and 2
6 are operated to delay the leading and trailing edges of their input signals by the same delay time t ₁ or t ₂ .

The edge detector 22 has an input side connected to the lines 14 and 15.
an exclusive OR element 28 connected to and a connecting line 29
a delay element 30 which is connected to the output of the exclusive OR element 28 via a delay element 30 and has the same delay time _t1 as the delay element 25, and another exclusive OR element 31, in which case the exclusive OR element One input side of 31 is connected to the output side of the delay element 30 via a connection line 32, and the other input side is connected to the connection line 33.
and the exclusive OR element 2 directly via the connecting line 29
It is connected to the output side of 8. The clock pulse T occurring at the output of the edge detector 22, ie the exclusive OR element 31, is fed via a connection 34 to the input of the delay element 26 on the one hand, and is inverted via the negation element 35 on the other hand. It is applied to output line 20 as a clock pulse.

The frequency divider 5 has a reversible pulse counter 36, which divides the clock pulses supplied to the clock input side of the reversible pulse counter via the line 20 into 1/4.
i.e. 1 for each 4 clock pulses.
One clock pulse output T ₄ is sent to an output line 37 connected to the clock input C of the position counter 6.

The frequency divider 5 also outputs the output signal of the pulse counter 36.
It has a NAND element 38 that logically connects Q ₁ and Q ₃ ,
The NAND element 38 is connected via a delay element 39 to one input side of a NAND element 40 having a jump characteristic.

The output signal Co is also supplied to the other input side of the NAND element 40 via another delay element 41. The delay time t ₃ of delay elements 39 and 41 is shorter than t ₁ but can also be chosen equal to t ₁ .

The output side of the NAND element 40 is connected to the set input side P of the pulse counter 36 via the connection line 37, and by applying the 1- signal to the set input side, the counter 36 is connected to the set input side P of the pulse counter 36. It is preset to the number added to ₁ to _P4 in the form of a binary signal. This number depends on whether the direction signal R applied directly to the input P ₁ or inverted via the negation element 42 to the input P ₃ is a 1-signal or a 0-signal. , the binary number "0001" or decimal number "1", or the binary number "0100" or decimal number "4".

The direction signal R is also supplied to the counting direction control inputs U/D of counters 6 and 36, which counters R
If is a 1-signal, it “counts up” and R becomes 0.
- “Countdown” for signals.

Next, the operation of the adjusting circuit shown in FIG. 1, such as an incremental digital converter composed of a signal generator 4, a frequency divider 5, and a position counter 6, will be explained using the same reference numerals in FIGS. 2 to 4. This will be explained in detail using

Position signals A and B in Fig. 2 require the position counter 6 to perform a countdown operation (R="0").
A signal S (see FIGS. 1 and 2) is produced by an exclusive OR element 28 from these position signals. The frequency of signal S has twice the magnitude of the frequency of one of position signals A and B, and the impulse coefficient percentages are the same at 0.5. Therefore, at the output of the delay element 30, there is a time difference with respect to the signal S.
Signal S′ delayed by t ₁ (see Figures 1 and 2)
occurs. This signal S' is once again logically combined with the undelayed signal S in the exclusive OR element 3 position, thereby providing the position signals A and B on the connection line 34.
A clock pulse T (see FIGS. 1 and 2) occurs which has a frequency significantly higher than the frequency of .
The leading edge of clock pulse T coincides with all edges of position signals A and B. The duration of clock pulse T corresponds to the delay time t ₁ of delay element 30. The clock pulse T is inverted by a negation element 35, which then causes the counting operation of the counter 36 to be delayed somewhat with respect to the edges of the signals A and B by the leading edge of the clock pulse applied to the clock input C. (0
-1 transition edge), the amplitude of the direction signal is stabilized after alternating changes in the amplitude of the direction signal R, synchronized with the leading edge of the clock signal T, before opening the counting operation. It is from.

The clock pulse T is also supplied to the clock input C of the flip-flop circuits 23 and 24 as a clock pulse T' delayed by a delay time _t2 .
The position signal A is directly supplied to the D-input side of the flip-flop circuit 23, while the position signal B is supplied to the D-input side of the flip-flop circuit 24 through the delay element 2.
Position signal delayed by delay time _t1 by 5
Supplied as B′. Flip-flop circuits 23 and 2 of the information supplied in each case to the D-input side.
4 is stored in each case at the leading edge (0-1 transition edge) of the clock pulse T' supplied to the clock input C.
D-type flip-flop circuit 23
When a 1- signal is applied to the D- input of C and 24 and a clock pulse is subsequently applied to the clock input C, the D-type flip-flop circuit in question becomes Q-.
The circuit state is such that a 1- signal is also generated on the output side. If a 1-signal has already been generated on the Q-output side, that 1-signal is held. Each information change (1-0 change or 0-1 change) on the D-input side is triggered by a subsequent clock pulse.
It is remembered by T′. The adder element 27 generates a direction signal R="1"("countup") whenever the signals on the Q-output sides of the flip-flop circuits 23 and 24 are different, and otherwise generates a direction signal R="0". ” (“countdown”) occurs. Therefore, the position signal A immediately preceding one edge of the position signal B is in front of the following edge of the position signal A.
, or if the position signal B after one edge of the position signal B corresponds to the position signal A immediately after the following edge of the position signal A, then the summing element 2
7 generates a 0- signal ("countdown").
The clock pulse is derived from the edge of the position signal, and the clock pulse detects (memorizes) the value of the position signal immediately before the edge of the position signal that triggers the clock pulse. By delaying by the time t ₁ by the delay element 25, the clock pulse T derived from the edge of the position signal B is always a time t ₁ later than the delayed (actually sampled) position signal B'. (see B' and T in Figure 2). The clock pulse also detects the value of position signal A that occurs immediately after the edge of position signal A that triggers the clock pulse. Therefore, the clock pulse that actually samples the position signals A and B in order to stabilize the position signal A to a new value after the edge that triggers the clock pulse in question and before the clock pulse T' occurs.
T' is delayed by a time t ₂ with respect to the clock pulse T, which is derived directly from the edge of the position signal. Also, as mentioned above, t ₂ is chosen to be smaller than t ₁ since clock pulse T' should be in front of the edge of the position signal B that triggers it. Also, with the relative phase positions of the position signals A and B shown in FIG.
If 6 is made to count up instead of counting down, the circuit function (&B) v (A&)
Instead of an exclusive OR element 27 (in which case in the circuit function "&" indicates an AND combination and "v" indicates an OR combination) which detects the (non-equivalence) of the position signals A and B according to , circuit function (A&B) v(
A coupling element that detects &) can also be used as the addition element 27.

In addition, the purpose of providing the frequency divider 5 will be briefly explained with reference to FIG. be. Such asymmetric position signals A and B are shown in FIG. 4, although the asymmetry is exaggerated for clarity.
As a result, the clock pulses T (see FIG. 4) derived from the edges of these position signals A and B also have different spacings. Therefore, even if the shaft 13 rotates uniformly and the object 11 moves uniformly, the actual value detection in the position counter 6 does not take place uniformly, so that the adjustment process becomes unstable or It becomes impossible to make accurate comparisons with the set values. If the frequency of the clock pulse is divided by one-fourth, the clock pulse output _T4 of the frequency divider 5 will have a uniform pulse interval. This is because although the impact coefficient percentages of the position signals A and B may actually be different, the frequency or period of these signals is constant if the speed of the moving object is constant. Furthermore, the position counter 6 is constructed with a relatively small counting capacity (for the same maximum counting distance section of the moving object) for a position counter that switches step by step on every clock pulse or on every other clock pulse.

The binary counter 36 of the frequency divider 5 generates an output pulse Co (see FIG. 2) at each fourth clock pulse, i.e. the frequency divider 5 generates a clock pulse output T ₄ at every fourth clock pulse. In order to do this, the counter 36 is again set by the respective clock pulse output T ₄ to the initial value given via the preset inputs P ₁ to P ₄ by the direction signal R, i.e. "0001" = 1. or “0100”
=4. In the case of a count-up, the count value of the counter 36 is a decimal number, and the number sequence 1, 2, 2, etc.
It changes to form 3, 4, 1, 2, 3, 4, 1, 2... When changing from "4" to "1", the counter 36 temporarily becomes the count value "5" = "0101", in which case both output signals Q ₁ and Q ₃ (see Figure 3) are " 1”. Therefore, NAND element 3
8 produces a 0-signal S ₃₈ which is delayed by a delay element ₃₉ by a time t ₃ and
It is inverted by the NAND element and supplied as a reset pulse _T4 to the reset input P of the counter 36 (or as a clock pulse output to the output of the frequency divider 5). Thereby, the counter 36 is reset to "1"(="0001"), so that the counting process continues as 1, 2, 3, . . . .

In the case of countdown (R="1"), counter 3
The count value of 6 is obtained by reversing the above sequence, that is, the sequence 4,
It changes to form 3, 2, 1, 4, 3,... When changing from "1" to "4", the counter 36 generates a 0-pulse Co (see Figure 2),
- Pulse Co is delayed by time t ₃ by delay element 41 and inverted by NAND element 40, so that a reset pulse or clock pulse T ₄ occurs at the output of NAND element 40; This pulse resets the counter 36, thus terminating the 0-pulse Co. The duration of the clock pulse output then corresponds to the delay time _t3 .

The position counter 6 counts the clock pulses T ₄ supplied during the period of 1-signal R in the count-up direction, and counts the clock pulses T ₄ supplied during the period of the count-down signal R=0 in the count-down direction. The count value of the position counter 6 always corresponds to the actual value of the position of the movable object 11. This actual value is compared in the regulator 1 with the setpoint set in the setpoint generator 7, so that, if an adjustment deviation exists, the position of the movable object 11 is readjusted accordingly.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a position adjustment circuit having a transducer according to the invention, and FIGS. 2 to 4 are diagrams showing the time variations of signals occurring in the position adjustment circuit of FIG. 1...Adjuster, 2...Servo motor, 3...Pulse generator, 4...Signal generator, 5...Frequency divider,
6...Position counter, 7...Set value generator, 11...
…object.

Claims (1)

[Claims] 1. An incremental digital converter that converts two position signals into a digital quantity representing a position, comprising: a pulse generator 3; a set value generator 7; a reversible position counter 6; a regulator 1; a signal generator 4; B, the set value generator 7 sends out a predetermined digital target value, and the reversible position counter 6 calculates the actual position value of the object 11 from the direction signal R and the clock pulse. the regulator 1 compares the setpoint value with the actual position value and adjusts the object 11 in accordance with the control deviation; the signal generator It has a detector 22 and a direction discriminator 21, the edge detector 22 derives the clock pulses counted by the position counter from each edge of one of the position signals B, and the direction discriminator The edge detector 22 is connected to the edge detector 21 on the one hand.
clock pulse T is supplied, on the other hand the two position signals A, B are supplied, and the position counter 6 is supplied with a clock pulse T.
In the incremental digital converter, the direction signal R that determines the counting direction of the flip-flop is derived from the position signals A and B. and an adder element 27, and the first flip-flop circuit 23 has a first
The second flip-flop circuit 24 is configured as a D-type flip-flop circuit to which the position signal A of the second flip-flop circuit 24 is directly supplied.
The summing element 27 is configured as a D-type flip-flop circuit to which the position signal B is supplied via a delay element 25; The edge detector 22 forms a clock pulse T at each edge of the other position signal A in the same way as the one position signal B. The clock pulse of the edge detector 22 is
Incremental digital converter, characterized in that it is supplied to the clock input C of the flip-flop circuits 23, 24.