SE455231B - INCREMENTAL DIGITAL CONVERTER - Google Patents

Description

15 20 25 30 35 455 231 2 incorrect rotation, but also when reversing to the correct direction of movement until it has re-measured the original turning point. If the error pulse counter is still filled at the beginning of a movement of the moving object, it must first be empty counted by "correct path pulses" before the actual position-is-value calculation process can begin. This is an inconvenience on many occasions of use, for example in the index control of a turntable and many machine tool controls, since the first part of the movement is not perceived here. Therefore, in the known converter, the beat pulses are derived only from the flanks of one position signal.

This does not allow reliable phase discrimination of the position signals to determine the direction of movement, because firstly the tolerances at the sensing conditions for the position signals are relatively large, eg amount to I 10%, while secondly the phase shift of the two position signals from the normal phase shift of 900 may deviate by 1 45 °. ie by 50%. Such tolerance errors are included directly in the calculation of the position-is-value. The object of the invention is a transducer in the initially known technique, which determines with greater accuracy the position of the moving object even when moving in the false direction of movement.

This object is fulfilled according to the invention in that said flip-flop is a D-flip-flop, the D-input of which is applied to the position signal via a delay means, the direction discriminator comprising partly a second D-flip-flop, the D-input of which is directly supplied to the second position signal after the two D-flip-flops are connected summing means, that both inputs of the edge detector are directly supplied to the position signals and that the pulses from the flank detector are supplied to the beat inputs of the D-flip-flops.

In this design, the position counter, the count value, always corresponds to the value of the position of the moving object. No error heart rate monitor is needed. Sensing all the edges of the two signals has the advantage that a change in the direction of movement of the moving object is determined at the earliest possible time with a high resolution. Determination of the direction of movement takes place by using the D-flip-flops and the summing means with a small material accumulation. The delay means ensures that the value of this position signal present in the summing means immediately before an edge of one position signal can be compared with the value for direction discrimination present before the next edge of the other position signal. Likewise, the amplitude value present before a flank of one position signal can be compared with the amplitude value present immediately after a flank of the other position signal.

Thus, it has preferably been ensured that a delay means is inserted between the output of the flank detector and the clock input for one D-flip-flop, the delay time of which is less than the delay time of the delay means connected in front of the D-input. In this way it is ensured that the amplitude value of the second position signal has stabilized before the sensing immediately after the edge of this position signal.

The delay means may be integrating RC means. Their construction is especially simple, since they can handle only an ohmic resistor and a capacitor.

Between the output of the edge detector and the clock pulse output of the position counter, a pulse frequency with four dividing frequency dividers is preferably connected. This frequency divider eliminates through frequency tolerances in the sensing conditions for the two position signals the frequency variations in the rate pulses derived from all the edges of the position signals, since it transmits only every fourth pulse to the position counter in terms of counting and counting. the two position signals at a constant speed of movement of the moving object, the time intervals of all fourth clock pulses are constant.

The frequency divider may also comprise a reversible pulse counter, the counting direction input of which is connected to the output of the direction discriminator. The calculation direction of this pulse counter is then reversed at the same time as the reversal of the direction of movement of the moving object, so that erroneous calculations when reversing the direction of movement are avoided. The invention and its further embodiments are described in more detail below in connection with the accompanying drawing, which shows a preferred embodiment. Fig. 1 is a block diagram of a position control circuit with a converter according to the invention and fig. 2-4 show time diagrams of signals which appear in the position control circuit according to fig. 1.

Den i fíg. The position control circuit shown in 1 contains a controller 1, a setting motor 2, a pulse sensor 3, a signal generator 4, a frequency divider S, a position counter 6 and a setpoint sensor 7.

A setpoint digitally represented by the setpoint sensor 7 is compared with a position-is-value digitally represented by the position counter 6 in the controller 1. A difference occurring in the comparison, namely the control deviation, is converted into an analog display signal and is supplied via a line B to the disengagement motor 2. This disguises, depending on this adjustment signal, possibly via a gear with conical wheels 9 and a spindle 10, a movable object 11, e.g. the table of a machine tool, in one or the other, indicated by the double arrow 12, the direction of movement. The rotational angle position, the number of revolutions and the direction of rotation of the shaft 13 of the displacement motor 2 and thus the position and direction of movement of the movable object 11 are converted by the pulse sensor 3 also connected to the shaft 13 with two output lines 14 and 15 to two approximate 90 ° A and B with a rectangular course and a pulse ratio (ratio between pulse duration and period duration) of about 501. Since one position signal A comes before or after the other position signal B in phase position, this means that the disengagement motor 2 and the movable object 11, respectively. driven in one direction or another. The number of pulses of the two position signals A and B since the beginning of the movement, on the other hand, is a measure of the back-to-back wave and the position of the moving object 11 relative to the starting point of the movement.

For this purpose, the encoder ß contains a raster scale 16 driven by the displacement motor 2, the ster aster being sensed by being displaced in space corresponding to the desired 900-phase shift of the position signals, sensors and converted over the pulse shapers 17,18 into the rectangular position signals and B. 10 15 20 25 30 35 5 455 231 The position signals A and B are applied to the signal generator 4.

This derives from the sign of the relative phase shift of the position signals A and B a direction signal R on an output line 19 and derives from all the flanks of the position signals A and B each a clock pulse T on a second output line 20.

For this purpose, the signal generator 4 contains a directional discriminator 21 and a flank detector 22. The directional discriminator 21 contains two D-flip-flops 23 and 24, a delay means ZS connected in front of the D-input to the flip-flop 24, one in front of the clock input C of both flip-flops 23 and 24 connected second delay means 26 and a summing means 27 in the form of an EXOR gate connected to the Q outputs ~ (the "true" outputs) from the two flip-flops 23 and 24. The delay time t1 of the delay means 25 is substantially less than half the minimum period duration of one of the position signals A and B and the delay means 25 and 26 cause a delay of the front and rear flanks' for their delay time tz is less than t1. input signals with the same delay time t1 resp. tz.

The flank detector 22 contains on the input side an EXOR gate 28 connected to the lines 14 and 15, a delay means 30 connected to the output from the EXOR gate 28 via a line 29 with the same delay time t1 as the delay means 25 and a further EXOR gate 31 , one input of which is connected via a line 32 to the output of the delay means 30 and the other input of which via a line 33 and the line 29 is directly connected to the output of the EXOR gate 28. Those at the output of the flank detector 22 resp. The beat pulses T generated by the EXOR gate 31 are applied via a line 34 on one side to the input of the delay means 26 and on the other side via a NON means 35 such as an inverted beat pulse T to the output line 20. The frequency divider S contains a reversible pulse counter 36. which divides the beat pulses T applied to its beat input C over line 20 by four, i.e. generates at every fourth beat pulse T an output beat pulse'f4 on an output line 37, which is connected to the beat input C of the position counter 6.

Furthermore, the frequency counter 5 contains an output signals Q1 and Q3 from the pulse counter 36 connecting NAND gate 38, which is connected via a delay means 39 to one input of a NAND gate 40 with tilt attenuation.

Furthermore, the output signal Co is supplied via a further delay means 41 to the second input of the NAND gate 40.

The delay times ts of the delay means 39 and 41 are less than t1, but they can also be selected equal to this.

The output of the NAND gate 40 is connected via the line 37 to a position input P of the pulse counter 36, which on receiving a 1 signal causes the counter 36 to be preset to a number which in the form of binary signals lies on the input signal. arna P1-P4. For this number, the binary number "Q001" applies, ie. the decimal number 1, or the binary number "0100", ie. the decimal number 4, since the direction signal R applied directly to the input P or to the input P3 via a non-means device is a 1 signal or a 0 signal.

The direction signal R is also applied to the counting direction control inputs U / D of the counters 6 and 36, the counters at a 1-signal R counting "forward" and at a 0-signal R "backwards".

In the following, the mode of operation of the control circuit shown in Fig. 1, especially for the incremental digital converter formed by the signal generator 4, the frequency divider S and the position counter 6, will be described in more detail with simultaneous reference to Figs. 2-4.

From the position signals A and B in Fig. 2, the relative phase position of which would require a bake-back calculation in the position counter 6 (R = "0"), the BXOR gate 28 generates the signal S (Figs. 1 and 2), the frequency of which is twice as high as the for one of the position signals A and B and which likewise has a pulse ratio of 0.5. Therefore, at the output of the delay means 30, a signal S 'delayed by the time t1 appears relatively (Figs. 1 and 2).

This signal S 'will in gate 31 once again be subjected to an EXOR function together with the undelayed signal S, so that on line 34 the clock pulses T (Figs. 1 and 2) appear, the frequency of which, however, is four times as high as that of the position signals A and B. The leading edges of the beat pulses T coincide with all the edges of the position signals A and B. The duration of the beat pulses T corresponds to the delay time t1 of the delay means 30. The beat pulses T are inverted by the NOT means 35, when the further connection of the counter 36 takes place through the leading edges (0-1 transitions) of the clock pulses T applied to the clock input C, but must be somewhat delayed relative to the edges of the signals A and B, so that after an amplitude change of the direction signal R synchronized with the leading edges of the clock signal T, its amplitude has stabilized before the counting process begins.

The beat pulses T are also supplied to the beat inputs C of the flip-flops 23 and 24 as delayed beat pulses T 'with the delay time tz. While the position signal A is applied directly to the D input of the flip-flop 23, the position signal B is applied to the D input of the flip-flop 24 as through the delay means 25 down the delay time t1 delayed position signal B '. The storage of the information present in the current inputs at the D-inputs in the flip-flops 23 and 24 takes place with the leading edge (0-1-transition) of a clock pulse T 'applied to the clock input C, i.e. when a 1 signal is present at the D input of one of the D flip-flops 23 and 24, and since a clock pulse appears at the clock input C, the D-flip-flop in question is flipped, so that at its Q-output a -signal occurs. If there is already a 1 signal at the Q output, this 1 signal remains. Each information change (1-D or O-1 transition) at the D input is first stored with the following clock pulse T '. The summing means 27 always generates a direction signal R = "1" ("forward count"), when the signals on the Q outputs from the flip-flops 23 and 24 are different, and otherwise the direction signal R = "0" ("reverse count"). Therefore, if the position signal B immediately before a flank of the position signal B matches the position signal A before the following edge of the position signal A or when the position signal B after a flank of the position signal B corresponds to the position signal A immediately after the next edge of the position signal A, the summing means generates 27 a 0 signal ("reverse counting"). When the clock pulses are derived from the edges of the position signals, but a clock pulse in the present case must also determine (store) the value of the position signal immediately before the edge pulse triggering of the position signal, the position signal B is delayed by the delay means 25 with time t1. the clock pulses T derived from the position signal B always occur the time t1 before the edge of the delay (in fact sensed) position signal B '(cf. B' and T in Fig. 2). On the other hand, however, the clock pulses must also determine an instantaneous value of the position signal A occurring immediately behind a same triggering edge of the position signal A.

Therefore, the position signals A and B, in fact sensing the beat pulses T ', are also delayed the time tz relative to the beat pulses T derived directly from the edges of the position signals to ensure that the position signal A has stabilized on the new value after its beat pulse in question. , before the beat pulse T 'occurs. Since the clock pulses T ', as stated, must also be before the same triggering edges of the position signal B, tz has 1. Instead of that antivalence (difference) of the position signals A and B according to the function (Ä GB) v (A & F) determining the EXOR gate 27 (where in the switching function "G" means an AND function and "v" an OR function) an equivalent according to the function (A & B) v (Ä & F) determining means can also be arranged as summing means 27 , when the counters 6 and 36, which both receive the direction signal R, at the relative phase position shown in Fig. 2 for the position signals A and B, are not to count backwards but forwards. The purpose of the frequency divider 5 shall be briefly described in connection with Fig. 4: In practice, the pulse ratio conditions for the position signals A and B may deviate from 501, e.g. due to manufacturing tolerances for the encoder 3. In this way, asymmetric position signals A and B are shown in Fig. 4, however, for the sake of clarity. The consequence is that clock pulses T (Fig. 4) derived from the flanks of these position signals A and B also have different distances. Despite uniform rotation of the shaft 13 and uniform movement of the object 11, therefore, the value determination in the position counter 6 would take place differently, so that the regulation process could become unstable or the setpoint, which should appear, could not be achieved exactly. On the other hand, due to the frequency variation of the clock pulses to a quarter, a uniform pulse distance arises at the output clock pulses T¿ from the frequency divider 5, since in practice the pulse ratio of the position signals A and B may be different but their frequency and period duration are variable for constant duration. constant. In addition, one can manage the position counter 6 with a smaller counting capacity relative to that of a position counter (for a total of less than t 10 15 20 ZS 30 35 40 'J 455 231 ma maximum distance traveled, which is to be calculated for the moving object).

In order for the binary counting counter 36 in the frequency divider S to generate an output pulse Co at every fourth clock pulse T (Fig. 2) and the frequency divider 5 at every fourth clock pulse to generate an output clock pulse T4, the counter 36 is recalculated by each output clock pulse T ¿Again to an output value determined by the direction signal R over the preset inputs P1-P¿, i.e. either "0001" - 1 or "C100" - 4. When counting forward, the count value of the counter 36, written decimally cyclically, undergoes the number sequence 1, 2,3,4,1,2,3,4 1,2 ... etc. When switching from "Å" to "1", the counter 36 assumes a transient count value "S" - "0101", at which the output signals Q1 and Q3 (Fig. 3) are both equal to "1". This is determined by the NAND gate 38 by outputting an O signal S38, which through the delay means 39, delayed by a time ts and inverted by the NAND gate, is returned to the reset input P of the counter 36 as the reset pulse (respectively to the output of frequency divider S as output pulse) T4.

Thereby the counter 36 is returned to "1" (= "00O1"), so that the counting process with 1,2,3, ... continues.

When counting backwards (R - "1"), the count value of the counter 36 undergoes the mentioned sequence of numbers in reverse, ie. in the order 4,3,2,1,4,3, ... etc. Upon transition from "1" to "4", the sensor 36 generates an 0-pulse Co (Fig. 2), which is delayed by the delay means 41 by the time ts and inverted by the NAND gate 40, so that at the output of the NAND gate 40 back the position or clock pulse T4 appears, which triggers the reset of the counter 36 and thus determines the end of the 0-pulse Co.The duration of the output clock pulse also corresponds to the delay time ts.

The position counter 6 counts the clock pulses T4 applied to it during the duration of the 1-signal R in the forward direction and the clock pulses T¿ applied to it during the duration of the reverse signal R-0, so that the count value of the position counter 6 always corresponds to is the value of the position of the movable object ll. This actual value is compared with the setpoint set in the setpoint counter 7 in order to correspondingly post-adjust the position of the movable object 11 in the event of a control deviation.

Claims (5)

455 231 10 PATENT REQUIREMENTS An incremental digital converter for converting two phase-shifted position signals from a encoder (3), representing the position and direction of an object (11) moving in two opposite directions, to a position digitally representing quantity with a reversible position counter (6 ) and with a counting signal (R) and clock timing pulses to be counted from the position counter (4) from the position signals (A and B) determining the direction of the position counter. comprising a flank detector (22) conducting a clock pulse (T) from each edge of one position signal and a directional discriminator (21), which for generating the direction pulses (R) of the flank detector (22) can be supplied on the one hand T) and on the other hand the position signals (A, B) and which have a flip-flop (24) to which one position signal (B) can be applied, characterized in that said flip-flop is a D-flip-flop (24), the D input, the position signal (8) is supplied via a delay means (25), that the direction discriminator (21) comprises on the one hand a second D-flip-flop (23). whose D-input is directly applied to the second position signal (A), partly a summing means (27) connected to the two D-flip-flops (23, 24), that both inputs of the edge detector (22) are directly applied to the position signals (A. B) and that the pulses from the edge detector are applied to the clock inputs (C) of the D- flip-flops (23, 24). Converter according to Claim 1, characterized in that a delay means (26) Xr is inserted between the output of the edge detector (22) and the stroke input (C) of one D-flip-flop (24), the delay time (t2) of which is less than the delay time (t1) of the delay means (25) connected in front of the D input. Converters according to claim 1 or 2, characterized in that the delay means (25, 26) are integrating RC means. 11 455 231 4. A circuit according to any one of claims 1-3, characterized in that a pulse frequency with four dividing frequency dividers (5) is connected between the output of the edge detector (22) and the clock pulse input (C) of the position counter (6). . A converter according to claim 4, characterized in that the frequency divider (S) comprises a reversible pulse counter (36). whose counting direction input (U / D) is connected to the output of the direction discriminator (21).