JPH02147910A - Encoder signal abnormality detection circuit - Google Patents

Abstract

PURPOSE:To enable application to an open collector output type by counting an encoder pulse within an encoder generation circuit until a next Z-phase signal is inputted after the inputting of one Z-phase signal to compare the results with a set rated value of the encoder output pulse per rotation. CONSTITUTION:An encoder pulse generation circuit 2 is provided with an increment/decrement counter to count an encoder pulse between the application of a Z-phase signal and the application of a next Z-phase signal. On the other hand, the number of rated encoder pulses per rotation of an encoder applied is set on an encoder pulse setting device 1 beforehand to determine an absolute value of an output data of the circuit 2 with an absolute value output circuit 3. Then, the absolute value is compared with a data of the setting device 1 by a first comparator 4 and a data of the circuit 3 is compared with 0 by a second comparator 5. Outputs of both the comparators 4 and 5 are inputted into an OR circuit 6 to detect and error.

Description

Detailed Description of the Invention <Industrial Application Field> The present invention relates to an abnormality detection circuit for an encoder signal coupled to a motor and output in accordance with the rotation angle of the motor. The present invention relates to a circuit that detects an abnormality in an encoder signal such as noise mixing when outputting phase, B-phase, and Z-phase signals.

<Prior Art> Encoders are often connected to the rotating shaft of a motor, for example, and used to accurately detect the rotation angle of the motor.
There are optical types, magnetic types, etc., which have different phases depending on the rotation angle.
It is configured to output two types of phase signals and a Z signal indicating the zero point position. These signals are all pulse signals, and if an abnormality occurs in the encoder signal, such as when pulse noise is mixed in, the rotation angle may be incorrect. Therefore, conventionally, this type of encoder is provided with a circuit for detecting an abnormality in its output signal.

FIG. 3 is a block diagram showing an example of a conventional encoder signal abnormality detection circuit.

This circuit uses encoder signal buffer BA to
A phase as shown in Fig. 4, which are in opposite phase relation to each other,
The A-phase differential signals are applied to the exclusive OR EXOR, and the error signal ERR is output from there.

<Problems to be Solved by the Invention> The conventional abnormality detection circuit having such a configuration can be applied when the encoder signal is a differential output, but cannot be applied to an oven collector output type encoder. There wasn't.

The present invention has been made in view of these points, and
It is an object of the present invention to provide a signal abnormality detection circuit that does not utilize the differential output of an encoder and is therefore applicable to an oven collector output type encoder.

Means for Solving the Problems> The present invention to solve the above problems includes: an encoder pulse setting device for setting the rated value of encoder output pulses per rotation; and A-phase signals from the encoder having mutually different phases.

An encoder pulse that inputs a B-phase signal and a Z-phase signal output every rotation, and outputs encoder pulse count data from the time the Z-phase signal is applied until the next two-phase signal is applied. a generation circuit; an absolute value output circuit that takes the absolute value of output data from the encoder pulse generation circuit; and data from the encoder pulse setter and data from the encoder pulse generation circuit provided via the absolute value circuit. A first comparator that compares O and outputs an OK signal when both data are equal, and a first comparator that compares O and the data from the encoder pulse generation circuit and outputs an OK signal when the data is 0.
a second comparator outputting a K times signal; a first comparator; It is configured to include an OR circuit which receives the OK multiplied signal from each of the second comparators and outputs an error signal if the OK multiplied signal is not output from either side.

<Function> An up/down counter is provided in the encoder pulse generation circuit, and counts the encoder pulses from the time a Z-phase signal is applied until the next Z-phase signal is applied, and its value If it is normal, it will be 0 or the number of encoder pulses for 1 revolution.

Therefore, the first. The second comparator detects whether the encoder signal is normal or abnormal by determining whether the count value is the rated number of encoder pulses or 0.

<Example> Embodiments of the present invention will be described in detail below with reference to the drawings.

FIG. 1 is a block diagram showing an embodiment of the present invention. In the figure, 1 is an encoder pulse setting device that sets the rated encoder pulse number NS per rotation of the applied encoder, 2 is an encoder pulse generation circuit that inputs A-phase, B-phase signals, and Z-phase signals from the encoder. It has an up/down counter inside, and obtains the motor rotation direction and encoder pulses from the A-phase and B-phase signals, counts these encoder pulses with the up/down counter, and latches and clears them with the pulses from the Z-phase signal. It is composed of Therefore, from here, the encoder pulse count data N from the time the Z-phase signal is applied until the next Z-phase signal is applied is output.
If the value is normal, it will be 0 or the number of encoder pulses for one revolution.

3 is an absolute value output circuit which takes the absolute value of data N from the encoder pulse generation circuit 2.

In this absolute value circuit, since data N can be both positive and negative depending on the rotation direction, for example, in the case of negative data,
Provided for converting into positive data. 4 is a first comparator that compares the data NS from the encoder pulse setter 1 with the data N from the encoder pulse generation circuit 2 provided via the absolute value circuit 3;
When S and N are equal, an OK times signal is output. A second comparator 5 compares O with data N from the encoder pulse generation circuit 2, and outputs an OK times signal when data N is 0. 6 is an OR circuit; The OK multiplied signal from each of the second comparators 4 and 5 is input, and if the OK multiplied signal is not output from either side, it is configured to output an error signal ERR.

The operation of the circuit configured in this way will be explained as follows.

FIG. 2 is a time chart showing the operation.

(a) shows the input phase signal of the encoder output, and (b) shows the waveform of the B-phase signal. Here, the A-phase signal and the B-phase signal are 90 degrees out of phase with each other, and whether the phase advances by 90 degrees or not. As shown in (d), it is possible to judge whether the rotation direction is forward or reverse depending on whether the rotation direction is delayed or delayed. (c) is a Z-phase signal, and a pulse signal is output as shown every time the motor rotates once.

After the Z-phase signal shown in (C) is output, the encoder pulse generation circuit 2 uses an up-down counter to count up the A-phase signal pulse shown in (a) by capturing the rising edge of the pulse during the normal rotation period. , and the reversal period is counted down.

As a result, the count value N of the up/down counter is (
The pulse waveforms change sequentially as shown in the numbers beside each pulse waveform in a). This count value N is calculated at the time when the Z-phase signal is applied (
(at the falling edge of the pulse), it is output to the first comparator 4 and the second comparator 5 via the absolute value output circuit 3.

Here, if there is no abnormality in the A-phase and B-phase signals from the encoder, the count value N output from the up-down counter every time the Z-phase signal is given is 1 of the encoder.
The value is NS, which is the rated number of pulses output per rotation, or 0.

The first comparator 4 determines whether the count value N is equal to the rated pulse number NS, and outputs an OK times signal if the count value N is equal to the rated pulse number NS. Further, the second comparator 5 determines whether the count value N is equal to 0, and if it is equal, outputs an OK times signal. The OR circuit 6 logically ORs these OK times signals, and outputs an ERR signal when the OK times signal is not output from any of the comparators, that is, when the count value N is less than the rated pulse number NS or O.

With such an operation, it is possible to detect whether the encoder signal is normal or abnormal every time the Z signal is output.

<Effects of the Invention> As explained in detail above, according to the present invention, since the differential output of the encoder is not used, it is possible to realize an encoder signal abnormality detection circuit that is applicable to open collector output type encoders. .

[Brief explanation of the drawing]

FIG. 1 shows an embodiment of the present invention (R block diagram, FIG. 2 is a time chart for explaining its operation, and FIG. 3 is a time chart for explaining its operation.
The figure is a block diagram showing an example of a conventional encoder signal abnormality detection circuit, and FIG. 4 is a waveform diagram showing its operation. 1... Encoder pulse setter 2... Encoder pulse generation circuit 3... Absolute value output circuit 4... First comparator 5.
...Second comparator 6...OR circuit patent applicant Yokogawa Electric Corporation

Claims (1)

[Claims] An encoder pulse setting device that sets the rated value of encoder output pulses per rotation, A-phase and B-phase signals having mutually different phases from the encoder, and a Z-phase signal outputted every rotation. an encoder pulse generation circuit that inputs a signal and outputs encoder pulse count data from the time a Z-phase signal is applied until the next Z-phase signal is applied, and the output data from this encoder pulse generation circuit. An absolute value output circuit that takes an absolute value compares the data from the encoder pulse setter with the data from the encoder pulse generation circuit provided via the absolute value circuit, and outputs an OK signal when both data are equal. A first comparator compares 0 with data from the encoder pulse generation circuit, and when the data is 0, O
A second comparator that outputs the K signal, and an OR circuit that inputs the OK signal from each of the first and second comparators and outputs an error signal if the OK signal is not output from either side. Equipped with an encoder signal abnormality detection circuit.