JPH0440850B2 - - Google Patents

Info

Publication number
JPH0440850B2
JPH0440850B2 JP60043142A JP4314285A JPH0440850B2 JP H0440850 B2 JPH0440850 B2 JP H0440850B2 JP 60043142 A JP60043142 A JP 60043142A JP 4314285 A JP4314285 A JP 4314285A JP H0440850 B2 JPH0440850 B2 JP H0440850B2
Authority
JP
Japan
Prior art keywords
capacitor
capacitors
electrode layer
electrode layers
circuits
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
JP60043142A
Other languages
Japanese (ja)
Other versions
JPS6127617A (en
Inventor
Kyoshi Sawairi
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Holdings Corp
Original Assignee
Matsushita Electric Industrial Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Matsushita Electric Industrial Co Ltd filed Critical Matsushita Electric Industrial Co Ltd
Priority to JP4314285A priority Critical patent/JPS6127617A/en
Publication of JPS6127617A publication Critical patent/JPS6127617A/en
Publication of JPH0440850B2 publication Critical patent/JPH0440850B2/ja
Granted legal-status Critical Current

Links

Landscapes

  • Parts Printed On Printed Circuit Boards (AREA)
  • Fixed Capacitors And Capacitor Manufacturing Machines (AREA)

Description

【発明の詳細な説明】 産業上の利用分野 本発明は複数のコンデンサを一体に内蔵する積
層コンデンサに関するものである。
DETAILED DESCRIPTION OF THE INVENTION Field of Industrial Application The present invention relates to a multilayer capacitor that integrally incorporates a plurality of capacitors.

従来の技術 例えばスーパーヘテロダイン受信機のアンテナ
同調回路と局部発振回路との間で互いに結合が起
こると、その周波数が近い場合には、引込み現象
が起こつたり発振電圧がアンテナ回路を介して不
要輻射として外部に輻射され妨害となつたりする
不都合があつた。このため従来は上記のような回
路同志は物理的な空間を隔てて配置したり、一方
の回路をシールド板で覆つたりした互いの結合を
避けていたが、このような構成では小型化に限度
があつた。一方回路の小型化の手段として、複合
部品を用いることが一般に行なわれている。例え
ば積層コンデンサなどでは、複数個の同程度の容
量値のコンデンサであれば、極板面積がほぼ同じ
であるから、一体構造で作製することが可能であ
る。
Conventional technology For example, when coupling occurs between the antenna tuning circuit and the local oscillation circuit of a superheterodyne receiver, if their frequencies are close, a pull-in phenomenon may occur or the oscillation voltage may be radiated through the antenna circuit. There was a problem that the light was radiated to the outside and caused interference. For this reason, in the past, circuits such as those described above were placed apart from each other physically, or one circuit was covered with a shield plate to avoid coupling with each other, but such a configuration made it difficult to downsize. There was a limit. On the other hand, as a means of downsizing circuits, it is common practice to use composite components. For example, in the case of a multilayer capacitor, if a plurality of capacitors have the same capacitance value, the plate areas are approximately the same, so it is possible to manufacture them as an integral structure.

発明が解決しようとする問題点 しかしながら、上記のような回路にそれぞれ接
続されるコンデンサを一体化すれば、必ず回路間
結合が起こり、小型化のために複合された積層コ
ンデンサを用いることができなかつた。
Problems to be Solved by the Invention However, if the capacitors connected to each of the above circuits are integrated, coupling between the circuits will inevitably occur, making it impossible to use composite multilayer capacitors for miniaturization. Ta.

本発明は、互いのコンデンサ間の結合容量を非
常に小さくして各コンデンサが接続された異なる
回路間の結合を抑えることを目的とするものであ
る。
An object of the present invention is to minimize coupling capacitance between capacitors to suppress coupling between different circuits to which each capacitor is connected.

問題点を解決するための手段 上記の問題を解決するため、本発明の積層コン
デンサは、複数のコンデンサを一体に内蔵する積
層コンデンサにおいて、一方のコンデンサのホツ
ト側の電極層と他方のコンデンサのアース側の電
極層とを同一面上に印刷形成したことを特徴とす
るものである。
Means for Solving the Problems In order to solve the above problems, the multilayer capacitor of the present invention has a multilayer capacitor that integrates a plurality of capacitors, and the electrode layer on the hot side of one capacitor and the ground of the other capacitor. It is characterized in that the side electrode layer and the electrode layer are printed on the same surface.

作 用 本発明は、上記した構成により、互いにシール
ド効果を有し相互間の結合容量を小さくした積層
コンデンサを実現することができるものである。
Effects According to the present invention, with the above-described configuration, it is possible to realize a multilayer capacitor that has a mutual shielding effect and reduces mutual coupling capacitance.

実施例 以下本発明の実施例を図面にもとづいて説明す
る。第1図は本実施例の回路図であり、コンデン
サC1,C2は端子A,Dがホツト側に、端子B,
Eがアース側に接続されるものである。第2図は
本実施例の正面図、第3図は第2図M−M′線に
よる断面上面図である。1は誘電体層、2x,3
xは電極層、4は誘電体層、2y,3yは電極
層、5は誘電体層であり、順次印刷により形成す
る。上記各電極層は一部を端面にまで導出してあ
り、この部分に導電体を設けることにより端子を
形成する。そして電極層2x,2yによりコンデ
ンサC1を、電極層3x,3yによりコンデンサ
C2が形成される。
Embodiments Hereinafter, embodiments of the present invention will be described based on the drawings. Figure 1 is a circuit diagram of this embodiment, in which capacitors C 1 and C 2 have terminals A and D on the hot side, and terminals B and C 2 on the hot side.
E is connected to the ground side. FIG. 2 is a front view of this embodiment, and FIG. 3 is a cross-sectional top view taken along line MM' in FIG. 1 is a dielectric layer, 2x, 3
x is an electrode layer, 4 is a dielectric layer, 2y and 3y are electrode layers, and 5 is a dielectric layer, which are sequentially formed by printing. A portion of each of the electrode layers is led out to the end face, and a terminal is formed by providing a conductor in this portion. The electrode layers 2x and 2y form a capacitor C1 , and the electrode layers 3x and 3y form a capacitor C1.
C 2 is formed.

上記実施例では、同一面にある電極層2x,3
xにはそれぞれ端子A,Eが接続される。ここで
第1図に示すように端子Aはホツト側に接続さ
れ、端子Eはアース側に接続されるものである。
また他の一面にある電極層2y,3yはそれぞれ
アース接続の端子B、ホツト接続の端子Dに接続
されている。
In the above embodiment, the electrode layers 2x, 3 on the same surface
Terminals A and E are connected to x, respectively. Here, as shown in FIG. 1, terminal A is connected to the hot side, and terminal E is connected to the ground side.
Further, the electrode layers 2y and 3y on the other side are connected to a ground connection terminal B and a hot connection terminal D, respectively.

上記の構成によれば、たとえ大きな誘電体材料
を用いても、アース側に接続された電極層2y,
3xが互いにシールド効果を有するために、電極
層2x,3y(極子A,D)間の結合容量は極め
て小さく、端子A,Dがそれぞれ接続される別系
統の回路間の結合を抑えることが可能となる。
According to the above configuration, even if a large dielectric material is used, the electrode layer 2y connected to the ground side,
Since 3x have a mutual shielding effect, the coupling capacitance between electrode layers 2x and 3y (poles A and D) is extremely small, making it possible to suppress coupling between circuits of different systems to which terminals A and D are respectively connected. becomes.

なお図示のように、アース側に接続される電極
層2y,3xの形状を、他の電極層2x,3yよ
りも大となすことにより、端子A,D間の結合容
量をより小さくできるとともに、印刷工程での位
置精度の誤差を吸収し容量のばらつきを小さくす
ることができる。
As shown in the figure, by making the shape of the electrode layers 2y and 3x connected to the ground side larger than the other electrode layers 2x and 3y, the coupling capacitance between the terminals A and D can be further reduced. It is possible to absorb errors in positional accuracy during the printing process and reduce variations in capacity.

発明の効果 以上のように本発明の積層コンデンサによれ
ば、一方のコンデンサのホツト側の電極層と他方
のコンデンサのアース側の電極層とを同一面上に
印刷形成したことにより、互いのコンデンサ間の
結合容量を小さくして、各コンデンサが接続され
た異なる回路間の結合を抑えることが可能とな
り、すなわちこれらの回路を小型化する上で大き
く寄与するものである。
Effects of the Invention As described above, according to the multilayer capacitor of the present invention, the hot-side electrode layer of one capacitor and the ground-side electrode layer of the other capacitor are printed on the same surface. By reducing the coupling capacitance between the capacitors, it is possible to suppress coupling between different circuits to which each capacitor is connected, which greatly contributes to miniaturization of these circuits.

【図面の簡単な説明】[Brief explanation of drawings]

第1図は本発明の積層コンデンサの一実施例の
回路図、第2図は本実施例の正面図、第3図は第
2図M−M′線による断面上面図である。 1……誘電体層、2x,2y,3x,3y……
電極層、4,5……誘電体層、A,B,C,D…
…端子。
FIG. 1 is a circuit diagram of an embodiment of a multilayer capacitor according to the present invention, FIG. 2 is a front view of this embodiment, and FIG. 3 is a cross-sectional top view taken along line M-M' in FIG. 1...Dielectric layer, 2x, 2y, 3x, 3y...
Electrode layer, 4, 5...Dielectric layer, A, B, C, D...
...Terminal.

Claims (1)

【特許請求の範囲】[Claims] 1 複数のコンデンサを一体に内蔵する積層コン
デンサにおいて、一方のコンデンサのホツト側の
電極層と他方のコンデンサのアース側の電極層と
を同一面上に印刷形成したことを特徴とする積層
コンデンサ。
1. A multilayer capacitor that incorporates a plurality of capacitors, characterized in that a hot-side electrode layer of one capacitor and a ground-side electrode layer of the other capacitor are printed on the same surface.
JP4314285A 1985-03-05 1985-03-05 Laminated capacitor Granted JPS6127617A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP4314285A JPS6127617A (en) 1985-03-05 1985-03-05 Laminated capacitor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP4314285A JPS6127617A (en) 1985-03-05 1985-03-05 Laminated capacitor

Publications (2)

Publication Number Publication Date
JPS6127617A JPS6127617A (en) 1986-02-07
JPH0440850B2 true JPH0440850B2 (en) 1992-07-06

Family

ID=12655583

Family Applications (1)

Application Number Title Priority Date Filing Date
JP4314285A Granted JPS6127617A (en) 1985-03-05 1985-03-05 Laminated capacitor

Country Status (1)

Country Link
JP (1) JPS6127617A (en)

Also Published As

Publication number Publication date
JPS6127617A (en) 1986-02-07

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