JPH0440789A - Picture reproducing device - Google Patents

Abstract

PURPOSE:To prevent random noise from being generated on a monitor with a simple constitution by making data given to an auxiliary memory transferred to a memory by a transfer means. CONSTITUTION:A memory 4 to store picture information given in a device to reproduce a picture signal given specially, auxiliary memories 5 and 6 to store data to rewrite the contents of the memory 4 and transfer means 9 and 10 to transfer the data stored in the auxiliary memories 5 and 6 to the memory 4 are provided. However, the picture memories 4 to 6 are the multiport random access memories constituted so as to able to execute the writing of picture data to a random address from a decoding circuit 3 side and to able to read at a frame rate effectively asynchronously with it. Thus, random noise can be prevented from being generated on a monitor.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an image reproducing device, and particularly to a device for reproducing a given image signal.

[Conventional technology]

2. Description of the Related Art Conventionally, various devices are known for receiving still images and displaying them on a monitor, such as still image video telephones, teletext receiving devices, and the like.

[Problem to be solved by the invention]

Such a device has an image memory in which image data received over a relatively long period of time is stored and read out repeatedly from the image memory at a high speed, for example, at a speed compatible with standard television standards. It is configured to play still images on the monitor.

However, in such a device, if the received data has not yet been written to the image memory at the time of starting reception, random noise is generated in the memory, and this noise is displayed on the monitor, resulting in an unsightly image. This problem is not limited to the above-mentioned reception start, but also occurs when there are multiple image reception transmission paths and the transmission paths are switched.

SUMMARY OF THE INVENTION An object of the present invention is to provide an image reproducing device that can solve this problem and quickly display an appropriate image.

[Means to solve the problem]

In order to achieve the above-mentioned object, the first invention of the present application provides a memory for storing given image information, an auxiliary memory for storing data for rewriting the contents of the memory, and a memory for storing data stored in the auxiliary memory. and a transfer means for transferring the data to.

Moreover, in order to achieve the above-mentioned object, the second invention of the present application has the following features:
The apparatus includes means for selecting image information of a plurality of channels, an image memory for writing the image information, and means for setting the image memory to a predetermined value in accordance with the selection by the selection means.

[Effect]

According to the first aspect of the above configuration, data given to the auxiliary memory is transferred to the memory by the transfer means.

According to the second invention, the image memory is set to a predetermined value in accordance with the selection by the selection means.

Embodiment] The present invention will be described in detail below with reference to the drawings. FIG. 1 shows a configuration block diagram of the present invention. 1 is an antenna for receiving radio waves transmitted from, for example, a broadcasting satellite; 20 is a diagram showing the entire image receiving and reproducing device according to the present invention; 21 is a scanning line; an HDTV color monitor device that displays 1,125 images; be. In the image receiving and reproducing apparatus according to the present embodiment shown in 20, 2 is a tuner that converts the radio waves received by the antenna 1 into image digital compressed data and device control data, and 3 is image digital compressed data band-compressed by, for example, the DPCM method. This is a decoding circuit that restores a still image to the original image data, and in this embodiment, it takes several seconds to about 10 seconds to receive one still image. 4 is an image frame memory FM-A that stores one frame of image data restored by the decoding circuit 3; 5 is an image frame memory FM that stores one frame of image data restored by the decoding circuit 3; -B, 6 is an image frame memory FM-C that stores one frame of image data restored by the decoding circuit 3; These image frame memories are multi-port random access memories configured so that image data can be written to random addresses from the decoding circuit 3 side and read out completely asynchronously at the effective frame rate. 7 is a register REGA for temporarily storing a single color that will be a background color, and 8 is a register REG-B for temporarily storing another single color that will be a background color, and each of these registers has a simple D flip-flop. There are only a few bits for the luminance signal and color difference signal. 9 is the frame rate, that is, the digital video bus that can effectively transmit one image in 1730 seconds.
BA, 10 uses another digital video bus VB-B that can effectively transmit one image at a frame rate of 1/30 seconds, and 11 uses digital video buses VB-A and VB-B with a frame rate of 9.1o. calculate the image data,
For example, an image effect circuit performs image effect processing such as combining both image data, and 12 is a D/A converter that converts the image data read from the image effect circuit 11 into analog. 1
3 is the frame memory of 4.5.6 F) l-A, -B.

This is a device control circuit that controls writing and reading of -C and writes single color data, for example, which becomes a background color, to the registers REG-A and REG-B of 7.8.

For normal images, 4.5.6 image frame memory FM-
The write image data for A and FM-BSFM-C is generated by the decoding circuit 3, and the device control unit 13 allows the write command received from the tuner 2 to be written into which frame memory. In addition, the device control unit 13 temporally manages the read command received from the tuner 2 and controls which frame memory is output to which video bus 9.10.
It issues various image effect execution commands to the image effect circuit.

In the case of a single color as the background color, the control unit 13 receives the single color data as the background color received from the tuner 2 or the data for creating the single color data as the background color, and registers REG in 7.8. Write the single color data to either -A, REG-B, or both.

Furthermore, the single color image data written to the above registers REG-A and REG-13 can be transferred to any image frame memory FM-A or FM- at the frame rate via any of the video buses VB-A and VB-B in 9.10. It is possible to write to the entire area of BSFM-C.

FIG. 2 shows an example of the application of the image effect according to the present invention. (a) shows that the background color black is written in the register REG-A (7) in FIG. 1 by the device control circuit (13), and the data is This is an image when output to video bus VB-A. The normal picture written in advance from the decoding circuit 3 to the picture frame memory FM-A is output to the video bus VB-B. The device control circuit and image effect circuit are temporally videonox VB-A.
, VB-B are selected and sent to the D/A converter 12, it is possible to obtain an image in which the image in the image frame memory FM-A is framed with a black background color.

(b) is an image obtained by writing the background color blue to the star REG-B (marked at 8) in FIG. The normal picture written in advance from the decoding circuit 3 to the image frame memory FM-C1 is output to the video bus VB-A. The device control circuit and image effect circuit are temporally connected to the video bus ~7B.
By switching and selecting -BXVB-B and sending it to the D/A converter, the image in the image frame memory FM-C changes from the screen cloth to the left to the background color blue over time. Obtainable.

(c) writes red, the background color, to register REG-H, number 8 in FIG.
Using frame rate and image frame memory FM-
This is an image when writing in B. Thereafter, a normal image is written into a part of the image frame memory FMB from a decoding circuit shown as 3. Then, the image frame memory FM-B is output to the video bus VB-B, and the device control circuit and the image effect circuit select only the video bus VB-B.
/A converter, the image frame memory FM
It is possible to obtain an image in which the -H image is framed by the red background color. During this time, the video bus VB-A is not used at all, so other images can be exchanged.

(d) writes the background color red into register REG-A, number 7 in FIG. 1, by device control circuit number 13, outputs the data to video bus VB-A, and registers R
The background color blue is written to EG-B by 13 device control circuits, the data is output to video bus VB-B, and these video buses are used to write image frame memory FM-A.
, FM-B at the same frame rate, and then the background color yellow is written to the register REG-A of 7 by the device control circuit 13, and the FM-C is written using the video bus VB-A. Write across the entire area at the frame rate. By doing so, it is possible to rewrite the contents of the three image frame memories over the entire area to any background color in two frame times.

Next, the operation of the embodiment having the configuration described above will be explained using the operation flowchart shown in the third figure.

First, start from the moment the device is powered on.1)
In FIG. 1, tuner 2 waits until it receives a write command to either the image frame memory or the register (2). This write command is received by the tuner 2. Next, when a write command is received for either one, it is determined whether the writing destination is the image frame memory or the register3).If it is a register, it is determined whether the write destination is REG-A or REG-B 4) If the instruction is to write to register REGA, the device control circuit 13 in FIG. On the other hand, in the judgment in (4) above, if it is a write command to register REG-B, the data is written from the device control circuit side of 13 in FIG. 1 to 8 in the same figure. The background data is written to the register REG-B (6).

In addition, in the judgment in (3) above, if the write destination is the image frame memory, it is necessary to judge which image frame memory to write to (7), and the image frame memory FM-
If it is a write command to A, 3 in Figure 1.
From the decoding circuit side of 4 in the same figure, image frame memory FM
If the image data is written to A (8) and the write command is to the image frame memory F M -H, then the image frame 5 from the decoding circuit side of 3 in FIG. When image data is written to the memory FM-B (9) and the write command is to the image frame memory FM-C, the image number 6 in the figure is transferred from the decoding circuit 3 in FIG. Image data is written to frame memory FM-C (10).

Next, it is determined again whether a write command was received (11), and if it was a write command, the process returns to the determination in (3) above. If a write command is not input, then it is determined whether the given command is a data transfer command from the register to the image frame memory (12), and if it is a transfer command, the transfer source of that register is REG-
Please judge whether it is A or REG-B13), R
If it is EG-A, REG-A at 7 in FIG. 1 is output to digital video bus VB-B at 9 in the same figure (
14). On the other hand, in the judgment in (13) above, RFC,
If it is B, change REG-B of 8 in Fig. 1 to
Output to digital video bus VB-H of 9 (15)
. Next, it is necessary to determine where the image frame memory is to be written (16), and the image frame memory FM-A is
In this case, the image frame memory FM of 4 in FIG.
-A inputs image data from the digital video bus VBB at 9 in the same figure (17), and in the judgment in (16) above, if it is the image frame memory FM-B,
Image frame memory FM-B at 5 in FIG. C, the image frame memory FIVI-C at 6 in FIG. 1 receives image data from the digital video bus VB-B at 9 in the figure (19).

In addition, in the judgment in (12) above, if it is not a transfer instruction, then it is judged whether it is a read instruction or not.
), the system waits until a read command () is received. When the read command is received, the device control circuit 13 in FIG.
21).

In order to generate various special effects as described above in FIG. 2, the image effect circuit 11 in this embodiment issues image data read commands to gate circuits such as AND gates and OR gates and FM-A-C. It has a memory control circuit (not shown).

Next, the operation when the power is turned on in the embodiment shown in FIG. 1 will be explained using FIG. 4.

FIG. 4 is a flowchart showing the operation of the embodiment of FIG. 1 when the power is turned on.

When the power is turned on (40), interrupts are disabled for the first time (41), and blue data is written in the register REG-A in FIG. 1 (42).

Next, the blue data written in register REG-A is transferred to frame memories FM-A, B, C, 4, 5, 6,
Clear all memories to blue data color (43).

When this clearing is completed, the prohibition of interrupts is canceled and interrupts are accepted, as shown in Figure 3 (1) above.
The flow branches to perform the operations described above.

While the flowchart in FIG. 3 is being executed, interrupt acceptance is in the enabled state, and when the selection of the input source is changed, that is, for example, when the receiving channel of the tuner 2 is changed, an interrupt is generated (45). (42), (4
Perform the same operation as (46) and (47) in Figure 3 (2).
) the flow returns to (48).

Some of the application examples of image effects according to this embodiment have been shown above, but in these examples, the image frame memory, register, and video bus can be freely selected, and the image frame memory, register, and video bus are not limited to the above examples. It goes without saying that the numbers of memories, registers, and video buses are not limited to the above example. Further, by preparing a plurality of stages of the registers in the above embodiment, a complex fixed pattern can be outputted by increasing the number of stages from a simple fixed pattern. Although this embodiment has been described with reference to still images, the technology of the present invention is not limited to still images if higher capacity transmission media, higher speed decoding circuits, and higher speed image frame memories are realized. No, 1/30
The present invention can also be applied to an image receiving and reproducing device that handles moving images whose images are updated every second.

As can be easily understood from the above explanation, according to this embodiment, it is possible to write a simple background color of blue or a simple fixed pattern into the register from the device control circuit without passing it through the image decoding circuit. By outputting the data through the image processing system, it has become possible to provide an image receiving and reproducing apparatus that requires only a short transmission time.

〔Effect of the invention〕

According to the present invention described above, it is possible to prevent random noise from occurring on the monitor with a simple configuration.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of the configuration of the embodiment of the present invention, FIG. 2 is a diagram showing an application example of the embodiment of the present invention, and FIGS. 3 and 4 explain the operation of the embodiment of FIG. 1. Flowchart for 2... Tuner 3... Decoder 4.5.6... Frame memory 13... Control section 5' M-8 Figure 4 Go to Figure 3 (1)

Claims (2)

[Claims] (1) A memory for storing given image information; an auxiliary memory for storing data for rewriting the contents of the memory; and a transfer means for transferring the data stored in the auxiliary memory to the memory. Image playback device. (2) An image reproducing device comprising: means for selecting image information of a plurality of channels; an image memory for writing the image information; and means for setting the image memory to a predetermined value according to the selection by the selection means. .