JP4070480B2 - MEMORY CONTROL METHOD AND DEVICE, AND DISPLAY DEVICE USING THEM - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to an image synthesizer that synthesizes background image data and foreground image data, and a video display device including such an image synthesizer .
[0002]
[Prior art]
The progress of digital technology is also remarkable in the broadcasting world. For example, digital television receivers (hereinafter also simply referred to as digital television) are becoming widespread as products that affect the lives of ordinary people. The digital television has a built-in CPU (Central Processing Unit) and performs various data processing including image processing.
[0003]
As an example of such processing, there is a superposition of images, for example, a normal video is displayed on the background, and data broadcast information is displayed thereon. For this purpose, the CPU temporarily converts the text data corresponding to the characters into image data, and the image data is overlapped by α blending or other techniques in an OSD (on-screen display) processing unit or the like and rendered. Due to the processing by the CPU, a very diverse video expression is realized.
[0004]
[Problems to be solved by the invention]
When processing image data, the data is often temporarily stored in a memory such as a frame buffer (hereinafter simply referred to as a memory). The memory entry bit width (which is also simply referred to as the memory bus width) is increased to some extent for speeding up the drawing. For example, even when data is written in units of one byte for drawing, the memory The bus width is 4 bytes. This bus width is realized by juxtaposing one to several memory elements.
[0005]
However, due to the wide bus width, if some of the bytes need to be rewritten, for example, if the “Read Modify Write” mode of a known memory is used, the byte data that does not need to be rewritten is also read once. Need to be written back as it is. Therefore, even if it is intended to increase the bus width and cope with high speed, two cycles of a read cycle and a write cycle are required, which may be contrary to the original purpose.
[0006]
The present invention has been made in view of these problems, and an object of the present invention is to provide an image synthesizer that can synthesize background image data and foreground image data at high speed, and a video display including such an image synthesizer. Relates to the device .
[0007]
[Means for Solving the Problems]
An aspect of the present invention is an image composition device that overwrites background image data with foreground image data and synthesizes these images, and n times the unit data width of writing (n is an integer of 2 or more). A memory for storing input image data, and an instruction register for holding a data value for instructing whether or not overwriting of foreground image data is permitted with respect to the memory storing background image data. , the data of each pixel of the foreground picture, and inputs the data held by the instruction register, and n pieces of comparators for performing an output based on these comparison results, with a, for each pixel of the foreground and background image data data width equal to the unit data width of the write, the data bus width, a n times the data width of each pixel of the foreground and background image data, before the output of the n comparators each And forming a logical data overwrite permission for each unit data width of the memory.
[0008]
Another aspect of the present invention is a video display device that displays a composite image obtained by combining foreground image data and background image data, and data that is n times the write unit data width (n is an integer of 2 or more). A memory having a bus width and storing input image data; an instruction register holding a data value for instructing whether or not to overwrite the foreground image data to the memory storing the background image data; Data for each pixel of the image and data held in the instruction register are input, and n comparators for outputting based on the comparison result and a display unit for displaying the output from the memory are provided. and the data width of each pixel of the background image data is equal to the unit data width of the write, the data bus width, a n times the data width of each pixel of the foreground and background image data, these n pieces The output of the comparator and forming the logic of data overwrite permission for each unit data width of said memory, respectively.
[0010]
An example of “a data value indicating whether or not data writing is permitted” is a data value that should be permitted to be written. Another example is a data value that should be prohibited from data writing. As an example of “forming data writing permission / inhibition logic”, there is “a signal itself that permits or prohibits data writing, or an input to a circuit that generates the signal”. Therefore, this apparatus permits or prohibits writing to the memory according to the data value, or generates a factor for permitting or prohibiting. Even in this apparatus, two cycles such as read-modify-write are unnecessary.
[0011]
The memory control device further includes a logic switching circuit having a mode in which the output of the n comparators is output in the logic as it is and a mode in which the output is inverted and output, and the output of the circuit is the write mask signal as the memory. May be entered.
[0013]
It should be noted that any combination of the above-described constituent elements and a conversion of the expression of the present invention between a method, an apparatus, a system, a recording medium, a computer program, etc. are also effective as an aspect of the present invention.
[0014]
DETAILED DESCRIPTION OF THE INVENTION
FIGS. 1 and 2 show the same logic for generating a composite image 204 by superimposing the background image 200 and the foreground image 202. Although the foreground image 202 is originally text data, it has already been converted into image data here. Further, the foreground image 202 does not necessarily come to the foreground depending on the processing, but is referred to as such for convenience.
[0015]
In FIG. 1, characters of the foreground image 202 are superimposed on the background image 200. In the composite image 204, only a portion of the foreground image 202 with the characters is the image of the foreground image 202, and the other portions are the background image. There are 200 images. This is a method used when displaying information broadcast on the background moving image in a telop or other form. This is hereinafter referred to as “ON writing”.
[0016]
In contrast, in FIG. 2, in the composite image 204, only the marked portion of the foreground image 202 is the image of the background image 200, and the other portion is the image of the foreground image 202. This can be used for watermarking the background moving image only at the mark portion, and is hereinafter referred to as “OFF writing”.
[0017]
The present embodiment is based on the knowledge that in many cases, such characters and marks are monochromatic or generally expressed with a very small number of colors compared to a background moving image. For example, in the ON writing shown in FIG. Then, in order to generate the composite image 204, only the pixel that is “black” in the foreground image 202 among the pixels of the background image 200 may be rewritten to that color. Therefore, the outline is the following memory control.
[0018]
1) The background image 200 is stored in the memory.
2) While scanning the foreground image 202, the pixel values are sequentially overwritten on the background image 200. However, at this time, the “write mask signal” is asserted, that is, output at the write timing of the pixels that are found to be not “black” among the pixels of the foreground image 202, and the memory contents are write-protected.
[0019]
By this process, only the pixels that were black in the foreground image 202 are overwritten on the background image 200, and a composite image 204 is obtained. In the case of OFF writing, the logic of the “write mask signal” may be inverted.
[0020]
FIG. 3 is a circuit diagram of the memory control device 100 that realizes the above control. In the figure, the write data is 32 bits D0-31, which are expressed as B1, B2, B3, B4 in order from the lower byte for the sake of brevity and convenience. The memory 10 has a data bus width of 4 bytes and a write unit data width of 1 byte. The control signal and address signal are omitted. Memory 10 has write mask inputs MSK1-4, which protect writing of bytes B1-4, respectively. In this figure, all the signals are determined to be high and active, but of course not limited thereto.
[0021]
The memory control device 100 has an instruction register 12 related to an instruction of whether or not data writing is permitted. A desired value is set in the instruction register 12 from the CPU. The output of the instruction register 12, that is, the set value S is commonly input to the second ports of the first comparator 22, the second comparator 24, the third comparator 26, and the fourth comparator 28. These comparators compare the input data value of the first port with the input data value of the second port, and when they match, CPOUT1 to CPOUT4 are asserted, respectively. Bytes B1 to B4 of write data are input to the first ports of the first comparator 22, the second comparator 24, the third comparator 26, and the fourth comparator 28, respectively.
[0022]
The outputs CPOUT1 to CPOUT4 of the comparators are connected to one input of a first EXOR 32, a second EXOR 34, a third EXOR 36, and a fourth EXOR 38 (EXOR indicates an exclusive OR gate), respectively. An ON signal 16 is connected to the other input of these EXORs. The mode register 14 sets the ON signal 16 to high or low. When “ON write” is designated by the CPU for the mode register 14, the ON signal 16 becomes high, and when “OFF write” is designated, it becomes low. The outputs of the first EXOR 32, the second EXOR 34, the third EXOR 36, and the fourth EXOR 38 become the write mask signals MSK1 to MSK4 of the memory 10, respectively. The first EXOR 32, the second EXOR 34, the third EXOR 36, the fourth EXOR 38, and the mode register 14 function as a logic switching circuit for the write mask signal.
[0023]
The operation of the above configuration will be described. The image data of the background image 200 is already stored in the memory 10. Foreground image 202 data is sequentially sent as write data D0-31. This data sequentially overwrites the memory 10, but if the write data is data other than “black” in units of bytes, the write mask signal becomes active for the bytes and writing is blocked. If the pixel value indicating “black” is “00h”, “00h” is written from the CPU to the instruction register 12 prior to data transfer. Similarly, “ON write” is designated in the mode register 14 by the CPU.
[0024]
Suppose now that the data of byte B1 is not “00h” and is not black. At this time, the output CPOUT1 of the first comparator 22 goes low. Since the ON signal 16 is high, the output MSK1 of the first EXOR 32 becomes high, writing of this byte is prevented, and the data of the background image 200 remains as it is. Conversely, if the data in byte B1 is “00h”, that is, black, the output CPOUT1 of the first comparator 22 goes high, and the write mask signal MSK1 that is the output of the first EXOR 32 goes low. Writing is permitted, and the data of the foreground image 202 is written into the memory. The same applies to the other bytes. By repeating this operation, only black pixels in the foreground image 202 data are written in the memory, and ON writing is realized.
[0025]
FIG. 4 shows the rewriting relationship between the write mask signals MSK1 to MSK4 and the bytes B1 to B4. In the figure, MSK1 = MSK4 = 1, MSK2 = MSK3 = 0, bytes B2 and B3 are updated, and bytes B1 and B4 hold the previous value. Since data comparison is performed in units of bytes, whether or not rewriting is permitted in units of bytes can be controlled as shown in this figure.
[0026]
FIG. 5 shows another form of the memory control device 100. Here, only the instruction register 12 and the first comparator 22 are illustrated, but the second comparator 24, the third comparator 26, and the fourth comparator 28 also have the same input as the first comparator 22 in the second port. is there. Of course, corresponding byte data is input to the first port.
[0027]
In this form, two sub-registers A12a and B12b are provided in the instruction register 12, and two values can be set by the CPU. For convenience, the values set in the sub-register A12a and the sub-register B12b are expressed as DA and DB (DA ≦ DB), respectively. Further, the value indicated by the byte B1 is denoted as X. Several specifications of the first comparator 22 are conceivable. For example, there are the following examples.
[0028]
1. CPOUT1 = 1 only when X = DA or X = DB
2. CPOUT1 = 1 only when DA ≦ X ≦ DB
That is, whether or not data writing is permitted may be specified by directly specifying a plurality of data values or by specifying a range. Of course, the number of sub-registers may be any number of three or more.
[0029]
FIG. 6 shows a configuration of a display device 300 using the memory control device 100 described above, more specifically, a television receiver. The broadcast wave is given to the tuner 304 via the antenna 302. The stream demodulated here is sent to the audio / image decoder 306. The audio / image decoder 306 decodes a packet corresponding to a desired channel in accordance with, for example, MPEG specifications, and outputs audio data to the audio processing unit 308 and image data to the image processing unit 310. The sound processing unit 308 performs predetermined processing on the sound data, and finally the sound is output to the speaker 330. The image processing unit 310 performs predetermined processing on the input image data, and stores the processed data in the memory 10. The memory 10 is provided with a memory control device 100.
[0030]
The CPU 320 centrally controls the above units. In the memory 10, necessary ON writing or OFF writing processing is performed by the cooperation of the speaker 330 and the memory control device 100, and the output of the memory 10 is output to the desired display unit 332 via the encoder 312 compliant with NTSC and others. .
[0031]
The present invention has been described based on the embodiments. This embodiment is an exemplification, and it will be understood by those skilled in the art that various modifications can be made to combinations of the respective constituent elements and processing processes, and such modifications are also within the scope of the present invention. is there. Here are some examples.
[0032]
The memory control device 100 may be wholly or arbitrarily built in one LSI. This LSI may be a so-called graphic controller.
[0033]
In the embodiment, the write mask input of the memory 10 is used to prohibit data writing. In the absence of this signal, for example, there is a method in which a CAS (Column Address Strobe) provided for each byte of the memory 10 and other signals for determining the write operation are negated, that is, output inactive. Since the CAS signal is generally low active, the output signal of the first EXOR 32 and the OR signal of the CAS signal may be given to the memory 10 as a new CAS signal.
[0034]
In the embodiment, the display device 300 is illustrated as an application of the memory control device 100. However, there are naturally other uses. For example, the present invention can be applied to a PC (personal computer) or any other computer, and can be applied to any digital video equipment.
[0035]
【The invention's effect】
According to the present invention, memory control for rewriting only a necessary portion at high speed and its application device are realized. In addition, necessary data can be rewritten flexibly with a relatively small circuit configuration.
[Brief description of the drawings]
FIG. 1 is a diagram showing “ON writing” image processing according to an embodiment;
FIG. 2 is a diagram illustrating “OFF writing” image processing according to the embodiment;
FIG. 3 is a configuration diagram of a memory control device according to the embodiment;
4 is a diagram showing a relationship between a write mask signal and data update by the memory control device of FIG. 3; FIG.
FIG. 5 is another configuration diagram of the memory control device of FIG. 3;
6 is a configuration diagram of a display device using the memory control device of FIG. 3. FIG.
[Explanation of symbols]
10 memory, 12 instruction register, 14 mode register, 22 first comparator, 24 second comparator, 26 third comparator, 28 fourth comparator, 32 first EXOR, 34 second EXOR, 36 third EXOR, 38 fourth EXOR , 100 memory control device, 200 background image, 202 foreground image, 204 composite image, 300 display device, 320 CPU.

Claims (2)

An image composition device that overwrites background image data with foreground image data and synthesizes these images,
A memory having a data bus width n times the unit data width of writing (n is an integer of 2 or more) and storing input image data;
An instruction register for holding a data value for instructing whether or not to overwrite the foreground image data with respect to the memory in which the background image data is stored;
And n comparators that input data of each pixel of the foreground image and data held in the instruction register and output based on the comparison result,
The data width of each pixel of the foreground and background image data is equal to the unit data width of the writing, and the data bus width is n times the data width of each pixel of the foreground and background image data,
An image synthesizing apparatus characterized in that the outputs of these n comparators respectively form data overwriting permission / inhibition logic for each unit data width of the memory. A video display device that displays a composite image obtained by combining foreground image data and background image data,
A memory having a data bus width n times the unit data width of writing (n is an integer of 2 or more) and storing input image data;
An instruction register for holding a data value for instructing whether or not to overwrite the foreground image data with respect to the memory in which the background image data is stored;
N comparators for inputting the data of each pixel of the foreground image and data held in the instruction register and outputting based on the comparison results;
A display unit for displaying the output from the memory;
The data width of each pixel of the foreground and background image data is equal to the unit data width of the writing, and the data bus width is n times the data width of each pixel of the foreground and background image data,
An image display device characterized in that the outputs of these n comparators respectively form data overwriting permission / inhibition logic for each unit data width of the memory.

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