JP2003256271A - Memory control method and apparatus, and display device using these - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a memory control technology for rewriting only a required part at high speed even in a memory having a wide bus width. <P>SOLUTION: The data of a background image are stored in a memory 10. As write data, the data of an upper layer image are propagated. A data value to permit write is written in an instruction register 12 in advance. Data are compared for each byte by a first comparator 22 or the like and when data to permit write come, the signal of an MSK1 or the like is negated. In the other case, the MSK1 or the like is asserted and rewrite is protected. <P>COPYRIGHT: (C)2003,JPO

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a memory control technique and a display device, and more particularly to a method and a device for controlling writing of data in a memory, and a display device that can utilize them.

[0002]

2. Description of the Related Art The progress of digital technology is remarkable in the world of broadcasting, and digital television receivers (hereinafter, also simply referred to as digital televisions) are becoming popular as products that widely affect the lives of the general public. . The digital television has a built-in CPU (central processing unit) and performs various data processing such as image processing.

An example of such processing is superimposition of images, for example, a normal video is displayed in the background, and data-broadcast information is displayed thereon. For this purpose, the CPU temporarily converts the text data corresponding to the character into image data, and the OSD (on-screen display) processing unit or the like superimposes the image data on each other by α blending or another method, and draws this. CP
Due to the processing by U, a wide variety of video expressions are realized.

[0004]

When processing image data, the data is often temporarily stored in a memory such as a frame buffer (hereinafter simply referred to as a memory). The entry bit width of the memory (which is also simply referred to as the memory bus width) is set to be wide to some extent in order to speed up drawing. For example, even when data is written in 1-byte units for drawing, the memory The bus width is 4 bytes. This bus width is realized by juxtaposing one to several memory elements.

However, if the rewriting of a part of the bytes is necessary because of the wide bus width, for example, if the "read-modify-write" mode of the known memory is used, the data of the bytes that do not need to be rewritten are also once. It is necessary to read it out and write it back as it is. Therefore, even if the bus width is widened to cope with the speedup, two cycles of the read cycle and the write cycle are required, which may be contrary to the original purpose.

The present invention has been made in view of these problems, and an object thereof is to provide a memory control technique for rewriting only a necessary portion at high speed even in a memory having a wide bus width. . Another object is to provide a memory control technique that flexibly implements necessary data rewriting with a relatively small circuit configuration. Still another object is to provide a display device that utilizes those technologies and enjoys the effects thereof.

[0007]

One aspect of the present invention is a memory control method, and when writing data to a memory, when the data value satisfies a predetermined relationship with a preset value, the writing of the data is performed. When the data value does not satisfy the predetermined relationship, the write mask signal is output to prohibit the data writing.

This technique determines whether or not writing to the memory is possible according to the data value. The “predetermined relationship” is, for example, a “match” relationship. For example, "00
If the value "h" is set in advance, the data is written to the memory only when the value of the write data to the memory is "00h". Values other than "00h" are not written and the original data is retained in the memory. Therefore, unlike read-modify-write, desired rewriting is realized in one write cycle. This technique is useful when storing data in a state where character data is overwritten on a background image in a memory, as in “ON writing” described later.
As another example, if the relationship is "mismatch",
The “OFF writing” described later is realized.

Another aspect of the present invention is a device for controlling a memory having a data bus width n times (n is a natural number) the unit data width for writing, and a data value indicating whether data writing is permitted or not. And a write data for the memory are received at the first port for each unit data width, and the output of the instruction register is shared by the second port.
N comparators that are received at the port of the memory, and the outputs of these n comparators respectively form the logic of data write permission / prohibition for each unit data width of the memory.

"Data value indicating whether data writing is permitted or not"
Is an example of a data value to which data writing should be permitted. Another example is a data value whose data writing should be prohibited. An example of “forming the logic of permission / prohibition of data writing” is “become a signal itself for permitting or prohibiting data writing, or be an input of a circuit generating the signal”. Therefore, this device permits or prohibits writing to the memory, or generates a factor for permitting or prohibiting, depending on the data value. This device also does not require the two cycles of read-modify-write.

The memory control device further includes a logic switching circuit having a mode in which the output of the n comparators is output in the logic as it is and a mode in which the output is inverted and output, and the output of the circuit is a write mask signal. May be input to the memory as.

Yet another aspect of the present invention is a display device, which comprises any of the memory control devices described above, and the write data is drawing data, and Realize partial rewriting.

It is to be noted that any combination of the above constituent elements, and the expression of the present invention converted between a method, an apparatus, a system, a recording medium, a computer program and the like are also effective as an aspect of the present invention.

[0014]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT FIGS. 1 and 2 show the dual logic for generating a composite image 204 by superimposing a background image 200 and a foreground image 202. Foreground image 202
Is originally text data, but here it has already been converted to image data. Also, the foreground image 20
2 does not always come to the foreground depending on the processing, but is referred to as such for convenience.

In FIG. 1, the characters of the foreground image 202 are superimposed on the background image 200. In the composite image 204, only the part of the foreground image 202 with the characters is the image of the foreground image 202, and the other parts. Is an image of the background image 200. This is a method used when displaying information that has been data-broadcasted on a background moving image in the form of a telop or other form, and is hereinafter referred to as "ON writing".

Contrary to FIG. 2, in the composite image 204, only the marked portion of the foreground image 202 is the background image 200.
The image of the foreground image 202 is the other image. This can be used for the purpose of showing the background moving image as a watermark only in the mark part, and is referred to as "OFF writing" below.

The present embodiment is based on the knowledge that such characters and marks are often monochrome or expressed with a very small number of colors as compared with the background moving image. For example, in the ON writing of FIG. 1, it is assumed that the portion of the character "A" is a black single color. Then, the composite image 204
Of the background image 200, only the pixels that are “black” in the foreground image 202 need to be rewritten to that color. Therefore, the outline of the memory control is as follows.

1) The background image 200 is stored in the memory. 2) While scanning the foreground image 202, the pixel values thereof are sequentially overwritten on the background image 200. However, at this time,
Of the pixels of the foreground image 202, the "write mask signal" is asserted at the timing of writing the pixel which is found not to be "black", that is, the pixel is output as active, and the contents of the memory are write-protected.

By this processing, only the black pixels in the foreground image 202 are overwritten on the background image 200, and the composite image 204 is obtained. In the case of OFF writing, the logic of the "write mask signal" may be inverted.

FIG. 3 is a circuit diagram of the memory control device 100 that realizes the above control. In the figure, the write data is 32 bits of D0-31, but for simplicity and convenience of description, B1, B2, B3, in order from the lower byte.
It is written as B4. Memory 10 has a data bus width of 4
The writing unit data width is 1 byte. Control signals and address signals are omitted. Memory 10 has write mask inputs MSK1-4, which protect the writing of bytes B1-4, respectively. In this figure, all signals are determined to be high and active, but this is not a limitation.

The memory control device 100 has an instruction register 12 related to the instruction of data write permission. A desired value is set in the instruction register 12 by the CPU. The output of the instruction register 12, that is, the set value S is the first comparator 2
2, second comparator 24, third comparator 26, fourth comparator 28
Is commonly input to the second port of the. These comparators compare the input data value of the first port and the input data value of the second port, and when they match, the CPO
Assert UT1-4. Bytes B1 to B4 of write data are input to the first ports of the first comparator 22, the second comparator 24, the third comparator 26, and the fourth comparator 28, respectively.

Outputs CPOUT1 to 4 of the comparator are respectively a first EXOR 32, a second EXOR 34 and a third EXOR.
36, the fourth EXOR 38 (EXOR indicates an exclusive OR gate) is connected to one input. These EXO
An ON signal 16 is connected to the other input of R. The mode register 14 sets the ON signal 16 to high or low. When the CPU specifies "ON writing" for the mode register 14, the ON signal 16 becomes high, and "OF" is set.
It becomes low when "F writing" is specified. First EXOR3
2, second EXOR34, third EXOR36, fourth EXO
The outputs of R38 become the write mask signals MSK1 to MSK4 of the memory 10, respectively. First EXOR 32, second EXOR
34, the third EXOR 36, the fourth EXOR 38 and the mode register 14 act as a logic switching circuit for the write mask signal.

The operation of the above configuration will be described. The image data of the background image 200 is already stored in the memory 10. The data of the foreground image 202 is sequentially sent as the write data D0-31. This data sequentially overwrites the memory 10, but if the write data is data other than "black" in bytes, the write mask signal becomes active for that byte and writing is blocked.
Assuming that the pixel value indicating "black" is "00h", "00h" is written from the CPU to the instruction register 12 before the data transfer. In addition, the mode register 14
Similarly, "ON writing" is designated by the CPU.

Now assume that the data of byte B1 is "00".
h ”, not black. At this time, the output CPOUT1 of the first comparator 22 becomes low. ON signal 16
Is high, the output MSK1 of the first EXOR 32 goes high, preventing writing of this byte, and the background image 200
Data remains. On the contrary, if the data of the byte B1 is "00h", that is, black, the output CPOUT1 of the first comparator 22 becomes high and the write mask signal MSK1 which is the output of the first EXOR 32 becomes low. Writing is permitted, and the data of the foreground image 202 is written in the memory. The same applies to the other bytes. By repeating this operation, only black pixels of the data of the foreground image 202 are written in the memory, and ON writing is realized.

FIG. 4 shows the relationship between the write mask signals MSK1 to MSK4 and the rewriting of the bytes B1 to B4. In the figure, MSK1 = M
SK4 = 1, MSK2 = MSK3 = 0, byte B
2 and B3 are updated, and bytes B1 and B4 hold the previous value. Since data comparison is performed in byte units, rewriting permission / prohibition can be controlled in byte units as shown in this figure.

FIG. 5 shows another form of the memory control device 100. Although only the instruction register 12 and the first comparator 22 are drawn here, the second comparator 24, the third comparator 26,
The second port of the fourth comparator 28 has the same input as that of the first comparator 22. Of course, the corresponding byte of data is input to the first port.

In this embodiment, two sub-registers A12a and B12b are provided inside the instruction register 12.
Is provided, and two values can be set from the CPU.
For convenience, the sub-register A12a and the sub-register B12b
The values set in are described as DA and DB (DA ≦ DB), respectively. Further, the value indicated by the byte B1 is expressed as X.
There are several possible specifications for the first comparator 22, and there are the following examples, for example.

1. CPOUT1 = 1 only when X = DA or X = DB 2. Only when DA ≦ X ≦ DB, CPOUT1 = 1, that is, whether data writing is permitted or not may be directly designated by a plurality of data values or may be designated by a range. Of course, the sub-registers can be any number greater than or equal to three.

FIG. 6 shows a configuration of a display device 300 using the above memory control device 100, more specifically, a television receiver. The broadcast wave is given to the tuner 304 via the antenna 302. The stream demodulated here is sent to the audio / image decoder 306. The audio / image decoder 306 decodes a packet corresponding to a desired channel according to, for example, the MPEG specifications, and outputs audio data to the audio processing unit 308 and image data to the image processing unit 310, respectively. The voice processing unit 308 performs predetermined processing on the voice data, and finally voice is output to the speaker 330. The image processing unit 310 performs a predetermined process on the input image data and stores the processed data in the memory 10.
A memory control device 100 is attached to the memory 10.

The CPU 320 centrally controls each of the above parts. In the memory 10, the speaker 330 and the memory control device 100 cooperate to turn on or off the necessary
Writing processing is performed, and the output of the memory 10 is output to a desired display unit 332 via an encoder 312 conforming to NTSC or the like.

The present invention has been described above based on the embodiments. It should be understood by those skilled in the art that this embodiment is merely an example, and that various modifications can be made to the combinations of the respective constituent elements and the respective processing processes, and that such modifications are also within the scope of the present invention. is there. Below, such an example is given.

The memory control device 100 may be wholly or partly incorporated in one LSI. This LSI
May be a so-called graphic controller.

In the embodiment, the write mask input of the memory 10 is used to prohibit the writing of data. When this signal is not present, for example, there is a method of negating, ie, inactively outputting a signal (CAS) provided for each byte of the memory 10 or the like, which determines a write operation. Since the CAS signal is generally low active, the output signal of the first EXOR 32 or the like and the OR signal of the CAS signal may be given to the memory 10 as a new CAS signal.

In the embodiment, the display device 300 is exemplified as the application of the memory control device 100.
Of course, there are other uses. For example, it can be applied to any computer such as a PC (personal computer) or any digital video device.

[0035]

According to the present invention, memory control for rewriting only a necessary part at high speed and its application device are realized. In addition, necessary data can be rewritten flexibly with a relatively small circuit configuration.

[Brief description of drawings]

FIG. 1 is a diagram showing image processing of “ON writing” according to an embodiment.

FIG. 2 is a diagram showing image processing of “OFF writing” according to the embodiment.

FIG. 3 is a configuration diagram of a memory control device according to an embodiment.

FIG. 4 is a diagram showing a relationship between a write mask signal and data update by the memory control device of FIG. 3;

5 is another configuration diagram of the memory control device of FIG. 3. FIG.

6 is a configuration diagram of a display device using the memory control device of FIG.

[Explanation of symbols]

10 memory, 12 instruction register, 14 mode register, 22 first comparator, 24 second comparator,
26 3rd comparator, 28 4th comparator, 32 1st
EXOR, 34 2nd EXOR, 36 3rd EXO
R, 38 4th EXOR, 100 memory controller,
200 background image, 202 foreground image, 204
Composite image, 300 display device, 320 CPU.

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁷ Identification symbol FI theme code (reference) G09G 5/00 550 G09G 5/00 550P 5/393 5/36 530E F term (reference) 5B060 DA04 GA01 5B069 AA01 BC02 LA02 LA12 LA15 5C082 AA02 BA12 BA27 BB03 BB13 BB15 BB22 BB53 CA56 DA22 DA42 DA54 DA64 DA73 DA86 MM02

Claims (4)

[Claims] 1. When writing data to a memory, when the data value satisfies a predetermined relationship with a preset value, the writing of the data is executed as it is, and the data value satisfies the predetermined relationship. A memory control method characterized by outputting a write mask signal to inhibit data writing when there is no data. 2. A device for controlling a memory having a data bus width n times (n is a natural number) the writing unit data width, and an instruction register for holding a data value for instructing permission or prohibition of data writing. , N comparators that receive write data to the memory for each unit data width at the first port and commonly receive the output of the instruction register at the second port, A memory controller, wherein outputs of n comparators form a logic of data write permission / prohibition for each unit data width of the memory. 3. A logic switching circuit having a mode in which the outputs of the n comparators are output in the same logic as that of the logic and a mode in which the outputs are inverted and output, and the output of the circuit is supplied to the memory as a write mask signal. The memory control device according to claim 2, wherein the memory control device is input. 4. A display device comprising the memory control device according to claim 2 or 3, wherein the write data is drawing data, and partial rewriting of data to be displayed is realized.