JPH0439760A - Data processing system - Google Patents

Abstract

PURPOSE:To improve the processing speed of the whole system by releasing a system bus to an exclusive processor and transferring data from a main memory to an exclusive memory, and thereafter, returning the system bus 2 and allowing it to execute a specific data processing on the exclusive memory. CONSTITUTION:When a system bus is released, a reading-out means B1 of an exclusive processor B reads out data of a processing object to an exclusive memory D from a main memory C. When read-out by the reading-out means B1 is finished, a returning means B2 returns the system bus to a general processor A. A first processing control means B3 accesses the data read out to the exclusive memory D through an internal bus and executes a specific data processing. A second processing control means A1 of the general processor A executes a different processing by utilizing the system bus and the main memory C. In such a way, the processing can be executed at a higher speed by utilizing the main memory and the system bus.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a data processing system comprising a dedicated processing device that specializes in specific data processing based on instructions from a general-purpose processing unit.

[Summary of the Invention] This invention provides, in the above data processing system, a dedicated memory that is used exclusively by the dedicated processing device in addition to the main memory, and when performing specific data processing, the system bus is released to the dedicated processing device. This dedicated processing device transfers the data to be processed from the main memory to the dedicated memory, and then returns the system bus to general-purpose processing to perform specific data processing on the dedicated memory. The exclusive period of main memory and system bus is shortened, and even if data processing is performed by a dedicated processing device, the general-purpose processing device can use the main memory and system bus to perform other processing in the remaining period. By performing these steps in parallel, the processing speed of the entire system is further increased.

[Prior Art] In order to speed up specific data processing such as sorting and merging on variable-length data stored in memory, the applicant first performed the processing on a dedicated processing device, and analyzed the processing results. We have devised a system that uses only the
An application was filed (Japanese Patent Application No. 1751.22/1983).

This system aims to speed up specific data processing.
As a result, the general-purpose processing device can perform more processing, and the processing efficiency of the entire system can be improved.

[Problems to be Solved by the Invention] However, in the above system, after instructing the dedicated processing device to process specific data, the general-purpose processing device The system remains in a processing waiting state for a long time, and especially when the amount of data to be processed is enormous, the processing waiting time of the general-purpose processing device becomes long, and there is a limit to how much the processing efficiency of the entire system can be improved.

This is due to the fact that during the above period, the main memory and system bus remain exclusively occupied by the dedicated processing unit, and during this exclusive period, the general-purpose processing unit cannot utilize the main memory or system bus to perform other processing. .

In other words, if the period during which the main memory and system bus are exclusively occupied by a dedicated processing device can be shortened, then even if the dedicated processing device is performing specific data processing, the general-purpose processing device can be used as the main It is clear that it is possible to utilize memory and the system bus to execute other processes in parallel, further increasing speed.

An object of the present invention is to shorten the period during which a main memory and a system bus are occupied by a dedicated processing device so that the dedicated processing device and the general-purpose processing device can execute separate processes in parallel.

[Means to solve the problem] The means of this invention are as follows.

General-purpose processing procedure A (see the functional block diagram in Figure 1; the same applies hereinafter) performs various data processing such as data input/output and data processing, and data processing is performed by dedicated processing device B described below. When a request is made, the processing result is used to perform a predetermined process.

The dedicated processing device B specializes in specific data processing such as sorting and merging based on instructions from the general-purpose processing device A.

Main memory C is connected to general purpose processing unit A and special purpose processing unit B via a system bus.

Dedicated memory D is connected to dedicated processing device B via an internal bus.

The reading means B1 of the dedicated processing device B reads the data to be processed from the main memory C to the dedicated memory D via this system bus when the system bus is released from the general-purpose processing procedure A when performing specific data processing. When the reading by the reading means B1 is completed, the returning means B2 outputs the
Return the system bus to general purpose processing procedure A. The first processing control means B3 accesses the data read into the dedicated memory D via the internal bus and performs specific data processing.

The second processing control means A1 of the general-purpose processing procedure A executes another process by utilizing the returned system bus and main memory C in response to the return of the system bus by the return means B2.

[Work] The operation of the means of this invention is as follows.

Now, the general-purpose processing unit A instructs the dedicated processing unit B to perform a sorting process on a predetermined variable-length data string in the main memory C, and the system bus is released from the general-purpose processing unit A. shall be.

Then, the reading means B1 of the dedicated processing device B reads the specified variable length data from the main memory C to the dedicated memory D using the released system bus.

Then, when the reading by the reading means B1 is completed, the returning means B2 immediately returns the system bus to the general-purpose processing procedure A.

After this return, the first processing control means B3 accesses the variable length data string read into the dedicated memory D via the internal bus and performs a sorting process. In other words, the first processing control means B3 Since data processing is performed without using the main memory C and the system bus, the first processing control means B
While data processing is being performed in step 3, the main memory C and system bus are available for use by other devices.

Therefore, the second processing control means A1 of the general-purpose processing procedure A,
Utilizing the returned system bus and main memory C,
Another process is executed in parallel with the data processing by the first processing control means B3.

Therefore, the exclusive period of the main memory and system bus by the dedicated processing device is shortened, and the dedicated processing device and the general-purpose processing device can execute separate processes in parallel.

[Example] An example will be described below with reference to FIGS. 2 to 9.

FIG. 2 is a system configuration diagram of the data processing system, which includes a general-purpose data processing device 1, a variable-length data processing device 2, a magnetic disk 3, a disk controller 4, a main memory 5, and various input/output devices 6 and a system bus. Connected by SB. In addition, each of these devices and system bus 3
Gate arrays are provided between all the 8th and 8th
In the figure, only the gate array G1 between the general-purpose data processing device 1 and the system bus 38 and the gate array G2 between the variable-length data processing device 2 and the system bus 38 are shown. Also,
A local memory 7 is connected to the variable length data processing device 2 via an internal bus IB.

The general-purpose data processing device 1 controls input/output between the main memory 5, the magnetic disk 3, and the input/output device 6, and performs various data processing on the main memory 5 while managing the right to use the system bus SB. In addition, it instructs the variable length data processing device 2 to perform specific data processing such as sorting.

The variable length data processing device 2 includes a control circuit 21, a first address control circuit 22, a second address control circuit 23, a firmware instruction memory 24, a read buffer 25, an arithmetic circuit 26,
It has a designated delimiter register 27 and a delimiter detector 28, which are connected by an internal bus IB. When the general-purpose data processing device 1 releases the system bus SB to the variable-length data processing device 2 and instructs it to perform specific data processing, the variable-length data processing device 2 releases the variable-length data to be processed. After the data is transferred from the main memory 5 to the local memory 7, the system bus SB is immediately returned, and data processing related to the instruction is executed using the local memory 7, internal bus IB, etc.

In other words, the variable length data to be processed is stored in the local memory 7.
By reading data to main memory 5 and system bus S
Execute data processing without using B.

The firmware instruction memory 24 stores firmware instructions as shown in FIG. That is, this firm instruction is a macro instruction for instructing a series of processing on variable length data, and examples of this firm instruction include sorting, merging, etc.

These firm instructions are composed of a plurality of microinstructions such as transfer, comparison, and addition, and each microinstruction has an operand for microinstruction code, an address part, a mode part, a processing unit part, and the like. Here, mode 1 specified in the mode section indicates that the microinstruction is to be executed under address control by the first address control circuit 22, and mode 2 indicates that the microinstruction is to be executed under address control by the first address control circuit 22.
This indicates that the microinstruction should be executed under address control by . In addition, in the processing unit section, the fourth
A delimiter (separator code) such as a word end code, record start code, track end code, etc. corresponding to the symbol mark ""(","Z" shown in the figure) is specified. is data other than the delimiter, and each data (including the delimiter) is 1 byte.

Furthermore, the first and last microinstructions in each firmware instruction are both transfer microinstructions that instruct data transfer between the main memory 5 and the local memory 7.

That is, in the address part of the transfer microinstruction, main memory address MA, address, and address LA indicating the addresses of main memory 5 and local memory 7, respectively.
is specified. These main memory addresses MA,
Specifically, in the first transfer microinstruction, the local memory address LA is the local write address (
LA), the main read address (MA) is specified,
In the final transfer microinstruction, the main write address (
MA), a local read address (LA) is specified. That is, as shown in FIG. 5, the first transfer microinstruction is an instruction to transfer the data to be processed from the main memory 5 to the local memory 7, and the last transfer microinstruction is an instruction to transfer the processed data (operation result). This is an instruction to transfer data from the local memory 7 to the main memory 5. Note that, as shown in FIG. 5, arithmetic operations such as comparison and addition are executed on the local memory 7, so the address of the local memory 7 is specified in the address section of the microinstruction that instructs these arithmetic operations. has been done.

Based on the firmware instruction from the general-purpose data processing device 1, the control unit 1 sequentially reads and decodes each microinstruction of the corresponding firmware instruction in the firmware instruction memory 24, and stores the address, mote, and delimiter via the internal bus IB. , R/W
outputs the access signal etc. to the corresponding component.

The first address control circuit 22 has a main address register 22m and a local address register 221, and the main memory address MA and local memory address LA from the control circuit 21 are initially set in these registers, respectively. The first address control circuit 22 controls data transfer between the main memory 5 and the local memory 7 while incrementing the contents of each of these registers by 1.

The second address control circuit 23 controls the address for the local memory 7 necessary when performing arithmetic processing such as comparison and addition on the data transferred to the local memory 7. That is, when performing these arithmetic operations, the data in the local memory 7 is read out in units of bytes based on the read address specified by the second address control circuit 23.
After being stored in the read buffer 25, the arithmetic circuit 2
6, and the calculation result in this calculation circuit 26 is output to the second
The data is stored in the local memory 7 based on the write address specified by the address control circuit 23.

Note that the address control by the first address control circuit 22 and the second address control circuit 23 is performed when the delimiter (transfer unit) specified by the instruction set in the specified delimiter register 27 is detected by the edge limiter detector 28. This will continue until

Next, the operation of the variable length data processing device when performing specific data processing will be described with reference to FIGS. 6 to 9.

First, the startup operation performed on the general-purpose data processing device 1 or the variable-length data processing device 2 will be explained based on FIG.

The general-purpose data processing device 1 transfers the data to be processed in the magnetic disk 3 to the main memory 5 via the disk controller 4 and the system bus SB (see step S1 in FIG. 6 and ■ in FIG. 9), and In order to release the system bus SB to the variable length data processing device 2, the gate array G1
and opens the gate array G2 (step 52).Next, the firmware instruction code is output to the variable length data processing device 2 to start it up (step S3).

Then, in response to this activation, the variable length data processing device 2
transfers the data to be processed from the main memory 5 to the local memory 7, and when the transfer is completed, outputs a transfer end signal to the general-purpose data processing device 1, so it waits for the input of the transfer end signal. (Step S4, 9th
(See figure ■).

When the transfer end signal is input, the general-purpose data processing device 1 immediately opens the gate array G1 and closes the gate array G2 in order to regain the right to use the system bus SH (step S5). Transition to (
(See Figure 9 ■).

Next, the operation of the variable length data processing device 2 will be explained with reference to FIG.

When the control circuit 21 of the variable-length data processing device 2 receives a firm instruction code from the general-purpose data processing device 1, it reads out the first transfer microinstruction corresponding to the firm instruction from the firm instruction register 24 (the first 7, step S 101 >', and sets the delimiter specified as a transfer unit in the transfer microinstruction in the specified delimiter register 27 (step 5102).
Further, the main read address MA and local write address LA specified by the transfer microinstruction are initialized in the main address register 22m and local address register 221 in the first address control circuit 22, respectively (step 5103). Furthermore, mode 1 specified by the transfer microinstruction is specified to the first address control circuit 22 (step 5104).

In response to the preprocessing by the control circuit 21, the first address control circuit B22 controls the main address register 22m,
While updating each address initialized in the local address register 221 by 1, the variable length data to be processed in the main address 5 is sequentially transferred to the local memory 7 in 1-byte units (step 5105). On this occasion,
The data transferred to the local memory 7 is read to the read buffer 25 and output to the delimiter detection circuit 28 each time. The delimiter detection circuit 28 then compares the data from the read buffer 25 with the delimiter set in the designated delimiter register 27.
A limiter that is not specified as a transfer unit by the transfer microinstruction is detected from the transfer data.

Therefore, the control circuit 21 determines whether or not the delimiter is detected by the delimiter detection circuit 28 (step 5106). As a result, if the delimiter is not detected, the process returns to step 5105, and when the delimiter is detected, Instructs the first address control circuit 22 to stop the transfer and outputs a transfer end signal to the general-purpose data processing device 1 (step 5107), that is, the variable length data shown in ■ in FIG. When the word end code, record start code, or track end code delimiter corresponding to the symbol mark ","(""2" is specified for the column as the transfer unit, the symbol mark ","("
, The data strings indicated by ■ are transferred.

Based on this transfer end signal, the right to use the system bus SB is transferred from the variable-length data processing device 2 to the general-purpose data processing device 1.
As described above, each process of 0 or more steps 5101 to 5107 corresponds to (2) in FIG.

Next, the control circuit 21 reads the second and subsequent microinstructions in the firm instruction register one by one, performs the above-mentioned preprocessing according to the instructions, and performs the arithmetic processing corresponding to the microinstructions. The processing circuit 26 etc. executes (
Step 5108).

In this case, the control circuit 21 controls the first address control circuit 22.
Specify mote 2 for . That is, under address control by the first address control circuit 22, data in the local memory 7 is read out to the read buffer 25 in units of bytes, and is subjected to arithmetic processing in the arithmetic processing circuit 26. And the calculation result is the first address control time! It is written into the low camera memory 7 under address control by @22. In other words, this arithmetic processing is executed on the local camera memory 7, and the main memory 5 is not used at all. Furthermore, data reading from the local memory 7 based on each arithmetic microinstruction is performed using the delimiter specified by each arithmetic microinstruction. The calculation is executed continuously until the calculation is detected, and the calculation processing in the calculation processing circuit 26 is also performed in units as shown in FIG.

Next, the control circuit 21 determines whether the arithmetic processing in the firm instruction has been completed by determining whether the next microinstruction to be executed is the final transfer microinstruction in the firm instruction. A judgment is made (step 5109). As a result, if the arithmetic processing is not completed, the process returns to step 8108 to continue the arithmetic processing. Note that each process in steps 5108 and 5109 above is performed in the ninth step.
Corresponds to ■ in the figure.

When the arithmetic processing is completed, the same preprocessing as for the first transfer microinstruction is performed on the final transfer microinstruction.

That is, the control circuit 21 reads the final transfer microinstruction from the firmware instruction register 24 (step 511).
0), and the delimiter specified as the transfer unit in the transfer microinstruction is stored in the specified delimiter register 2.
7 (step 5ill), and the main write address MA specified in the transfer microinstruction above.
, the local read address LA is initialized in the main address register 22m and the local address register 221 in the first address control circuit 22, respectively (step 5112), and furthermore, the mode 1 specified by the transfer microinstruction is set as follows: The address is designated to the first address control circuit 22 (step 511B).

Then, the control circuit 21 outputs an end interrupt signal to the general-purpose data processing device 1 (step 5114), and waits for input of a transfer permission signal given from the general-purpose data processing device 1 in response to the signal (step 5115). Then, when the transfer permission signal is input, the first address control circuit 22
While updating each address initialized in the main address register 22m and the local address register 221 by 1°, the processing results in the local memory 7 are updated by 1°.
Step S116) in which the data is sequentially transferred to the main memory 5 in byte units.

Then, the control circuit 21 determines whether or not the delimiter is detected by the delimiter detection circuit 28 (step 5117). As a result, if the delimiter is not detected, the control circuit 21 returns to step 8116 to continue the transfer, When detected, it instructs the first address control circuit 22 to stop the transfer, outputs a transfer end signal to the general-purpose data processing device 1 (step 3118), and completes 0 or more steps 5110 to 5118. Each process corresponds to ■ in FIG.

Next, the general-purpose data processing device 1 based on the above-mentioned end interrupt signal
The operation will be explained with reference to FIG.

With the completion of the arithmetic processing in the variable length data processing device 2,
When the above-mentioned end interrupt signal is input, the general-purpose data processing device 1 interrupts the process currently being executed (step S21 in FIG. In order to release the system bus SB to the variable length data processing device 2 so that the results can be transferred to the main memory 5, the gate array G1 is closed and the gate array G2 is opened (step 522), and then the transfer described above is performed. Step 32: Output a permission signal to the variable length data processing device 2.
3) Wait for the input of the transfer end signal from the variable length data processing device 2 (step 524), and when the transfer end signal is input, open the gate array G1 in order to regain the right to use the system lot SB, The gate array G2 is closed (step 525), and the interrupt processing ends.

The main memory 5 and system bus S in the operations of the general-purpose data processing device 1 and the variable-length data processing device 2 described above.
The transition of the exclusive status of B is as shown in FIG. That is, when the variable-length data processing device 2 is executing arithmetic processing other than data transfer, the general-purpose data processing device 1 monopolizes the main memory 5 and system bus SB to execute other processing. . In other words, the arithmetic processing by the variable-length data processing device 2 and another processing by the general-purpose data processing device 1 are executed concurrently.

In this case, as shown in FIG. 9, the general-purpose data processing device 1 can also execute an interrupt process related to an interrupt request from another input/output device 6 as another process.

The present invention is not limited to the above-described embodiments; for example, the specific data processing may be processing on normal data other than variable length data.

[Effects of the Invention] According to this invention, the exclusive period of the main memory and system bus by the dedicated processing device is shortened, and the dedicated processing device and the general-purpose processing device can execute separate processes in parallel, resulting in even higher speeds. It becomes possible to aim for.

Figure 1 is a functional block diagram of the present invention, Figure 2 is a system configuration diagram of an embodiment, Figure 3 is a configuration diagram of firmware instructions, Figure 4 is a configuration diagram of variable length data, and Figure 5 is a configuration diagram of firmware instructions. A diagram to explain the address specified by the microinstruction of
FIG. 6 is a flowchart showing the processing startup operation of the general-purpose data processing device for the variable-length data processing device, FIG. 7 is a flowchart showing the operation of the variable-length data processing device performed in response to the startup, and FIG. 8 is the variable-length data processing device. A flowchart showing the operation of the general-purpose data processing device performed in response to a termination interrupt from the data processing device, FIG. 9 is a time chart corresponding to FIGS. 6 to 8. 91 General-purpose data processing device, 2 ...Variable length data processing device, 5--Main memory, 7--Local memory, 21--Control circuit,
22--First address control circuit, 23--Second address control circuit, 24--Firm instruction memory, 26--Arithmetic circuit, Gl, G2--Gate array, SB--System bus, 1B--・Internal bus.

[Brief explanation of drawings]

No. figure (a) CC) Article figure ■ No. figure No. figure

Claims (1)

[Claims] A general-purpose processing procedure that performs various data processing, a dedicated processing device that specializes in specific data processing based on instructions from the general-purpose processing procedure, and a system bus that connects the general-purpose processing procedure to the general-purpose processing procedure. It has a main memory connected to a dedicated processing device and a dedicated memory connected to the dedicated processing device via an internal bus, and the general-purpose processing is performed in a predetermined manner using data processed by the dedicated processing device. When the system bus is released from the general-purpose processing when performing specific data processing, the dedicated processing device processes the data to be processed via the system bus. a reading means for reading data from the main memory to the dedicated memory; a return means for returning the system bus to general processing processing when the reading by the reading means is completed; and a first processing control means that accesses and performs specific data processing, and the general-purpose processing action utilizes the returned system bus and the main memory in response to the return of the system bus by the return means. A data processing system characterized by comprising second processing control means for executing another processing.