JPH04392B2 - - Google Patents
Info
- Publication number
- JPH04392B2 JPH04392B2 JP57186863A JP18686382A JPH04392B2 JP H04392 B2 JPH04392 B2 JP H04392B2 JP 57186863 A JP57186863 A JP 57186863A JP 18686382 A JP18686382 A JP 18686382A JP H04392 B2 JPH04392 B2 JP H04392B2
- Authority
- JP
- Japan
- Prior art keywords
- integrated circuit
- section
- rows
- external terminals
- film
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 239000003990 capacitor Substances 0.000 claims description 8
- 238000010030 laminating Methods 0.000 claims 1
- 239000004020 conductor Substances 0.000 description 11
- 239000002184 metal Substances 0.000 description 4
- 239000003989 dielectric material Substances 0.000 description 2
- 239000010408 film Substances 0.000 description 2
- 230000010354 integration Effects 0.000 description 2
- 229910000679 solder Inorganic materials 0.000 description 2
- 238000005476 soldering Methods 0.000 description 2
- 239000010409 thin film Substances 0.000 description 2
- 230000037431 insertion Effects 0.000 description 1
- 238000003780 insertion Methods 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 238000004806 packaging method and process Methods 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/40—Forming printed elements for providing electric connections to or between printed circuits
- H05K3/403—Edge contacts; Windows or holes in the substrate having plural connections on the walls thereof
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K1/00—Printed circuits
- H05K1/16—Printed circuits incorporating printed electric components, e.g. printed resistor, capacitor, inductor
-
- H—ELECTRICITY
- H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
- H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
- H05K3/00—Apparatus or processes for manufacturing printed circuits
- H05K3/36—Assembling printed circuits with other printed circuits
- H05K3/366—Assembling printed circuits with other printed circuits substantially perpendicularly to each other
Description
【発明の詳細な説明】
本発明は竪形集積回路に関し、特に入出力端子
構造を改良した竪形集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a vertical integrated circuit, and more particularly to a vertical integrated circuit with an improved input/output terminal structure.
従来、集積回路は絶縁体パツケージに収納さ
れ、外部への引出しは金属端子板やパツケージ外
周へ施された金属薄膜端子などにより行われてい
る。第1図は前者の例で内部に混成集積回路を収
容したパツケージ1から脚状の金属端子列2を引
出している。しかし、この例では端子を金属板か
ら作る必要があるだけでなく、端子の占有空間が
大きくなるために集積化が不十分である。第2図
の例は混成集積回路を収容したパツケージ又は全
体で一個の混成集積回路となつている集積体3の
側辺に導体を引出してそこに導電膜による外部端
子列4を焼付け形成したものである。この例では
端子が占める体積はほとんど問題にならず、又プ
リント配線基板へ集積回路を直接半田づけするこ
とができるなど、集積度及び作業性が高くなる利
益が得られる。しかしながら、この例においても
混成集積回路は水平型であるからそれを搭載する
プリント配線基の面積利用率は依然として制限を
受ける。 Conventionally, integrated circuits have been housed in insulator packages, and have been led out to the outside using metal terminal plates or thin metal film terminals applied to the outer periphery of the package. FIG. 1 shows an example of the former, in which leg-shaped metal terminal rows 2 are drawn out from a package 1 housing a hybrid integrated circuit therein. However, in this example, not only the terminals must be made from metal plates, but also the space occupied by the terminals becomes large, resulting in insufficient integration. The example shown in Fig. 2 is a package containing a hybrid integrated circuit, or an integrated body 3 that is a single hybrid integrated circuit, with conductors drawn out to the sides and external terminal rows 4 made of conductive films formed thereon by baking. It is. In this example, the volume occupied by the terminals is of little concern, and the integrated circuit can be directly soldered to the printed wiring board, providing the advantage of increased integration and workability. However, even in this example, since the hybrid integrated circuit is horizontal, the area utilization rate of the printed wiring board on which it is mounted is still limited.
本発明はプリント配線基板への搭載密度を高め
ることができる竪形集積回路を提供することを目
的とする。 An object of the present invention is to provide a vertical integrated circuit that can be mounted more densely on a printed wiring board.
本発明は、集積回路の外部端子構造を工夫する
ことにより上記目的を達成する。簡単に説明する
と、本発明は平板形の集積回路の側辺に薄膜形外
部端子を形成した型の集積回路において、該回路
の1つの側辺に形成される外部端子を絶縁間隙を
置いて上下に離間させて2つの列として形成させ
たことを特徴とする。これにより、この1つの側
辺をプリント配線基板の面に沿わせて平板形集積
回路を垂直に直立させた状態で半田づけ等により
プリント配線基板へ固定することができる。これ
によりプリント配線基板面の利用効率を極大にす
ることができる。 The present invention achieves the above object by devising the external terminal structure of an integrated circuit. Briefly, the present invention relates to a type of integrated circuit in which thin-film external terminals are formed on the sides of a flat integrated circuit, and the external terminals formed on one side of the circuit are connected above and below with an insulating gap between them. It is characterized in that it is formed in two rows spaced apart from each other. Thereby, the flat integrated circuit can be fixed to the printed wiring board by soldering or the like in a vertically erect state with this one side along the surface of the printed wiring board. This makes it possible to maximize the utilization efficiency of the printed wiring board surface.
以下、本発明の実施例を詳しく説明する。第3
図は本発明の特徴を有する混成集積回路5を示
し、回路3は内部及び/又は表面に所定の電子部
品を搭載した平板状の本体6と、本体の側辺に設
けられた薄膜状外部導体10,11,12,1
3,14から構成されている。本体6はコイル
L、コンデンサC、トランジスタTr、ダイオー
ド、配線導体等を表面や内部或いは両方に配置し
た従来公知の任意の混成集積回路より構成しうる
ものであるが、実施例では高誘電率系の誘電体を
ベースとするコンデンサネツトワーク7、及び温
度補償特性を有する誘電体をベースとするコンデ
ンサネツトワーク8,9の3層サンドイツチ構造
のものとして説明する。これらの各層には所要の
コンデンサ電極が対向して配置されると共に端部
はネツトワーク7,8,9の周部側辺に引出され
ている。また上下のコンデンサネツトワーク8,
9の露出面には抵抗R、コイルL等の受動素子や
トランジスタTrなどが印刷や半田付などの手段
で形成され、また配線導体が配置されている。 Examples of the present invention will be described in detail below. Third
The figure shows a hybrid integrated circuit 5 having the characteristics of the present invention, in which the circuit 3 includes a flat body 6 with predetermined electronic components mounted inside and/or on the surface, and a thin film external conductor provided on the sides of the body. 10, 11, 12, 1
It consists of 3 and 14. The main body 6 can be composed of any conventionally known hybrid integrated circuit in which a coil L, a capacitor C, a transistor Tr, a diode, a wiring conductor, etc. are arranged on the surface, inside, or both. A three-layer sandwich structure including a capacitor network 7 based on a dielectric material and capacitor networks 8 and 9 based on a dielectric material having temperature compensation characteristics will be described. Required capacitor electrodes are arranged in each of these layers to face each other, and the ends are drawn out to the peripheral sides of the networks 7, 8, and 9. In addition, the upper and lower capacitor networks 8,
On the exposed surface of 9, passive elements such as a resistor R and a coil L, a transistor Tr, etc. are formed by printing, soldering, or other means, and wiring conductors are arranged.
混成集積回路本体5の3つの側辺には、3つの
層7,8,9にまたがる複数の薄膜状接続導体1
1,12,10が設けられており、各層から露出
する引出導体及び本体表面の配線導体の必要な相
互接続を行つている。本体5の残る1つの側辺に
は絶縁間隙gを置いて上下に離間した2列の膜状
外部端子13,14が設けられており、これらは
外部回路への接続のため本体5から引出されてい
る引出導体へ電気接続されている。外部端子1
3,14は、図示のように上下層の稜部を覆うよ
うに形成されていることが望ましいが、場合によ
り本体の上下面(第3図で)に形成されても良
い。 A plurality of thin film-like connection conductors 1 are provided on three sides of the hybrid integrated circuit body 5, spanning three layers 7, 8, and 9.
1, 12, and 10 are provided for necessary interconnection of the lead conductors exposed from each layer and the wiring conductors on the surface of the main body. Two rows of membrane-like external terminals 13 and 14 are provided on the remaining side of the main body 5, vertically spaced apart with an insulating gap g, and these are pulled out from the main body 5 for connection to an external circuit. electrically connected to the lead-out conductor. External terminal 1
3 and 14 are preferably formed so as to cover the ridges of the upper and lower layers as shown, but may be formed on the upper and lower surfaces of the main body (as shown in FIG. 3) as the case may be.
上記のように構成したから、本発明の集積回路
はプリント配線基板へ高い実装密度で取付けるこ
とができる。第4図のように、プリント配線基板
15のプリント配線導体16,17の間に差込み
スロツトを設け、これに本発明の混成集積回路5
を垂直状態で外部端子13,14を下にして差込
み、半田18,19を盛つて所定の電気接続を行
う。或いは第5図のように、プリント配線基板1
5のプリント配線導体16,17の対向部分に混
成集積回路5の外部端子13,14が接するよう
に載せて半田18,19を盛る。このように、本
発明によれば、平板形の集積回路をプリント配線
基板に垂直に立てて取付けることができるので、
同様な集積回路を接近させて高密度に実装でき、
プリント配線基板の利用効率が非常に高くなる。 With the above configuration, the integrated circuit of the present invention can be mounted on a printed wiring board with high packaging density. As shown in FIG. 4, an insertion slot is provided between the printed wiring conductors 16 and 17 of the printed wiring board 15, and the hybrid integrated circuit 5 of the present invention is inserted into this slot.
is inserted vertically with the external terminals 13 and 14 facing down, and solder 18 and 19 is applied to make a predetermined electrical connection. Or, as shown in FIG. 5, the printed wiring board 1
The external terminals 13 and 14 of the hybrid integrated circuit 5 are placed on the opposing portions of the printed wiring conductors 16 and 17 of No. 5 so as to be in contact with each other, and solders 18 and 19 are applied thereto. As described above, according to the present invention, a flat integrated circuit can be mounted vertically on a printed wiring board.
Similar integrated circuits can be mounted close together at high density.
The usage efficiency of printed wiring boards becomes extremely high.
第1図及び第2図は従来の混成集積回路の2つ
の例の斜視図、第3図は本発明の混成集積回路の
拡大斜視図、第4図は同使用状態を示す側面図、
及び第5図は他の使用状態を示す側面図である。
図中主な部分は次の通りである。5…混成集積
回路、6…平板状回路本体、7,8,9…コンデ
ンサベース、10,11,12…接続導体、1
3,14…外部端子、g…絶縁間隙。
1 and 2 are perspective views of two examples of conventional hybrid integrated circuits, FIG. 3 is an enlarged perspective view of the hybrid integrated circuit of the present invention, and FIG. 4 is a side view showing the same state of use.
and FIG. 5 is a side view showing another state of use. The main parts in the figure are as follows. 5... Hybrid integrated circuit, 6... Flat circuit body, 7, 8, 9... Capacitor base, 10, 11, 12... Connection conductor, 1
3, 14...External terminal, g...Insulation gap.
Claims (1)
面に直行する1つの側面に、該側面の長手方向に
沿つて複数個の膜状外部端子を互いに絶縁間隔を
保つて2列に配列し、前記1つの側面をプリント
基板への直付け取り付け面とし、前記2列に配列
された膜状外部端子は前記1つの側面から、該側
面と前記2つの板面が交差する稜を覆うようにし
て前記2つの板面の縁部に延長されていることを
特徴とする竪形集積回路。 2 集積回路部は、平板形の少なくとも1つの積
層インダクタ部と、平板形の少なくとも1つの積
層コンデンサ部とを積層したものである前記第1
項記載の竪形集積回路。 3 集積回路部は、1つのインダクタ部が2つの
コンデンサ部により挾み込まれてなる前記第2項
記載の竪形集積回路。[Scope of Claims] 1. A plurality of film-like external terminals are arranged along the longitudinal direction of one side surface of an integrated circuit section having a flat plate shape, which is perpendicular to the parallel plate surface, at an insulating distance from each other. The film-like external terminals arranged in the two rows are arranged in two rows with the one side surface used as a mounting surface for direct attachment to the printed circuit board, and the film-like external terminals arranged in the two rows are arranged from the one side surface so that the side surface and the two plate surfaces intersect. A vertical integrated circuit, characterized in that the circuit is extended to the edges of the two plate surfaces so as to cover the edges of the two plates. 2. The integrated circuit section is formed by laminating at least one flat plate-shaped multilayer inductor section and at least one flat plate-shaped multilayer capacitor section.
Vertical integrated circuit as described in section. 3. The vertical integrated circuit according to item 2, wherein the integrated circuit section is formed by sandwiching one inductor section between two capacitor sections.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57186863A JPS5976454A (en) | 1982-10-26 | 1982-10-26 | Hybrid integrated circuit |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP57186863A JPS5976454A (en) | 1982-10-26 | 1982-10-26 | Hybrid integrated circuit |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS5976454A JPS5976454A (en) | 1984-05-01 |
JPH04392B2 true JPH04392B2 (en) | 1992-01-07 |
Family
ID=16195975
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP57186863A Granted JPS5976454A (en) | 1982-10-26 | 1982-10-26 | Hybrid integrated circuit |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS5976454A (en) |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH04128021U (en) * | 1991-05-17 | 1992-11-20 | 河村電器産業株式会社 | Wire sheath stripping device |
Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5119953A (en) * | 1974-08-08 | 1976-02-17 | Motorola Inc | Haipuritsudo sutoritsupurainkairo oyobi gaikairono seizohoho |
JPS526148B2 (en) * | 1972-05-18 | 1977-02-19 | ||
JPS5643716A (en) * | 1979-09-18 | 1981-04-22 | Tdk Electronics Co Ltd | Solid*layerrbuilt electronic circuit parts |
Family Cites Families (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS526148U (en) * | 1975-06-30 | 1977-01-17 |
-
1982
- 1982-10-26 JP JP57186863A patent/JPS5976454A/en active Granted
Patent Citations (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS526148B2 (en) * | 1972-05-18 | 1977-02-19 | ||
JPS5119953A (en) * | 1974-08-08 | 1976-02-17 | Motorola Inc | Haipuritsudo sutoritsupurainkairo oyobi gaikairono seizohoho |
JPS5643716A (en) * | 1979-09-18 | 1981-04-22 | Tdk Electronics Co Ltd | Solid*layerrbuilt electronic circuit parts |
Also Published As
Publication number | Publication date |
---|---|
JPS5976454A (en) | 1984-05-01 |
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