JPH0438860A - Manufacture method of semiconductor device lead frame - Google Patents
Manufacture method of semiconductor device lead frameInfo
- Publication number
- JPH0438860A JPH0438860A JP14579290A JP14579290A JPH0438860A JP H0438860 A JPH0438860 A JP H0438860A JP 14579290 A JP14579290 A JP 14579290A JP 14579290 A JP14579290 A JP 14579290A JP H0438860 A JPH0438860 A JP H0438860A
- Authority
- JP
- Japan
- Prior art keywords
- lead frame
- processing
- raw material
- plating
- rolling
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000004519 manufacturing process Methods 0.000 title claims description 30
- 239000004065 semiconductor Substances 0.000 title claims description 17
- 238000007747 plating Methods 0.000 claims abstract description 38
- 239000000463 material Substances 0.000 claims abstract description 31
- 238000005096 rolling process Methods 0.000 claims abstract description 25
- 229910052709 silver Inorganic materials 0.000 claims abstract description 15
- 239000004332 silver Substances 0.000 claims abstract description 15
- 238000005266 casting Methods 0.000 claims abstract description 12
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 claims abstract description 11
- 229910052737 gold Inorganic materials 0.000 claims abstract description 11
- 239000010931 gold Substances 0.000 claims abstract description 11
- 239000010970 precious metal Substances 0.000 claims abstract description 6
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 abstract description 14
- 238000005530 etching Methods 0.000 abstract description 9
- 229910000881 Cu alloy Inorganic materials 0.000 abstract description 5
- 238000000137 annealing Methods 0.000 abstract description 2
- 238000005520 cutting process Methods 0.000 abstract description 2
- 238000005098 hot rolling Methods 0.000 abstract description 2
- XEMZLVDIUVCKGL-UHFFFAOYSA-N hydrogen peroxide;sulfuric acid Chemical group OO.OS(O)(=O)=O XEMZLVDIUVCKGL-UHFFFAOYSA-N 0.000 abstract description 2
- 239000002994 raw material Substances 0.000 abstract 7
- OQTOQAYHQVKZET-UHFFFAOYSA-N oxalonitrile;silver Chemical compound [Ag].N#CC#N OQTOQAYHQVKZET-UHFFFAOYSA-N 0.000 abstract 1
- 238000007796 conventional method Methods 0.000 description 6
- 238000010586 diagram Methods 0.000 description 4
- BASFCYQUMIYNBI-UHFFFAOYSA-N platinum Chemical compound [Pt] BASFCYQUMIYNBI-UHFFFAOYSA-N 0.000 description 4
- 238000003825 pressing Methods 0.000 description 4
- 230000000694 effects Effects 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 2
- XEEYBQQBJWHFJM-UHFFFAOYSA-N Iron Chemical compound [Fe] XEEYBQQBJWHFJM-UHFFFAOYSA-N 0.000 description 2
- 229910052802 copper Inorganic materials 0.000 description 2
- 239000010949 copper Substances 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 238000005554 pickling Methods 0.000 description 2
- 229910052697 platinum Inorganic materials 0.000 description 2
- 229910052703 rhodium Inorganic materials 0.000 description 2
- 239000010948 rhodium Substances 0.000 description 2
- MHOVAHRLVXNVSD-UHFFFAOYSA-N rhodium atom Chemical compound [Rh] MHOVAHRLVXNVSD-UHFFFAOYSA-N 0.000 description 2
- 238000011282 treatment Methods 0.000 description 2
- 229910000990 Ni alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 238000005097 cold rolling Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 229910052742 iron Inorganic materials 0.000 description 1
- WABPQHHGFIMREM-UHFFFAOYSA-N lead(0) Chemical compound [Pb] WABPQHHGFIMREM-UHFFFAOYSA-N 0.000 description 1
- 229910000510 noble metal Inorganic materials 0.000 description 1
- 239000008188 pellet Substances 0.000 description 1
- 230000003746 surface roughness Effects 0.000 description 1
Landscapes
- Electroplating Methods And Accessories (AREA)
- Lead Frames For Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔産業上の利用分野１
本発明は半導体装置用リードフレームの製造方法に関し
、特に、広幅の素材を短冊状に切出す前にめっき処理を
施し７てリードフレームを製造する方法に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field 1] The present invention relates to a method for manufacturing a lead frame for a semiconductor device, and in particular, a method for manufacturing a lead frame by plating a wide material before cutting it into strips. It's about how to do it.
［従来の技術］
従来の半導体装置用リードフレームの製造方法は、第４
図に示すように、鋳造工程Ｓ１．圧延工程Ｓ２．スリッ
ティング工程Ｓ３を経た金属条又は金属板を用いて、プ
レス加工又はエツチング加工Ｓ４を施してリードフレー
ムを成形し、その後に金、銀等のめっき加工Ｓ５を施し
て製造していた。また、リードフレーム加工工程（プレ
ス加工）Ｓ４を行う前に、めっき加工Ｓ５を実施した後
、プレス加工をする方法もある。これらの製造方法は、
いずれの場合も、スリッティング工程Ｓ３を経て金属条
とした素材に、めっきを施していることが特徴である。[Prior Art] A conventional method for manufacturing a lead frame for a semiconductor device is the fourth method.
As shown in the figure, casting process S1. Rolling process S2. The metal strip or metal plate that has undergone the slitting process S3 is used to form a lead frame by performing press working or etching process S4, and then is manufactured by performing gold, silver, etc. plating process S5. Furthermore, there is also a method of carrying out the plating process S5 before performing the lead frame processing step (pressing process) S4, and then performing the press process. These manufacturing methods are
In either case, a feature is that plating is applied to a material made into a metal strip through the slitting step S3.
二のリードフレーム上のめっきは、半導体装置製造工程
のワイヤボンディングに必要であるため、ワイヤボンデ
ィング時の高温の空気中で酸化されにくい素材、即ち、
金、銀、白金、ロジウムのめっきを使用するのが一般的
である。The plating on the second lead frame is necessary for wire bonding in the semiconductor device manufacturing process, so it must be made of a material that is resistant to oxidation in the high temperature air during wire bonding.
Gold, silver, platinum, and rhodium plating is commonly used.
［発明が解決しようとする課題］
従来のスリッティング後にめっきを施す半導体装置用リ
ードフレームの製造方法では、一般的に最終的なリード
フレーム、即ち短冊状の状態、もしくは、幅のせまい連
続状の状態で、金、銀のめっきをするため、リードフレ
ームの製造コストに占めるめっきのコストが高くなり、
リードフレーム全体のコストを押し上げる問題がある。[Problems to be Solved by the Invention] In the conventional method for manufacturing lead frames for semiconductor devices in which plating is applied after slitting, the final lead frame is generally formed into a strip-like state or a narrow continuous form. Since gold and silver plating is applied to the lead frame, the cost of plating becomes high in the manufacturing cost of the lead frame.
There is a problem that increases the cost of the entire lead frame.
さらに、プレス又はエツチング加工後、めっきを実施す
る方法では、半導体ペレットと結線されるべき内部リー
ドが変形しやすく、リードフレームの製造歩留りを低下
させるという間超がある。Furthermore, in the method of plating after pressing or etching, the internal leads to be connected to the semiconductor pellet are easily deformed, which lowers the manufacturing yield of the lead frame.
また、銅めっきを施した材料（例えば、神戸製鋼■のＤ
ＫＬＦ材）を用いて、プレス加工又はエツチング加工の
みでリードフレームを製造する方法もある。しかし、銅
めっきは酸化されやすいため、半導体装置の製造工程、
特にワイヤボンディングにおいて、不具合が発生しやす
い。従って、上記銅めっき済材料を使用する場合には、
リードフレームの製造工程及び半導体装置の製造工程の
全般に渡って、酸素フリーになるように製造雰囲気を制
御しなければならない。また酸素フリーとなるように設
備の改善が必要となる。In addition, copper-plated materials (for example, Kobe Steel's D
There is also a method of manufacturing a lead frame using only press processing or etching processing using KLF material. However, copper plating is easily oxidized, so it
Problems are particularly likely to occur in wire bonding. Therefore, when using the copper-plated materials mentioned above,
The manufacturing atmosphere must be controlled to be oxygen-free throughout the lead frame manufacturing process and the semiconductor device manufacturing process. Additionally, it is necessary to improve the equipment so that it is oxygen-free.
本発明の目的は、圧延工程で広幅の素材に貴金属のめっ
きを施すことにより、従来の問題点を解消した半導体装
置用リードフレームの製造方法を提供することにある。An object of the present invention is to provide a method for manufacturing a lead frame for a semiconductor device that eliminates the conventional problems by plating a wide material with precious metal in a rolling process.
［課題を解決するための手段］
前記目的を達成するため、本発明に係る半導体装置用リ
ードフレームの製造方法においては、鋳造工程と、圧延
工程と、めっき工程と、スリッティング工程と、リード
フレーム加工工程とを有する半導体装置用リードフレー
ムの製造方法であって、
鋳造工程は、広幅の素材に鋳造処理を行うものであり、
圧延工程は、鋳造処理された広幅の素材に圧延処理を行
うものであり、
めっき工程は、圧延処理の途中又は処理終了後に前記広
幅の素材に、金、銀等の貴金属めっき処理を行うもので
あり、
スリッティング工程は、めっき処理された広幅の素材か
ら細幅のリードフレーム素材をスリッティング加工する
ものであり、
リードフレーム加工工程は、前記リードフレーム素材を
リードフレームとして成形加工するものである。[Means for Solving the Problem] In order to achieve the above object, the method for manufacturing a lead frame for a semiconductor device according to the present invention includes a casting process, a rolling process, a plating process, a slitting process, and a lead frame manufacturing method. A method for manufacturing a lead frame for a semiconductor device, which includes a processing step, in which the casting step performs a casting process on a wide material, and the rolling process performs a rolling process on the cast wide material. In the plating process, the wide material is plated with precious metals such as gold or silver during or after the rolling process, and in the slitting process, the plated wide material is divided into narrow widths. The lead frame material is subjected to slitting processing, and the lead frame processing step is to form the lead frame material into a lead frame.
［作用］
本発明では第１図に示すようにスリッティング前の圧延
工程中に、広幅の素材のままで、金、銀等の貴金属めっ
きを施し、その後に、めっき済の素材を、プレス加工又
はエツチング加工のみ実施してリードフレームとして成
形するものである。[Function] In the present invention, as shown in Fig. 1, during the rolling process before slitting, the wide material is plated with precious metals such as gold or silver, and then the plated material is pressed. Alternatively, only etching may be performed to form a lead frame.
したがって、プレス又はエツチング加工後に、めっきを
実施しないため、リードフレームのリード変形を阻止す
ることが可能となる。Therefore, since plating is not performed after pressing or etching, deformation of the leads of the lead frame can be prevented.
また、金、銀等の貴金属をめっきするため、その後の半
導体装置の製造工程で酸素フリーのような雰囲気の制御
等も不要となり、従来の半導体装置の製造工程、製造装
置で生産が可能となる。In addition, since precious metals such as gold and silver are plated, there is no need to control the atmosphere such as oxygen-free in the subsequent semiconductor device manufacturing process, making it possible to produce with conventional semiconductor device manufacturing processes and manufacturing equipment. .
［実施例］ 以下、本発明の一実施例を図により説明する。[Example] Hereinafter, one embodiment of the present invention will be described with reference to the drawings.
第１図は本発明の一実施例に係る製造工程を示す工程線
図である。FIG. 1 is a process diagram showing a manufacturing process according to an embodiment of the present invention.
図において、本発明に係る製造工程は、鋳造工程Ｓ１．
圧延工程Ｓ２＋ めっき工程Ｓ６．スリッティング工程
Ｓ３．リードフレーふ加工工程Ｓ４からなる。In the figure, the manufacturing process according to the present invention is a casting process S1.
Rolling process S2+ Plating process S6. Slitting process S3. It consists of a lead flake processing step S4.
鋳造工程Ｓ１では、広幅の素材としての電気銅に不純物
を添加し、溶解鋳造の処理を行う。In the casting step S1, impurities are added to electrolytic copper as a wide material, and melt casting is performed.
圧延工程Ｓ２では、鋳造工程Ｓ１を経た銅合金に、熱間
圧延７面前、粗圧延、冷間圧延、焼鈍等の処理を行い、
その後、硫酸−過酸化水素系のエツチング液で酸洗する
。In the rolling process S2, the copper alloy that has undergone the casting process S1 is subjected to treatments such as hot rolling, rough rolling, cold rolling, and annealing.
Thereafter, it is pickled with a sulfuric acid-hydrogen peroxide etching solution.
その酸洗した後、めっき工程Ｓ６を行う。すなわち、め
っき工程Ｓ６では、酸洗した広幅の銅合金素材のままで
、市販の低シアン銀めっき液を用い、その両面に電解銀
めっき処理を行う。ここに、めっきの純度は、半導体装
置製造工程のワイヤボンディング性を考慮して９９．９
９％とした。また、めっき膜厚は、仕上げ圧延での損失
等を考慮して、３ｐｍ以上とした。After the pickling, a plating step S6 is performed. That is, in the plating step S6, electrolytic silver plating is performed on both sides of the pickled wide copper alloy material using a commercially available low cyan silver plating solution. Here, the purity of the plating is 99.9 in consideration of wire bonding properties in the semiconductor device manufacturing process.
It was set at 9%. In addition, the plating film thickness was set to 3 pm or more in consideration of losses during finish rolling.
さらに、めっき済の素材に仕上げ圧延処理を行い、０．
２５ｍｍの厚さにした。このときの表面粗度は０．４μ
ｍ ｍａｘで、銀めっきの厚さは２．５ｐｍ以上であっ
た。Furthermore, the plated material is subjected to finish rolling treatment to achieve a 0.
The thickness was set to 25 mm. The surface roughness at this time is 0.4μ
m max, the thickness of the silver plating was 2.5 pm or more.
スリッティング工程Ｓ３では、仕上げ圧延処理を施した
めっき済の素材からリードフレームとしての細幅をもつ
リードフレーム素材をスリッティング加工する。In the slitting step S3, a lead frame material having a narrow width as a lead frame is slit from a plated material that has been subjected to finish rolling.
最後に、リードフレーム加工工程Ｓ４では、スリッティ
ング加工されたリードフレーム素材にプレス加工を行い
、第２図に示す最終的な形状のリードフレームを成形す
る。第２図に示すリードフレームは、内部リード２．ア
イランド３．外部り−ド４．タイバー５．リードフレー
ム枠６．送りビン孔７を有している。Finally, in the lead frame processing step S4, the slitted lead frame material is pressed to form a lead frame having the final shape shown in FIG. The lead frame shown in FIG. 2 has internal leads 2. Island 3. External road 4. Tie bar5. Lead frame frame6. It has a feed bottle hole 7.
第３図は本発明に係るリードフレームの断面図、第５図
は第４図に基づ〈従来の製造方法で製造したリードフレ
ームの断面図である。第３図、第５図において、ｌ、１
′はめっき層、２は内部リード。FIG. 3 is a sectional view of a lead frame according to the present invention, and FIG. 5 is a sectional view of a lead frame manufactured by a conventional manufacturing method based on FIG. 4. In Figures 3 and 5, l, 1
′ is the plating layer, 2 is the internal lead.
３はアイランドである。3 is an island.
本発明に係る製造方法により製造したリードフレーム（
第３図）は、従来方法により製造したリードフレーム（
第５図）と比較して、電気特性、信頼性の点で同等以上
であった。Lead frame manufactured by the manufacturing method according to the present invention (
Figure 3) is a lead frame (Fig. 3) manufactured by the conventional method.
(Fig. 5), it was equivalent or better in terms of electrical characteristics and reliability.
本実施例では、素材として銅合金を用いたが、鉄、鉄−
ニッケル合金を用いてもよい。また、めっき材質として
銀を用いたが、金、白金、ロジウムを用いても効果に変
わりはない。In this example, copper alloy was used as the material, but iron,
A nickel alloy may also be used. In addition, although silver was used as the plating material, the effect remains the same even if gold, platinum, or rhodium is used.
さらに、酸洗−仕上げ圧延後に、全面めっきを施しても
同様な効果を得られることは言うまでもない。Furthermore, it goes without saying that the same effect can be obtained even if the entire surface is plated after pickling and finish rolling.
［発明の効果］
以上説明したように本発明は、圧延工程中で広幅の素材
に全面の金、銀等のめっきを施すため、めっき加工費を
３０％低下させることができる。[Effects of the Invention] As explained above, in the present invention, the entire surface of a wide material is plated with gold, silver, etc. during the rolling process, so that the plating cost can be reduced by 30%.
さらに、プレス又はエツチング加工後に、めっきを実施
しないため、内部リードの変形を防止できる。Furthermore, since plating is not performed after pressing or etching, deformation of the internal leads can be prevented.
また、めっき後、仕上げ圧延をすることにより、めっき
膜質が緻密になり、その後のワイヤボンディング工程に
おけるボンディング不良率が従来方法に比し、１０％低
下することができる。Further, by performing finish rolling after plating, the quality of the plating film becomes dense, and the bonding failure rate in the subsequent wire bonding process can be reduced by 10% compared to the conventional method.
さらに、めっき層として、金、銀等の貴金属を用いるた
め、半導体装置の製造中に酸化等が起こらないため、従
来の製造プロセス、製造装置がそのまま使用できる効果
がある。Furthermore, since noble metals such as gold and silver are used as the plating layer, oxidation and the like do not occur during the manufacture of the semiconductor device, which has the advantage that conventional manufacturing processes and manufacturing equipment can be used as is.
第１図は本発明の一実施例を示す工程線図、第２図は本
発明に係る半導体装置用リードフレームを示す部分図、
第３図は第２図のＡ−Ａ ′線断面図、第４図は従来方
法を示す工程線図、第５図は従来方法によるリードフレ
ームを示す断面図である。
ｌ、１′・・・めっき層 ２・・内部リード３
・アイランド ４・・・外部リード５・・・タ
イバー
６・・・リードフレーム枠
７・・・送りビン孔FIG. 1 is a process diagram showing an embodiment of the present invention, FIG. 2 is a partial diagram showing a lead frame for a semiconductor device according to the present invention,
3 is a sectional view taken along the line A-A' in FIG. 2, FIG. 4 is a process diagram showing the conventional method, and FIG. 5 is a sectional view showing a lead frame according to the conventional method. l, 1'... Plating layer 2... Internal lead 3
・Island 4...External lead 5...Tie bar 6...Lead frame frame 7...Feeding bottle hole
Claims (1)
ティング工程と、リードフレーム加工工程とを有する半
導体装置用リードフレームの製造方法であって、 鋳造工程は、広幅の素材に鋳造処理を行うものであり、 圧延工程は、鋳造処理された広幅の素材に圧延処理を行
うものであり、 めっき工程は、圧延処理の途中又は処理終了後に前記広
幅の素材に、金、銀等の貴金属めっき処理を行うもので
あり、 スリッティング工程は、めっき処理された広幅の素材か
ら細幅のリードフレーム素材をスリッティング加工する
ものであり、 リードフレーム加工工程は、前記リードフレーム素材を
リードフレームとして成形加工するものであることを特
徴とする半導体装置用リードフレームの製造方法。(1) A method for manufacturing a lead frame for a semiconductor device, which includes a casting process, a rolling process, a plating process, a slitting process, and a lead frame processing process, wherein the casting process involves casting a wide material. The rolling process involves rolling a cast wide material, and the plating process involves plating the wide material with precious metals such as gold or silver during or after the rolling process. The slitting process involves slitting a narrow lead frame material from a wide plated material, and the lead frame processing process involves forming the lead frame material into a lead frame. A method for manufacturing a lead frame for a semiconductor device, characterized in that the lead frame is processed.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14579290A JPH0438860A (en) | 1990-06-04 | 1990-06-04 | Manufacture method of semiconductor device lead frame |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP14579290A JPH0438860A (en) | 1990-06-04 | 1990-06-04 | Manufacture method of semiconductor device lead frame |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438860A true JPH0438860A (en) | 1992-02-10 |
Family
ID=15393268
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP14579290A Pending JPH0438860A (en) | 1990-06-04 | 1990-06-04 | Manufacture method of semiconductor device lead frame |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438860A (en) |
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291449A (en) * | 1992-04-10 | 1993-11-05 | Mitsubishi Electric Corp | Manufacture of electrode for semiconductor device |
| US8748907B2 (en) | 2012-02-03 | 2014-06-10 | Kabushiki Kaisha Toshiba | Optical coupling device |
| JP2016072578A (en) * | 2014-10-02 | 2016-05-09 | Ｓｈマテリアル株式会社 | Manufacturing method of lead frame |
| CN106514160A (en) * | 2017-01-04 | 2017-03-22 | 成都四威高科技产业园有限公司 | High-precision microwave assembly bottom face machining process |
-
1990
- 1990-06-04 JP JP14579290A patent/JPH0438860A/en active Pending
Cited By (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH05291449A (en) * | 1992-04-10 | 1993-11-05 | Mitsubishi Electric Corp | Manufacture of electrode for semiconductor device |
| US8748907B2 (en) | 2012-02-03 | 2014-06-10 | Kabushiki Kaisha Toshiba | Optical coupling device |
| JP2016072578A (en) * | 2014-10-02 | 2016-05-09 | Ｓｈマテリアル株式会社 | Manufacturing method of lead frame |
| CN106514160A (en) * | 2017-01-04 | 2017-03-22 | 成都四威高科技产业园有限公司 | High-precision microwave assembly bottom face machining process |
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