JPH0438843A - Hybrid integrated circuit device - Google Patents
Hybrid integrated circuit deviceInfo
- Publication number
- JPH0438843A JPH0438843A JP2144352A JP14435290A JPH0438843A JP H0438843 A JPH0438843 A JP H0438843A JP 2144352 A JP2144352 A JP 2144352A JP 14435290 A JP14435290 A JP 14435290A JP H0438843 A JPH0438843 A JP H0438843A
- Authority
- JP
- Japan
- Prior art keywords
- semiconductor chip
- wiring pattern
- bump
- circuit substrate
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 claims abstract description 22
- 239000011347 resin Substances 0.000 abstract description 4
- 229920005989 resin Polymers 0.000 abstract description 4
- 239000011521 glass Substances 0.000 abstract description 3
- 239000000956 alloy Substances 0.000 abstract description 2
- 229910045601 alloy Inorganic materials 0.000 abstract description 2
- 239000004033 plastic Substances 0.000 abstract description 2
- 239000000758 substrate Substances 0.000 abstract 5
- 238000009413 insulation Methods 0.000 abstract 2
- 238000000059 patterning Methods 0.000 abstract 1
- 230000002093 peripheral effect Effects 0.000 abstract 1
- 238000007789 sealing Methods 0.000 abstract 1
- 230000000694 effects Effects 0.000 description 2
- 230000002542 deteriorative effect Effects 0.000 description 1
- 238000000034 method Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 238000003825 pressing Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73201—Location after the connecting process on the same surface
- H01L2224/73203—Bump and layer connectors
- H01L2224/73204—Bump and layer connectors the bump connector being embedded into the layer connector
Landscapes
- Wire Bonding (AREA)
Abstract
Description
【発明の詳細な説明】 ［発明の目的］ （産業上の利用分野） 本発明は、混成集積回路装置に関するものである。[Detailed description of the invention] [Purpose of the invention] (Industrial application field) The present invention relates to a hybrid integrated circuit device.
（従来の技術）
従来の混成集積回路装置は一般に第３図に示すような構
造となっている。すなわち、半導体チップ３１の電極パ
ッド３２部に、バンプ３３（突起電極）を形成し、その
バンプ３３と回路基板３４の配線パターン３５とを位置
合わせし、前記半導体チ・ツブ３１の形成していない面
に圧力を加え、このバンプ３３を機械的に塑性変形させ
て配線パターン３５に実装し、回路基板３４と半導体チ
ップ３１とのすき間に樹脂３６を充填し、混成集積回路
装置を形成する。(Prior Art) A conventional hybrid integrated circuit device generally has a structure as shown in FIG. That is, bumps 33 (protruding electrodes) are formed on the electrode pads 32 of the semiconductor chip 31, and the bumps 33 and the wiring patterns 35 of the circuit board 34 are aligned, and the portions of the semiconductor chip 31 that are not formed are aligned. Pressure is applied to the surface to mechanically plastically deform the bumps 33 and mount them on the wiring pattern 35, and the gap between the circuit board 34 and the semiconductor chip 31 is filled with resin 36 to form a hybrid integrated circuit device.
ここで、現在半導体チップなどの高集積化・高機能化に
伴い、半導体チップ上の電極パッド数が増大する一方、
電極パッドの面積が小さく、電極ハツトの間隔が狭くな
る傾向にある。このような傾向に対処して回路基板上の
配線パターンの縮小化及びピッチの狭小化かなされてい
る。半導体チップを回路基板に実装する場合、配線パタ
ーンのピッチが狭いので、加圧した時、つぶれて広がっ
たバンプ同志が接触してしまい、短絡を起こす。Currently, as semiconductor chips become more highly integrated and highly functional, the number of electrode pads on semiconductor chips increases.
The area of the electrode pad is small, and the spacing between the electrode hats tends to be narrow. In response to this trend, wiring patterns on circuit boards have been reduced in size and pitch has been reduced. When a semiconductor chip is mounted on a circuit board, the pitch of the wiring pattern is narrow, so when pressure is applied, the bumps that have collapsed and expanded come into contact with each other, causing a short circuit.
（本発明か解決しようとする問題点）
従来は、半導体チップの高集積化・高機能化により、バ
ンプの間隔が狭ピッチになる傾向にあるため、実装する
にあたって、加圧をする際、バンプがつぶれて広がって
しまい、隣接するバンプ同士が接触し、電気的短絡が発
生し、信頼性が劣化していた。(Problem to be solved by the present invention) Conventionally, as semiconductor chips become highly integrated and highly functional, the pitch between bumps tends to become narrower. The bumps would collapse and spread, causing adjacent bumps to come into contact with each other, causing electrical shorts and deteriorating reliability.
本発明は、上記のような従来技術の欠点を除去し、バン
プの間隔が狭ピッチの場合において、実装する際、バン
プ同志が短絡することがなく、信頼性か向上することを
目的とする混成集積回路装置を提供するものである。The present invention eliminates the drawbacks of the prior art as described above, and aims to improve reliability by preventing short-circuits between bumps during mounting when the bumps are narrowly spaced. An integrated circuit device is provided.
［発明の構成］
（課題を解決するための手段）
上記目的を達成するために、本発明においては、上面に
配線パターンを有する回路基板と、前記回路基板上に配
設され、かつ、前記配線パターンと接続するバンプを有
する半導体チップと、前記配線パターンと前記バンプと
の接続部の周辺を覆うように形成する絶縁膜とを育する
ことを特徴とする混成集積回路装置を提供し、さらに、
前記絶縁膜の膜厚は、前記バンプの高さの１部２倍以上
１倍以下であることを特徴とする混成集積回路装置を提
供する。[Structure of the Invention] (Means for Solving the Problems) In order to achieve the above object, the present invention provides a circuit board having a wiring pattern on an upper surface, and a circuit board disposed on the circuit board and having a wiring pattern on the top surface. Provided is a hybrid integrated circuit device characterized by growing a semiconductor chip having bumps connected to a pattern, and an insulating film formed to cover the periphery of a connecting portion between the wiring pattern and the bump, and further comprising:
The present invention provides a hybrid integrated circuit device characterized in that the thickness of the insulating film is 1 part 2 or more and 1 times or less the height of the bump.
（作 用）
このように構成されたものにおいては半導体チップのバ
ンプと配線パターンとの接続部の周辺に絶縁膜を形成し
ているため、半導体チップを回路基板に実装する際、隣
接するバンプ同志の接触を防ぐことができ、電気的短絡
を防止できるので信頼性が向上する。(Function) In a device configured in this way, an insulating film is formed around the connection between the bumps of the semiconductor chip and the wiring pattern, so when the semiconductor chip is mounted on a circuit board, adjacent bumps may Since it is possible to prevent electrical short-circuits, reliability is improved.
（実施例） 第１図および第２図を参照して本実施例を説明する。(Example) This embodiment will be described with reference to FIGS. 1 and 2.
第１図は、本実施例に係る混成集積回路装置の回路基板
の要部構成を示す平面図、第２図は、本実施例の混成集
積回路装置の断面図である。FIG. 1 is a plan view showing the main part configuration of a circuit board of a hybrid integrated circuit device according to this embodiment, and FIG. 2 is a sectional view of the hybrid integrated circuit device according to this embodiment.
半導体チップ１の表面には、例えばＡＪ膜からド′
成る電極パラｙ２が設けられ、そのパッド上にＡｕとＩ
ｎの合金から成るバンプ３が形成されている。一方、ガ
ラス等の回路基板４上に配線パターンが形成されており
、この回路基板４上に絶縁膜としてＰＳＧＳｅＯ２ＯＧ
（Ｓｐｉｎ Ｏｎ Ｇｌａｓｓ）法により形成する。On the surface of the semiconductor chip 1, an electrode pad y2 made of, for example, an AJ film is provided.
A bump 3 made of an alloy of n is formed. On the other hand, a wiring pattern is formed on a circuit board 4 made of glass or the like, and PSGSeO2OG is formed as an insulating film on this circuit board 4.
(Spin On Glass) method.
このＰＳＧＳｅＯ２厚は、例えば、バンプ３の高さの１
部２倍とする。このＰＳＧＳｅＯ２バンプ３と回路基板
４上の配線パターン５とヲ接続するためのコンタクトホ
ール７を形成し、このコンタクトホール７の周辺部のＰ
ＳＧＳｅＯ２しバターニングする。次に、このコンタク
トホール７部に前記バンプ３の先端部を位置合わせし、
半導体チップ１の裏面を加圧することにより、バンプ３
を塑性変形させ、前記回路基板４の配線パターン５と半
導体チップ１の電極バットとを接続させ、その後、前記
回路基板４と半導体チップ１との間に樹脂８を注入し、
封止する。この実施例では、バンプと接続する回路基板
の配線パターンの周辺部に絶縁膜を形成しているため、
バンプの塑性変形による広がりが抑制され隣接するバン
プの接触かなく、電気的短絡が起きない。This PSGSeO2 thickness is, for example, 1 of the height of the bump 3.
The amount will be doubled. A contact hole 7 is formed to connect this PSGSeO2 bump 3 to the wiring pattern 5 on the circuit board 4, and the P
SGSeO2 and buttering. Next, align the tip of the bump 3 with this contact hole 7,
By applying pressure to the back surface of the semiconductor chip 1, the bumps 3
is plastically deformed to connect the wiring pattern 5 of the circuit board 4 and the electrode butt of the semiconductor chip 1, and then inject a resin 8 between the circuit board 4 and the semiconductor chip 1,
Seal. In this example, an insulating film is formed around the wiring pattern of the circuit board that connects to the bump.
Spreading of the bumps due to plastic deformation is suppressed, and adjacent bumps do not come into contact with each other, preventing electrical short circuits.
尚、上記では、絶縁膜にＰＳＧ膜を用いたが、Ｓ ｉｏ
ｘ膜等の無機絶縁膜を用いてもよい。また、ポリイミド
膜等の有機絶縁膜を用いてもよい。Note that in the above, a PSG film was used as the insulating film, but S io
An inorganic insulating film such as an x film may also be used. Alternatively, an organic insulating film such as a polyimide film may be used.
また、前記絶縁膜の膜厚は、薄すぎるとバンプの広がり
を阻止する効果が弱く、隣接するバンプ同志が接触する
恐れがあり、厚すぎると、バンプと配線パターンとの接
触が悪くなる恐れがあり、そのため、絶縁膜の膜厚をバ
ンプの高さの１７２倍以上１倍以下にするのが好ましい
。Furthermore, if the thickness of the insulating film is too thin, the effect of preventing the bumps from spreading will be weak, and adjacent bumps may come into contact with each other, and if the insulating film is too thick, the contact between the bumps and the wiring pattern may deteriorate. Therefore, it is preferable that the thickness of the insulating film is 172 times or more and 1 time or less the height of the bump.
［発明の効果コ
以上、述べてきたように、本発明によれば半導体チップ
を実装する時に発生するバンプの広がりによる隣接する
バンプとの接触を防止することができ、電気的短絡を防
止できるので、信頼性が向上する。[Effects of the Invention] As described above, according to the present invention, it is possible to prevent contact with adjacent bumps due to the spread of bumps that occurs when mounting a semiconductor chip, and it is possible to prevent electrical short circuits. , reliability is improved.
さらに、多ピン・狭ピッチの混成集積回路装置が可能と
なる。Furthermore, a hybrid integrated circuit device with a large number of pins and a narrow pitch becomes possible.
【図面の簡単な説明】
第１図は、本発明の混成集積回路装置の回路基板部分の
平面図、第２図は本発明の混成集積回路装置の断面図、
第３図は、従来の混成集積回路装置の断面図である。
１・・・半導体チップ
２・・電極バッ〆
３・・・バンプ
４・・・回路基板
５・・・配線パターン
６・・ＰＳＧ膜
７・・コンタクトホール
８・・・樹脂BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a plan view of a circuit board portion of a hybrid integrated circuit device of the present invention, and FIG. 2 is a sectional view of the hybrid integrated circuit device of the present invention.
FIG. 3 is a sectional view of a conventional hybrid integrated circuit device. 1... Semiconductor chip 2... Electrode back 3... Bump 4... Circuit board 5... Wiring pattern 6... PSG film 7... Contact hole 8... Resin
Claims (1)
基板上に配設され、かつ、前記配線パターンと接続する
バンプを有する半導体チップと、前記配線パターンと前
記バンプとの接続部の周辺を覆うように形成する絶縁膜
とを有することを特徴とする混成集積回路装置。 ２、前記絶縁膜の膜厚は、前記バンプの高さの１／２倍
以上１倍以下であることを特徴とする特許請求の範囲第
１項記載の混成集積回路装置。[Claims] 1. A circuit board having a wiring pattern on its upper surface, a semiconductor chip disposed on the circuit board and having bumps connected to the wiring pattern, and a combination of the wiring pattern and the bumps. 1. A hybrid integrated circuit device comprising: an insulating film formed to cover a periphery of a connection portion. 2. The hybrid integrated circuit device according to claim 1, wherein the thickness of the insulating film is 1/2 to 1 times the height of the bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2144352A JPH0438843A (en) | 1990-06-04 | 1990-06-04 | Hybrid integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP2144352A JPH0438843A (en) | 1990-06-04 | 1990-06-04 | Hybrid integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438843A true JPH0438843A (en) | 1992-02-10 |
Family
ID=15360110
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP2144352A Pending JPH0438843A (en) | 1990-06-04 | 1990-06-04 | Hybrid integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438843A (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005228990A (en) * | 2004-02-13 | 2005-08-25 | Ricoh Microelectronics Co Ltd | Member for circuit board manufacturing method, electronic component fixing method using relay board, relay board manufacturing method, and board equipped with the relay board |
-
1990
- 1990-06-04 JP JP2144352A patent/JPH0438843A/en active Pending
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP2005228990A (en) * | 2004-02-13 | 2005-08-25 | Ricoh Microelectronics Co Ltd | Member for circuit board manufacturing method, electronic component fixing method using relay board, relay board manufacturing method, and board equipped with the relay board |
| JP4503309B2 (en) * | 2004-02-13 | 2010-07-14 | リコーマイクロエレクトロニクス株式会社 | Electronic component fixing method using relay board, relay board manufacturing method, and component mounting board provided with relay board |
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