JPH0438524Y2 - - Google Patents
Info
- Publication number
- JPH0438524Y2 JPH0438524Y2 JP1986195595U JP19559586U JPH0438524Y2 JP H0438524 Y2 JPH0438524 Y2 JP H0438524Y2 JP 1986195595 U JP1986195595 U JP 1986195595U JP 19559586 U JP19559586 U JP 19559586U JP H0438524 Y2 JPH0438524 Y2 JP H0438524Y2
- Authority
- JP
- Japan
- Prior art keywords
- terrace
- electrode metal
- solder
- metal plate
- semiconductor device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 21
- 229910000679 solder Inorganic materials 0.000 claims description 18
- 239000002184 metal Substances 0.000 claims description 17
- 239000000758 substrate Substances 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 9
- 238000000576 coating method Methods 0.000 claims description 9
- 239000000463 material Substances 0.000 claims description 5
- 229920001721 polyimide Polymers 0.000 claims description 2
- 239000009719 polyimide resin Substances 0.000 claims description 2
- 238000010586 diagram Methods 0.000 description 5
- 230000008646 thermal stress Effects 0.000 description 2
- 238000007792 addition Methods 0.000 description 1
- 238000006243 chemical reaction Methods 0.000 description 1
- 239000002131 composite material Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/36—Structure, shape, material or disposition of the strap connectors prior to the connecting process
- H01L24/37—Structure, shape, material or disposition of the strap connectors prior to the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L24/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L24/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L24/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L24/84—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a strap connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/0212—Auxiliary members for bonding areas, e.g. spacers
- H01L2224/02122—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body
- H01L2224/02163—Auxiliary members for bonding areas, e.g. spacers being formed on the semiconductor or solid-state body on the bonding area
- H01L2224/02165—Reinforcing structures
- H01L2224/02166—Collar structures
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/26—Layer connectors, e.g. plate connectors, solder or adhesive layers; Manufacturing methods related thereto
- H01L2224/31—Structure, shape, material or disposition of the layer connectors after the connecting process
- H01L2224/32—Structure, shape, material or disposition of the layer connectors after the connecting process of an individual layer connector
- H01L2224/321—Disposition
- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/32221—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/32245—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4007—Shape of bonding interfaces, e.g. interlocking features
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/4005—Shape
- H01L2224/4009—Loop shape
- H01L2224/40095—Kinked
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/34—Strap connectors, e.g. copper straps for grounding power devices; Manufacturing methods related thereto
- H01L2224/39—Structure, shape, material or disposition of the strap connectors after the connecting process
- H01L2224/40—Structure, shape, material or disposition of the strap connectors after the connecting process of an individual strap connector
- H01L2224/401—Disposition
- H01L2224/40151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/40221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/40245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/40247—Connecting the strap to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/73—Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
- H01L2224/732—Location after the connecting process
- H01L2224/73251—Location after the connecting process on different surfaces
- H01L2224/73263—Layer and strap connectors
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Wire Bonding (AREA)
Description
【考案の詳細な説明】
本考案は、半導体装置の構造に関するものであ
る。従来のこの種装置は、半導体基体の両主表面
に夫々電極金属板を、半田を介して接続してお
り、その構造を第1図の断面構造図に示す。電極
金属板1上に、半導体基体2を半田3を介して接
続し、半導体基体2のPN接合面に近い側の主表
面には、電極金属板4を半田3を介して接続して
いるが、電極金属板4の自重と半田3の表面張力
等により、電極金属板4のテラス側面部4aに半
田3が多量に付いて、半導体基体2の主表面と電
極金属板4のテラス平たん部4b間の半田3は、
極端に厚さが薄くなる欠点があつた。
る。従来のこの種装置は、半導体基体の両主表面
に夫々電極金属板を、半田を介して接続してお
り、その構造を第1図の断面構造図に示す。電極
金属板1上に、半導体基体2を半田3を介して接
続し、半導体基体2のPN接合面に近い側の主表
面には、電極金属板4を半田3を介して接続して
いるが、電極金属板4の自重と半田3の表面張力
等により、電極金属板4のテラス側面部4aに半
田3が多量に付いて、半導体基体2の主表面と電
極金属板4のテラス平たん部4b間の半田3は、
極端に厚さが薄くなる欠点があつた。
本考案は、前述の欠点を解消したもので、単体
又は複合型の半導体基体に於いて、信頼性に富み
生産性の良い半導体装置を提供することを目的と
する。第2図は本考案の実施例を示す断面構造図
であつて、1は電極金属板、2は半導体基体、3
は半田、4は他の電極金属板、4aはテラス側面
部、4bはテラス平たん部、5はコーテイング材
による塗布部分を示す。電極金属板4は第3図に
示す様に、テラス側面部4aに半田漏れ性の良く
ないコーテイング材(例えばポリイミド樹脂)の
塗布部分5がある。塗布部分5は電極金属板4を
加工する段階で、前もつて所定位置(形状、塗布
量は問わない)に塗布することにより、生産性が
良く、安価で製作することが出来る。本装置を組
み立てるには、電極金属板1上に、半田3、半導
体基体2、半田3及び電極金属板4の順にセツト
し、加熱炉(図示していない)で半田固着を行な
う。組み立てられた半導体装置は、テラス側面部
4aにコーテイング材による塗布部分5があるた
め、半田3がテラス側面部4aに付くことなく、
半導体基体2の主表面とテラス平たん部4b間の
半田厚さを一定に保つことが出来る。半田厚さは
半田3の供給量によつて可変することができ、電
気的、熱的ストレスに強い厚さ(例えば50μ)に
することが出来る。
又は複合型の半導体基体に於いて、信頼性に富み
生産性の良い半導体装置を提供することを目的と
する。第2図は本考案の実施例を示す断面構造図
であつて、1は電極金属板、2は半導体基体、3
は半田、4は他の電極金属板、4aはテラス側面
部、4bはテラス平たん部、5はコーテイング材
による塗布部分を示す。電極金属板4は第3図に
示す様に、テラス側面部4aに半田漏れ性の良く
ないコーテイング材(例えばポリイミド樹脂)の
塗布部分5がある。塗布部分5は電極金属板4を
加工する段階で、前もつて所定位置(形状、塗布
量は問わない)に塗布することにより、生産性が
良く、安価で製作することが出来る。本装置を組
み立てるには、電極金属板1上に、半田3、半導
体基体2、半田3及び電極金属板4の順にセツト
し、加熱炉(図示していない)で半田固着を行な
う。組み立てられた半導体装置は、テラス側面部
4aにコーテイング材による塗布部分5があるた
め、半田3がテラス側面部4aに付くことなく、
半導体基体2の主表面とテラス平たん部4b間の
半田厚さを一定に保つことが出来る。半田厚さは
半田3の供給量によつて可変することができ、電
気的、熱的ストレスに強い厚さ(例えば50μ)に
することが出来る。
その他、各部の変形、変換、付加等は本願に含
まれる。
まれる。
以上のごとく、本考案の半導体装置は、組み立
てが容易で電気的、熱的ストレスに強く、信頼性
の高い半導体装置を提供するものである。実用に
供し、産業上の効果は大なるものである。
てが容易で電気的、熱的ストレスに強く、信頼性
の高い半導体装置を提供するものである。実用に
供し、産業上の効果は大なるものである。
第1図は従来の半導体装置の断面構造図、第2
図は本考案の実施例を示す断面構造図、第3図は
本考案の半導体装置に用いる電極金属板の構造例
図、であり、1……電極金属板、2……半導体基
体、3……半田、4……電極金属板、4a……テ
ラス側面部、4b……テラス平たん部、5……コ
ーテイング材による塗布部分である。
図は本考案の実施例を示す断面構造図、第3図は
本考案の半導体装置に用いる電極金属板の構造例
図、であり、1……電極金属板、2……半導体基
体、3……半田、4……電極金属板、4a……テ
ラス側面部、4b……テラス平たん部、5……コ
ーテイング材による塗布部分である。
Claims (1)
- 【実用新案登録請求の範囲】 (1) 2つの主表面を有する半導体基体の両表面
に、それぞれ電極金属板1及び4を配設した半
導体装置において、半導体基体のPN接合面に
近い側の主表面に配設する電極金属板4にはテ
ラス側面部4a及びテラス平たん部4bから成
るテラスを設け、該テラス側面部4aに半田漏
れ性の良くないコーテイング材の塗布部分を設
け、半導体基体の主表面と該テラス平たん部4
b間の半田厚さをほぼ均一にすることを特徴と
する半導体装置。 (2) 前記、コーテイング材にポリイミド系樹脂を
用いた事を特徴とする実用新案登録請求の範囲
第(1)項記載の半導体装置。
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986195595U JPH0438524Y2 (ja) | 1986-12-19 | 1986-12-19 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP1986195595U JPH0438524Y2 (ja) | 1986-12-19 | 1986-12-19 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS63100847U JPS63100847U (ja) | 1988-06-30 |
JPH0438524Y2 true JPH0438524Y2 (ja) | 1992-09-09 |
Family
ID=31153625
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP1986195595U Expired JPH0438524Y2 (ja) | 1986-12-19 | 1986-12-19 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPH0438524Y2 (ja) |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108206163A (zh) * | 2016-12-19 | 2018-06-26 | 安世有限公司 | Ic封装件中夹布置的半导体器件和方法 |
Families Citing this family (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5001545A (en) * | 1988-09-09 | 1991-03-19 | Motorola, Inc. | Formed top contact for non-flat semiconductor devices |
US4935803A (en) * | 1988-09-09 | 1990-06-19 | Motorola, Inc. | Self-centering electrode for power devices |
JP4645276B2 (ja) * | 2005-04-12 | 2011-03-09 | 富士電機システムズ株式会社 | 半導体装置 |
JP6479036B2 (ja) * | 2014-10-30 | 2019-03-06 | 三菱電機株式会社 | 半導体装置及びその製造方法 |
Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5313877A (en) * | 1976-07-23 | 1978-02-07 | Hitachi Ltd | Semiconductor device |
-
1986
- 1986-12-19 JP JP1986195595U patent/JPH0438524Y2/ja not_active Expired
Patent Citations (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5313877A (en) * | 1976-07-23 | 1978-02-07 | Hitachi Ltd | Semiconductor device |
Cited By (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
CN108206163A (zh) * | 2016-12-19 | 2018-06-26 | 安世有限公司 | Ic封装件中夹布置的半导体器件和方法 |
Also Published As
Publication number | Publication date |
---|---|
JPS63100847U (ja) | 1988-06-30 |
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