JPH0438189U - - Google Patents
Info
- Publication number
- JPH0438189U JPH0438189U JP7948490U JP7948490U JPH0438189U JP H0438189 U JPH0438189 U JP H0438189U JP 7948490 U JP7948490 U JP 7948490U JP 7948490 U JP7948490 U JP 7948490U JP H0438189 U JPH0438189 U JP H0438189U
- Authority
- JP
- Japan
- Prior art keywords
- amplifier
- switch circuit
- phase shifter
- signals
- television receiver
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- NJPPVKZQTLUDBO-UHFFFAOYSA-N novaluron Chemical compound C1=C(Cl)C(OC(F)(F)C(OC(F)(F)F)F)=CC=C1NC(=O)NC(=O)C1=C(F)C=CC=C1F NJPPVKZQTLUDBO-UHFFFAOYSA-N 0.000 claims description 5
- 230000003321 amplification Effects 0.000 claims 1
- 239000003990 capacitor Substances 0.000 claims 1
- 230000003111 delayed effect Effects 0.000 claims 1
- 238000003199 nucleic acid amplification method Methods 0.000 claims 1
- 238000010586 diagram Methods 0.000 description 2
Landscapes
- Picture Signal Circuits (AREA)
- Processing Of Color Television Signals (AREA)
Description
第１図は本考案の一実施例を示すペデスタルレ
ベルシフト回路のブロツク図、第２図は同第１図
の各部動作波形図である。
１はペデスタルレベルをシフトするスイツチ回
路、２は輝度信号等ペデスタルレベル以上の信号
成分用増幅器、３はクランプパルスの移相器であ
る。
FIG. 1 is a block diagram of a pedestal level shift circuit showing an embodiment of the present invention, and FIG. 2 is a waveform diagram of the operation of each part of FIG. 1 is a switch circuit for shifting the pedestal level, 2 is an amplifier for signal components higher than the pedestal level such as a luminance signal, and 3 is a phase shifter for clamp pulses.
Claims (1)
いて、直流分の重畳した映像信号等をスイツチ回
路の一方の入力端子に基準バイアス電圧を接続し
た同スイツチ回路の他方の入力端子に接続し、同
スイツチ回路出力をコンデンサを介してペデスタ
ルレベル以下のダイナミツクレンジを考慮してい
ない輝度信号用増幅器に接続し、また、クランプ
パルスを移相器に接続し、同移相器出力の遅相ク
ランプパルスを前記スイツチ回路の制御端子と輝
度信号用前記増幅器とに接続してなる同増幅器を
クロマ信号等ペデスタルレベルを中心とする上下
振幅信号用に適用可能とすることを特徴とする受
像機。 In a video signal amplification circuit such as a color television receiver, a video signal with a superimposed DC component is connected to one input terminal of a switch circuit with a reference bias voltage connected to the other input terminal of the same switch circuit. The output is connected via a capacitor to a luminance signal amplifier that does not take into account the dynamic range below the pedestal level, and the clamp pulse is connected to a phase shifter, and the delayed clamp pulse output from the phase shifter is A television receiver characterized in that the amplifier, which is connected to a control terminal of a switch circuit and the amplifier for luminance signals, can be applied to upper and lower amplitude signals centering on a pedestal level, such as chroma signals.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7948490U JPH0438189U (en) | 1990-07-25 | 1990-07-25 |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP7948490U JPH0438189U (en) | 1990-07-25 | 1990-07-25 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH0438189U true JPH0438189U (en) | 1992-03-31 |
Family
ID=31623687
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP7948490U Pending JPH0438189U (en) | 1990-07-25 | 1990-07-25 |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH0438189U (en) |
-
1990
- 1990-07-25 JP JP7948490U patent/JPH0438189U/ja active Pending
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