JPH0471087U

JPH0471087U -

Info

Publication number: JPH0471087U
Application number: JP11460190U
Authority: JP
Priority date: 1990-10-31
Filing date: 1990-10-31
Publication date: 1992-06-23

Description

[Brief explanation of the drawing]

第１図は本考案の一実施例の回路図、第２図は
従来技術のブロツク図、第３図は従来技術の回路
図である。１……第１の平衡変調回路、２……第２の平衡
変調回路、７……端子。 FIG. 1 is a circuit diagram of an embodiment of the present invention, FIG. 2 is a block diagram of the prior art, and FIG. 3 is a circuit diagram of the prior art. 1...First balanced modulation circuit, 2...Second balanced modulation circuit, 7...Terminal.

Claims

[Claims for Utility Model Registration] A first balanced modulation circuit that generates a first modulated color signal whose color subcarrier is phase-inverted every horizontal period;
a second balanced modulation circuit that generates a second modulated color signal in which the color subcarrier does not undergo phase inversion; and a carrier color signal that is quadrature-two-phase modulated by adding and combining the first and second modulated color signals. an upper differential pair of the first balanced modulation circuit; a buffer transistor whose emitter is connected to a collector load resistance of a differential pair transistor on the side from which the first modulated color signal is taken out, and whose base is connected to the DC offset removal capacitor; A resistor having substantially the same value as the load resistor is connected between the base and collector of the buffer transistor, and a connection point between the base of the buffer transistor and the resistor is connected to the external terminal via the external terminal. A video signal integrated circuit configured to be connected to one end of a DC offset removal capacitor and to have the other end of the DC offset removal capacitor connected to a power supply terminal.